DescriptionClarify that a trap value stored to memory stays a trap value after it's loaded back into a register, even though the side effect (for example, from a volatile store) is still undef.
Also extend trap values to cause undefined behavior when they control a conditional branch or switch. This is important for switches because it can allow the optimizer to change the default branch to unreachable. If a trap switch argument merely acted like undef, the optimizers couldn't introduce a branch to unreachable. I'm less sure that br(trap) needs to be unreachable, but it seems nicely symmetric.
Patch Set 1 #
Total comments: 2
Patch Set 2 : Tweak store trap wording #Patch Set 3 : Rearrange examples #Patch Set 4 : Reorder examples #Patch Set 5 : s/causes/results in/ #MessagesTotal messages: 2
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