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| 1 // Original source: |
| 2 // http://www.zorinaq.com/papers/md5-amd64.html |
| 3 // http://www.zorinaq.com/papers/md5-amd64.tar.bz2 |
| 4 // |
| 5 // Translated from Perl generating GNU assembly into |
| 6 // #defines generating 8a assembly, and adjusted for 386, |
| 7 // by the Go Authors. |
| 8 |
| 9 // MD5 optimized for AMD64. |
| 10 // |
| 11 // Author: Marc Bevand <bevand_m (at) epita.fr> |
| 12 // Licence: I hereby disclaim the copyright on this code and place it |
| 13 // in the public domain. |
| 14 |
| 15 #define ROUND1(a, b, c, d, index, const, shift) \ |
| 16 XORL c, BP; \ |
| 17 LEAL const(a)(DI*1), a; \ |
| 18 ANDL b, BP; \ |
| 19 XORL d, BP; \ |
| 20 MOVL (index*4)(SI), DI; \ |
| 21 ADDL BP, a; \ |
| 22 ROLL $shift, a; \ |
| 23 MOVL c, BP; \ |
| 24 ADDL b, a |
| 25 |
| 26 #define ROUND2(a, b, c, d, index, const, shift) \ |
| 27 LEAL const(a)(DI*1),a; \ |
| 28 MOVL d, DI; \ |
| 29 ANDL b, DI; \ |
| 30 MOVL d, BP; \ |
| 31 NOTL BP; \ |
| 32 ANDL c, BP; \ |
| 33 ORL DI, BP; \ |
| 34 MOVL (index*4)(SI),DI; \ |
| 35 ADDL BP, a; \ |
| 36 ROLL $shift, a; \ |
| 37 ADDL b, a |
| 38 |
| 39 #define ROUND3(a, b, c, d, index, const, shift) \ |
| 40 LEAL const(a)(DI*1),a; \ |
| 41 MOVL (index*4)(SI),DI; \ |
| 42 XORL d, BP; \ |
| 43 XORL b, BP; \ |
| 44 ADDL BP, a; \ |
| 45 ROLL $shift, a; \ |
| 46 MOVL b, BP; \ |
| 47 ADDL b, a |
| 48 |
| 49 #define ROUND4(a, b, c, d, index, const, shift) \ |
| 50 LEAL const(a)(DI*1),a; \ |
| 51 ORL b, BP; \ |
| 52 XORL c, BP; \ |
| 53 ADDL BP, a; \ |
| 54 MOVL (index*4)(SI),DI; \ |
| 55 MOVL $0xffffffff, BP; \ |
| 56 ROLL $shift, a; \ |
| 57 XORL c, BP; \ |
| 58 ADDL b, a |
| 59 |
| 60 TEXT ·block(SB),7,$24-16 |
| 61 MOVL dig+0(FP), BP |
| 62 MOVL p+4(FP), SI |
| 63 MOVL n+8(FP), DX |
| 64 SHRL $6, DX |
| 65 SHLL $6, DX |
| 66 |
| 67 LEAL (SI)(DX*1), DI |
| 68 MOVL (0*4)(BP), AX |
| 69 MOVL (1*4)(BP), BX |
| 70 MOVL (2*4)(BP), CX |
| 71 MOVL (3*4)(BP), DX |
| 72 |
| 73 CMPL SI, DI |
| 74 JEQ end |
| 75 |
| 76 MOVL DI, 16(SP) |
| 77 |
| 78 loop: |
| 79 MOVL AX, 0(SP) |
| 80 MOVL BX, 4(SP) |
| 81 MOVL CX, 8(SP) |
| 82 MOVL DX, 12(SP) |
| 83 |
| 84 MOVL (0*4)(SI), DI |
| 85 MOVL DX, BP |
| 86 |
| 87 ROUND1(AX,BX,CX,DX, 1,0xd76aa478, 7); |
| 88 ROUND1(DX,AX,BX,CX, 2,0xe8c7b756,12); |
| 89 ROUND1(CX,DX,AX,BX, 3,0x242070db,17); |
| 90 ROUND1(BX,CX,DX,AX, 4,0xc1bdceee,22); |
| 91 ROUND1(AX,BX,CX,DX, 5,0xf57c0faf, 7); |
| 92 ROUND1(DX,AX,BX,CX, 6,0x4787c62a,12); |
| 93 ROUND1(CX,DX,AX,BX, 7,0xa8304613,17); |
| 94 ROUND1(BX,CX,DX,AX, 8,0xfd469501,22); |
| 95 ROUND1(AX,BX,CX,DX, 9,0x698098d8, 7); |
| 96 ROUND1(DX,AX,BX,CX,10,0x8b44f7af,12); |
| 97 ROUND1(CX,DX,AX,BX,11,0xffff5bb1,17); |
| 98 ROUND1(BX,CX,DX,AX,12,0x895cd7be,22); |
| 99 ROUND1(AX,BX,CX,DX,13,0x6b901122, 7); |
| 100 ROUND1(DX,AX,BX,CX,14,0xfd987193,12); |
| 101 ROUND1(CX,DX,AX,BX,15,0xa679438e,17); |
| 102 ROUND1(BX,CX,DX,AX, 0,0x49b40821,22); |
| 103 |
| 104 MOVL (1*4)(SI), DI |
| 105 MOVL DX, BP |
| 106 |
| 107 ROUND2(AX,BX,CX,DX, 6,0xf61e2562, 5); |
| 108 ROUND2(DX,AX,BX,CX,11,0xc040b340, 9); |
| 109 ROUND2(CX,DX,AX,BX, 0,0x265e5a51,14); |
| 110 ROUND2(BX,CX,DX,AX, 5,0xe9b6c7aa,20); |
| 111 ROUND2(AX,BX,CX,DX,10,0xd62f105d, 5); |
| 112 ROUND2(DX,AX,BX,CX,15, 0x2441453, 9); |
| 113 ROUND2(CX,DX,AX,BX, 4,0xd8a1e681,14); |
| 114 ROUND2(BX,CX,DX,AX, 9,0xe7d3fbc8,20); |
| 115 ROUND2(AX,BX,CX,DX,14,0x21e1cde6, 5); |
| 116 ROUND2(DX,AX,BX,CX, 3,0xc33707d6, 9); |
| 117 ROUND2(CX,DX,AX,BX, 8,0xf4d50d87,14); |
| 118 ROUND2(BX,CX,DX,AX,13,0x455a14ed,20); |
| 119 ROUND2(AX,BX,CX,DX, 2,0xa9e3e905, 5); |
| 120 ROUND2(DX,AX,BX,CX, 7,0xfcefa3f8, 9); |
| 121 ROUND2(CX,DX,AX,BX,12,0x676f02d9,14); |
| 122 ROUND2(BX,CX,DX,AX, 0,0x8d2a4c8a,20); |
| 123 · |
| 124 MOVL (5*4)(SI), DI |
| 125 MOVL CX, BP |
| 126 |
| 127 ROUND3(AX,BX,CX,DX, 8,0xfffa3942, 4); |
| 128 ROUND3(DX,AX,BX,CX,11,0x8771f681,11); |
| 129 ROUND3(CX,DX,AX,BX,14,0x6d9d6122,16); |
| 130 ROUND3(BX,CX,DX,AX, 1,0xfde5380c,23); |
| 131 ROUND3(AX,BX,CX,DX, 4,0xa4beea44, 4); |
| 132 ROUND3(DX,AX,BX,CX, 7,0x4bdecfa9,11); |
| 133 ROUND3(CX,DX,AX,BX,10,0xf6bb4b60,16); |
| 134 ROUND3(BX,CX,DX,AX,13,0xbebfbc70,23); |
| 135 ROUND3(AX,BX,CX,DX, 0,0x289b7ec6, 4); |
| 136 ROUND3(DX,AX,BX,CX, 3,0xeaa127fa,11); |
| 137 ROUND3(CX,DX,AX,BX, 6,0xd4ef3085,16); |
| 138 ROUND3(BX,CX,DX,AX, 9, 0x4881d05,23); |
| 139 ROUND3(AX,BX,CX,DX,12,0xd9d4d039, 4); |
| 140 ROUND3(DX,AX,BX,CX,15,0xe6db99e5,11); |
| 141 ROUND3(CX,DX,AX,BX, 2,0x1fa27cf8,16); |
| 142 ROUND3(BX,CX,DX,AX, 0,0xc4ac5665,23); |
| 143 |
| 144 MOVL (0*4)(SI), DI |
| 145 MOVL $0xffffffff, BP |
| 146 XORL DX, BP |
| 147 |
| 148 ROUND4(AX,BX,CX,DX, 7,0xf4292244, 6); |
| 149 ROUND4(DX,AX,BX,CX,14,0x432aff97,10); |
| 150 ROUND4(CX,DX,AX,BX, 5,0xab9423a7,15); |
| 151 ROUND4(BX,CX,DX,AX,12,0xfc93a039,21); |
| 152 ROUND4(AX,BX,CX,DX, 3,0x655b59c3, 6); |
| 153 ROUND4(DX,AX,BX,CX,10,0x8f0ccc92,10); |
| 154 ROUND4(CX,DX,AX,BX, 1,0xffeff47d,15); |
| 155 ROUND4(BX,CX,DX,AX, 8,0x85845dd1,21); |
| 156 ROUND4(AX,BX,CX,DX,15,0x6fa87e4f, 6); |
| 157 ROUND4(DX,AX,BX,CX, 6,0xfe2ce6e0,10); |
| 158 ROUND4(CX,DX,AX,BX,13,0xa3014314,15); |
| 159 ROUND4(BX,CX,DX,AX, 4,0x4e0811a1,21); |
| 160 ROUND4(AX,BX,CX,DX,11,0xf7537e82, 6); |
| 161 ROUND4(DX,AX,BX,CX, 2,0xbd3af235,10); |
| 162 ROUND4(CX,DX,AX,BX, 9,0x2ad7d2bb,15); |
| 163 ROUND4(BX,CX,DX,AX, 0,0xeb86d391,21); |
| 164 |
| 165 ADDL 0(SP), AX |
| 166 ADDL 4(SP), BX |
| 167 ADDL 8(SP), CX |
| 168 ADDL 12(SP), DX |
| 169 |
| 170 ADDL $64, SI |
| 171 CMPL SI, 16(SP) |
| 172 JB loop |
| 173 |
| 174 end: |
| 175 MOVL dig+0(FP), BP |
| 176 MOVL AX, (0*4)(BP) |
| 177 MOVL BX, (1*4)(BP) |
| 178 MOVL CX, (2*4)(BP) |
| 179 MOVL DX, (3*4)(BP) |
| 180 RET |
| LEFT | RIGHT |
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