code review 6962043: cmd/dist, cmd/8g: implement GO386=387/sse to choose FPU...

src/cmd/8g/gsubr.c

 // Derived from Inferno utils/8c/txt.c
 // http://code.google.com/p/inferno-os/source/browse/utils/8c/txt.c
 //
 //      Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
 //      Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
 //      Portions Copyright © 1997-1999 Vita Nuova Limited
 //      Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com)
 //      Portions Copyright © 2004,2006 Bruce Ellis
 //      Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
 //      Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others
@@ skipping 672 matching lines @@
                 a = ACDQ;
                 break;
         }
         return a;
 }
 
 #define FCASE(a, b, c)  (((a)<<16)|((b)<<8)|(c))
 int
 foptoas(int op, Type *t, int flg)
 {
-        int et;
+        int et, a;
 
         et = simtype[t->etype];
+
+        if(use_sse)
+                goto sse;
 
         // If we need Fpop, it means we're working on
         // two different floating-point registers, not memory.
         // There the instruction only has a float64 form.
         if(flg & Fpop)
                 et = TFLOAT64;
 
         // clear Frev if unneeded
         switch(op) {
         case OADD:
@@ skipping 57 matching lines @@
                 return AFCOMDPP;
 ········
         case FCASE(OMINUS, TFLOAT32, 0):
                 return AFCHS;
         case FCASE(OMINUS, TFLOAT64, 0):
                 return AFCHS;
         }
 
         fatal("foptoas %O %T %#x", op, t, flg);
         return 0;
-}
+
+sse:
+        switch(CASE(op, et)) {
+        default:
+                fatal("foptoas-sse: no entry %O-%T", op, t);
+                break;
+
+        case CASE(OCMP, TFLOAT32):
+                a = AUCOMISS;
+                break;
+
+        case CASE(OCMP, TFLOAT64):
+                a = AUCOMISD;
+                break;
+
+        case CASE(OAS, TFLOAT32):
+                a = AMOVSS;
+                break;
+
+        case CASE(OAS, TFLOAT64):
+                a = AMOVSD;
+                break;
+
+        case CASE(OADD, TFLOAT32):
+                a = AADDSS;
+                break;
+
+        case CASE(OADD, TFLOAT64):
+                a = AADDSD;
+                break;
+
+        case CASE(OSUB, TFLOAT32):
+                a = ASUBSS;
+                break;
+
+        case CASE(OSUB, TFLOAT64):
+                a = ASUBSD;
+                break;
+
+        case CASE(OMUL, TFLOAT32):
+                a = AMULSS;
+                break;
+
+        case CASE(OMUL, TFLOAT64):
+                a = AMULSD;
+                break;
+
+        case CASE(ODIV, TFLOAT32):
+                a = ADIVSS;
+                break;
+
+        case CASE(ODIV, TFLOAT64):
+                a = ADIVSD;
+                break;
+        }
+        return a;
+}
+
 
 static  int     resvd[] =
 {
 //      D_DI,   // for movstring
 //      D_SI,   // for movstring
 
         D_AX,   // for divide
         D_CX,   // for shift
         D_DX,   // for divide
         D_SP,   // for stack
 
         D_BL,   // because D_BX can be allocated
         D_BH,
 };
 
 void
 ginit(void)
 {
         int i;
 
         for(i=0; i<nelem(reg); i++)
                 reg[i] = 1;
         for(i=D_AX; i<=D_DI; i++)
                 reg[i] = 0;
+        for(i=D_X0; i<=D_X7; i++)
+                reg[i] = 0;
         for(i=0; i<nelem(resvd); i++)
                 reg[resvd[i]]++;
 }
 
 uintptr regpc[D_NONE];
 
 void
 gclean(void)
 {
         int i;
 
         for(i=0; i<nelem(resvd); i++)
                 reg[resvd[i]]--;
 
         for(i=D_AX; i<=D_DI; i++)
                 if(reg[i])
                         yyerror("reg %R left allocated at %ux", i, regpc[i]);
+        for(i=D_X0; i<=D_X7; i++)
+                if(reg[i])
+                        yyerror("reg %R left allocated\n", i);
 }
 
 int32
 anyregalloc(void)
 {
         int i, j;
 
         for(i=D_AX; i<=D_DI; i++) {
                 if(reg[i] == 0)
                         goto ok;
                 for(j=0; j<nelem(resvd); j++)
                         if(resvd[j] == i)
                                 goto ok;
                 return 1;
         ok:;
         }
+        for(i=D_X0; i<=D_X7; i++)
+                if(reg[i])
+                        return 1;
         return 0;
 }
 
 /*
  * allocate register of type t, leave in n.
  * if o != N, o is desired fixed register.
  * caller must regfree(n).
  */
 void
 regalloc(Node *n, Type *t, Node *o)
 {
         int i, et;
 
         if(t == T)
                 fatal("regalloc: t nil");
         et = simtype[t->etype];
 
         switch(et) {
+        case TINT64:
+        case TUINT64:
+                fatal("regalloc64");
+
         case TINT8:
         case TUINT8:
         case TINT16:
         case TUINT16:
         case TINT32:
         case TUINT32:
-        case TINT64:
-        case TUINT64:
         case TPTR32:
         case TPTR64:
         case TBOOL:
                 if(o != N && o->op == OREGISTER) {
                         i = o->val.u.reg;
                         if(i >= D_AX && i <= D_DI)
                                 goto out;
                 }
                 for(i=D_AX; i<=D_DI; i++)
                         if(reg[i] == 0)
                                 goto out;
 
                 fprint(2, "registers allocated at\n");
                 for(i=D_AX; i<=D_DI; i++)
                         fprint(2, "\t%R\t%#lux\n", i, regpc[i]);
                 yyerror("out of fixed registers");
                 goto err;
 
         case TFLOAT32:
         case TFLOAT64:
-                i = D_F0;
-                goto out;
+                if(!use_sse) {
+                        i = D_F0;
+                        goto out;
+                }
+                if(o != N && o->op == OREGISTER) {
+                        i = o->val.u.reg;
+                        if(i >= D_X0 && i <= D_X7)
+                                goto out;
+                }
+                for(i=D_X0; i<=D_X7; i++)
+                        if(reg[i] == 0)
+                                goto out;
+                fprint(2, "registers allocated at\n");
+                for(i=D_X0; i<=D_X7; i++)
+                        fprint(2, "\t%R\t%#lux\n", i, regpc[i]);
+                fatal("out of floating registers");
         }
         yyerror("regalloc: unknown type %T", t);
 
 err:
         nodreg(n, t, 0);
         return;
 
 out:
         if (i == D_SP)
                 print("alloc SP\n");
@@ skipping 283 matching lines @@
 void
 memname(Node *n, Type *t)
 {
         tempname(n, t);
         strcpy(namebuf, n->sym->name);
         namebuf[0] = '.';       // keep optimizer from registerizing
         n->sym = lookup(namebuf);
         n->orig->sym = n->sym;
 }
 
+static void floatmove(Node *f, Node *t);
+static void floatmove_387(Node *f, Node *t);
+static void floatmove_sse(Node *f, Node *t);
+
 void
 gmove(Node *f, Node *t)
 {
         int a, ft, tt;
         Type *cvt;
-        Node r1, r2, t1, t2, flo, fhi, tlo, thi, con, f0, f1, ax, dx, cx;
-        Prog *p1, *p2, *p3;
+        Node r1, r2, flo, fhi, tlo, thi, con;
 
         if(debug['M'])
                 print("gmove %N -> %N\n", f, t);
 
         ft = simsimtype(f->type);
         tt = simsimtype(t->type);
         cvt = t->type;
-
+        
         if(iscomplex[ft] || iscomplex[tt]) {
                 complexmove(f, t);
+                return;
+        }
+        if(isfloat[ft] || isfloat[tt]) {
+                floatmove(f, t);
                 return;
         }
 
         // cannot have two integer memory operands;
         // except 64-bit, which always copies via registers anyway.
         if(isint[ft] && isint[tt] && !is64(f->type) && !is64(t->type) && ismem(f) && ismem(t))
                 goto hard;
 
         // convert constant to desired type
         if(f->op == OLITERAL) {
-                if(tt == TFLOAT32)
-                        convconst(&con, types[TFLOAT64], &f->val);
-                else
-                        convconst(&con, t->type, &f->val);
+                convconst(&con, t->type, &f->val);
                 f = &con;
                 ft = simsimtype(con.type);
-
-                // some constants can't move directly to memory.
-                if(ismem(t)) {
-                        // float constants come from memory.
-                        if(isfloat[tt])
-                                goto hard;
-                }
         }
 
         // value -> value copy, only one memory operand.
         // figure out the instruction to use.
         // break out of switch for one-instruction gins.
         // goto rdst for "destination must be register".
         // goto hard for "convert to cvt type first".
         // otherwise handle and return.
 
         switch(CASE(ft, tt)) {
@@ skipping 155 matching lines @@
                 splitclean();
                 return;
 
         case CASE(TUINT32, TINT64):     // zero extend uint32
         case CASE(TUINT32, TUINT64):
                 split64(t, &tlo, &thi);
                 gmove(f, &tlo);
                 gins(AMOVL, ncon(0), &thi);
                 splitclean();
                 return;
+        }
+
+        gins(a, f, t);
+        return;
+
+rsrc:
+        // requires register source
+        regalloc(&r1, f->type, t);
+        gmove(f, &r1);
+        gins(a, &r1, t);
+        regfree(&r1);
+        return;
+
+rdst:
+        // requires register destination
+        regalloc(&r1, t->type, t);
+        gins(a, f, &r1);
+        gmove(&r1, t);
+        regfree(&r1);
+        return;
+
+hard:
+        // requires register intermediate
+        regalloc(&r1, cvt, t);
+        gmove(f, &r1);
+        gmove(&r1, t);
+        regfree(&r1);
+        return;
+
+fatal:
+        // should not happen
+        fatal("gmove %N -> %N", f, t);
+}
+
+static void
+floatmove(Node *f, Node *t)
+{
+        Node r1, r2, t1, t2, tlo, thi, con, f0, f1, ax, dx, cx;
+        Type *cvt;
+        int a, ft, tt;
+        Prog *p1, *p2, *p3;
+
+        ft = simsimtype(f->type);
+        tt = simsimtype(t->type);
+        cvt = t->type;
+
+        // cannot have two floating point memory operands.
+        if(isfloat[ft] && isfloat[tt] && ismem(f) && ismem(t))
+                goto hard;
+
+        // convert constant to desired type
+        if(f->op == OLITERAL) {
+                convconst(&con, t->type, &f->val);
+                f = &con;
+                ft = simsimtype(con.type);
+
+                // some constants can't move directly to memory.
+                if(ismem(t)) {
+                        // float constants come from memory.
+                        if(isfloat[tt])
+                                goto hard;
+                }
+        }
+
+        // value -> value copy, only one memory operand.
+        // figure out the instruction to use.
+        // break out of switch for one-instruction gins.
+        // goto rdst for "destination must be register".
+        // goto hard for "convert to cvt type first".
+        // otherwise handle and return.
+
+        switch(CASE(ft, tt)) {
+        default:
+                if(use_sse)
+                        floatmove_sse(f, t);
+                else
+                        floatmove_387(f, t);
+                return;
+
+        // float to very long integer.
+        case CASE(TFLOAT32, TINT64):
+        case CASE(TFLOAT64, TINT64):
+                if(f->op == OREGISTER) {
+                        cvt = f->type;
+                        goto hardmem;
+                }
+                nodreg(&r1, types[ft], D_F0);
+                if(ft == TFLOAT32)
+                        gins(AFMOVF, f, &r1);
+                else
+                        gins(AFMOVD, f, &r1);
+
+                // set round to zero mode during conversion
+                memname(&t1, types[TUINT16]);
+                memname(&t2, types[TUINT16]);
+                gins(AFSTCW, N, &t1);
+                gins(AMOVW, ncon(0xf7f), &t2);
+                gins(AFLDCW, &t2, N);
+                if(tt == TINT16)
+                        gins(AFMOVWP, &r1, t);
+                else if(tt == TINT32)
+                        gins(AFMOVLP, &r1, t);
+                else
+                        gins(AFMOVVP, &r1, t);
+                gins(AFLDCW, &t1, N);
+                return;
+
+        case CASE(TFLOAT32, TUINT64):
+        case CASE(TFLOAT64, TUINT64):
+                if(!ismem(f)) {
+                        cvt = f->type;
+                        goto hardmem;
+                }
+                bignodes();
+                nodreg(&f0, types[ft], D_F0);
+                nodreg(&f1, types[ft], D_F0 + 1);
+                nodreg(&ax, types[TUINT16], D_AX);
+
+                if(ft == TFLOAT32)
+                        gins(AFMOVF, f, &f0);
+                else
+                        gins(AFMOVD, f, &f0);
+
+                // if 0 > v { answer = 0 }
+                gins(AFMOVD, &zerof, &f0);
+                gins(AFUCOMIP, &f0, &f1);
+                p1 = gbranch(optoas(OGT, types[tt]), T, 0);
+                // if 1<<64 <= v { answer = 0 too }
+                gins(AFMOVD, &two64f, &f0);
+                gins(AFUCOMIP, &f0, &f1);
+                p2 = gbranch(optoas(OGT, types[tt]), T, 0);
+                patch(p1, pc);
+                gins(AFMOVVP, &f0, t);  // don't care about t, but will pop the stack
+                split64(t, &tlo, &thi);
+                gins(AMOVL, ncon(0), &tlo);
+                gins(AMOVL, ncon(0), &thi);
+                splitclean();
+                p1 = gbranch(AJMP, T, 0);
+                patch(p2, pc);
+
+                // in range; algorithm is:
+                //      if small enough, use native float64 -> int64 conversion.
+                //      otherwise, subtract 2^63, convert, and add it back.
+
+                // set round to zero mode during conversion
+                memname(&t1, types[TUINT16]);
+                memname(&t2, types[TUINT16]);
+                gins(AFSTCW, N, &t1);
+                gins(AMOVW, ncon(0xf7f), &t2);
+                gins(AFLDCW, &t2, N);
+
+                // actual work
+                gins(AFMOVD, &two63f, &f0);
+                gins(AFUCOMIP, &f0, &f1);
+                p2 = gbranch(optoas(OLE, types[tt]), T, 0);
+                gins(AFMOVVP, &f0, t);
+                p3 = gbranch(AJMP, T, 0);
+                patch(p2, pc);
+                gins(AFMOVD, &two63f, &f0);
+                gins(AFSUBDP, &f0, &f1);
+                gins(AFMOVVP, &f0, t);
+                split64(t, &tlo, &thi);
+                gins(AXORL, ncon(0x80000000), &thi);    // + 2^63
+                patch(p3, pc);
+                splitclean();
+                // restore rounding mode
+                gins(AFLDCW, &t1, N);
+
+                patch(p1, pc);
+                return;
+
+        /*
+         * integer to float
+         */
+        case CASE(TINT64, TFLOAT32):
+        case CASE(TINT64, TFLOAT64):
+                if(t->op == OREGISTER)
+                        goto hardmem;
+                nodreg(&f0, t->type, D_F0);
+                gins(AFMOVV, f, &f0);
+                if(tt == TFLOAT32)
+                        gins(AFMOVFP, &f0, t);
+                else
+                        gins(AFMOVDP, &f0, t);
+                return;
+
+        case CASE(TUINT64, TFLOAT32):
+        case CASE(TUINT64, TFLOAT64):
+                // algorithm is:
+                //      if small enough, use native int64 -> float64 conversion.
+                //      otherwise, halve (rounding to odd?), convert, and double.
+                nodreg(&ax, types[TUINT32], D_AX);
+                nodreg(&dx, types[TUINT32], D_DX);
+                nodreg(&cx, types[TUINT32], D_CX);
+                tempname(&t1, f->type);
+                split64(&t1, &tlo, &thi);
+                gmove(f, &t1);
+                gins(ACMPL, &thi, ncon(0));
+                p1 = gbranch(AJLT, T, 0);
+                // native
+                t1.type = types[TINT64];
+                nodreg(&r1, types[tt], D_F0);
+                gins(AFMOVV, &t1, &r1);
+                if(tt == TFLOAT32)
+                        gins(AFMOVFP, &r1, t);
+                else
+                        gins(AFMOVDP, &r1, t);
+                p2 = gbranch(AJMP, T, 0);
+                // simulated
+                patch(p1, pc);
+                gmove(&tlo, &ax);
+                gmove(&thi, &dx);
+                p1 = gins(ASHRL, ncon(1), &ax);
+                p1->from.index = D_DX;  // double-width shift DX -> AX
+                p1->from.scale = 0;
+                gins(AMOVL, ncon(0), &cx);
+                gins(ASETCC, N, &cx);
+                gins(AORL, &cx, &ax);
+                gins(ASHRL, ncon(1), &dx);
+                gmove(&dx, &thi);
+                gmove(&ax, &tlo);
+                nodreg(&r1, types[tt], D_F0);
+                nodreg(&r2, types[tt], D_F0 + 1);
+                gins(AFMOVV, &t1, &r1);
+                gins(AFMOVD, &r1, &r1);
+                gins(AFADDDP, &r1, &r2);
+                if(tt == TFLOAT32)
+                        gins(AFMOVFP, &r1, t);
+                else
+                        gins(AFMOVDP, &r1, t);
+                patch(p2, pc);
+                splitclean();
+                return;
+        }
+
+        gins(a, f, t);
+        return;
+
+hard:
+        // requires register intermediate
+        regalloc(&r1, cvt, t);
+        gmove(f, &r1);
+        gmove(&r1, t);
+        regfree(&r1);
+        return;
+
+hardmem:
+        // requires memory intermediate
+        tempname(&r1, cvt);
+        gmove(f, &r1);
+        gmove(&r1, t);
+        return;
+}
+
+static void
+floatmove_387(Node *f, Node *t)
+{
+        Node r1, t1, t2;
+        Type *cvt;
+        Prog *p1, *p2, *p3;
+        int a, ft, tt;
+
+        ft = simsimtype(f->type);
+        tt = simsimtype(t->type);
+        cvt = t->type;
+
+        switch(CASE(ft, tt)) {
+        default:
+                goto fatal;
 
         /*
         * float to integer
         */
         case CASE(TFLOAT32, TINT16):
         case CASE(TFLOAT32, TINT32):
         case CASE(TFLOAT32, TINT64):
         case CASE(TFLOAT64, TINT16):
         case CASE(TFLOAT64, TINT32):
         case CASE(TFLOAT64, TINT64):
@@ skipping 59 matching lines @@
                         gins(AMOVL, ncon(0), &t1);
                         patch(p1, pc);
                         gmove(&t1, t);
                         break;
                 }
                 return;
 
         case CASE(TFLOAT32, TUINT32):
         case CASE(TFLOAT64, TUINT32):
                 // convert via int64.
-                tempname(&t1, types[TINT64]);
-                gmove(f, &t1);
-                split64(&t1, &tlo, &thi);
-                gins(ACMPL, &thi, ncon(0));
-                p1 = gbranch(AJEQ, T, +1);
-                gins(AMOVL, ncon(0), &tlo);
-                patch(p1, pc);
-                gmove(&tlo, t);
-                splitclean();
-                return;
-
-        case CASE(TFLOAT32, TUINT64):
-        case CASE(TFLOAT64, TUINT64):
-                bignodes();
-                nodreg(&f0, types[ft], D_F0);
-                nodreg(&f1, types[ft], D_F0 + 1);
-                nodreg(&ax, types[TUINT16], D_AX);
-
-                gmove(f, &f0);
-
-                // if 0 > v { answer = 0 }
-                gmove(&zerof, &f0);
-                gins(AFUCOMIP, &f0, &f1);
-                p1 = gbranch(optoas(OGT, types[tt]), T, 0);
-                // if 1<<64 <= v { answer = 0 too }
-                gmove(&two64f, &f0);
-                gins(AFUCOMIP, &f0, &f1);
-                p2 = gbranch(optoas(OGT, types[tt]), T, 0);
-                patch(p1, pc);
-                gins(AFMOVVP, &f0, t);  // don't care about t, but will pop the stack
-                split64(t, &tlo, &thi);
-                gins(AMOVL, ncon(0), &tlo);
-                gins(AMOVL, ncon(0), &thi);
-                splitclean();
-                p1 = gbranch(AJMP, T, 0);
-                patch(p2, pc);
-
-                // in range; algorithm is:
-                //      if small enough, use native float64 -> int64 conversion.
-                //      otherwise, subtract 2^63, convert, and add it back.
-
-                // set round to zero mode during conversion
-                memname(&t1, types[TUINT16]);
-                memname(&t2, types[TUINT16]);
-                gins(AFSTCW, N, &t1);
-                gins(AMOVW, ncon(0xf7f), &t2);
-                gins(AFLDCW, &t2, N);
-
-                // actual work
-                gmove(&two63f, &f0);
-                gins(AFUCOMIP, &f0, &f1);
-                p2 = gbranch(optoas(OLE, types[tt]), T, 0);
-                gins(AFMOVVP, &f0, t);
-                p3 = gbranch(AJMP, T, 0);
-                patch(p2, pc);
-                gmove(&two63f, &f0);
-                gins(AFSUBDP, &f0, &f1);
-                gins(AFMOVVP, &f0, t);
-                split64(t, &tlo, &thi);
-                gins(AXORL, ncon(0x80000000), &thi);    // + 2^63
-                patch(p3, pc);
-                splitclean();
-                // restore rounding mode
-                gins(AFLDCW, &t1, N);
-
-                patch(p1, pc);
-                return;
+                cvt = types[TINT64];
+                goto hardmem;
 
         /*
          * integer to float
          */
         case CASE(TINT16, TFLOAT32):
         case CASE(TINT16, TFLOAT64):
         case CASE(TINT32, TFLOAT32):
         case CASE(TINT32, TFLOAT64):
         case CASE(TINT64, TFLOAT32):
         case CASE(TINT64, TFLOAT64):
@@ skipping 24 matching lines @@
         case CASE(TUINT8, TFLOAT64):
                 // convert via int32 memory
                 cvt = types[TINT32];
                 goto hardmem;
 
         case CASE(TUINT32, TFLOAT32):
         case CASE(TUINT32, TFLOAT64):
                 // convert via int64 memory
                 cvt = types[TINT64];
                 goto hardmem;
-
-        case CASE(TUINT64, TFLOAT32):
-        case CASE(TUINT64, TFLOAT64):
-                // algorithm is:
-                //      if small enough, use native int64 -> uint64 conversion.
-                //      otherwise, halve (rounding to odd?), convert, and double.
-                nodreg(&ax, types[TUINT32], D_AX);
-                nodreg(&dx, types[TUINT32], D_DX);
-                nodreg(&cx, types[TUINT32], D_CX);
-                tempname(&t1, f->type);
-                split64(&t1, &tlo, &thi);
-                gmove(f, &t1);
-                gins(ACMPL, &thi, ncon(0));
-                p1 = gbranch(AJLT, T, 0);
-                // native
-                t1.type = types[TINT64];
-                gmove(&t1, t);
-                p2 = gbranch(AJMP, T, 0);
-                // simulated
-                patch(p1, pc);
-                gmove(&tlo, &ax);
-                gmove(&thi, &dx);
-                p1 = gins(ASHRL, ncon(1), &ax);
-                p1->from.index = D_DX;  // double-width shift DX -> AX
-                p1->from.scale = 0;
-                gins(AMOVL, ncon(0), &cx);
-                gins(ASETCC, N, &cx);
-                gins(AORL, &cx, &ax);
-                gins(ASHRL, ncon(1), &dx);
-                gmove(&dx, &thi);
-                gmove(&ax, &tlo);
-                nodreg(&r1, types[tt], D_F0);
-                nodreg(&r2, types[tt], D_F0 + 1);
-                gmove(&t1, &r1);        // t1.type is TINT64 now, set above
-                gins(AFMOVD, &r1, &r1);
-                gins(AFADDDP, &r1, &r2);
-                gmove(&r1, t);
-                patch(p2, pc);
-                splitclean();
-                return;
 
         /*
          * float to float
          */
         case CASE(TFLOAT32, TFLOAT32):
         case CASE(TFLOAT64, TFLOAT64):
                 // The way the code generator uses floating-point
                 // registers, a move from F0 to F0 is intended as a no-op.
                 // On the x86, it's not: it pushes a second copy of F0
                 // on the floating point stack.  So toss it away here.
@@ skipping 44 matching lines @@
                 if(f->op == OREGISTER)
                         gins(AFMOVFP, f, t);
                 else
                         gins(AFMOVD, f, t);
                 return;
         }
 
         gins(a, f, t);
         return;
 
-rsrc:
-        // requires register source
-        regalloc(&r1, f->type, t);
+hard:
+        // requires register intermediate
+        regalloc(&r1, cvt, t);
         gmove(f, &r1);
-        gins(a, &r1, t);
+        gmove(&r1, t);
         regfree(&r1);
+        return;
+
+hardmem:
+        // requires memory intermediate
+        tempname(&r1, cvt);
+        gmove(f, &r1);
+        gmove(&r1, t);
+        return;
+
+fatal:
+        // should not happen
+        fatal("gmove %lN -> %lN", f, t);
+        return;
+}
+
+static void
+floatmove_sse(Node *f, Node *t)
+{
+        Node r1;
+        Type *cvt;
+        int a, ft, tt;
+
+        ft = simsimtype(f->type);
+        tt = simsimtype(t->type);
+
+        switch(CASE(ft, tt)) {
+        default:
+                // should not happen
+                fatal("gmove %N -> %N", f, t);
+                return;
+        /*
+        * float to integer
+        */
+        case CASE(TFLOAT32, TINT16):
+        case CASE(TFLOAT32, TINT8):
+        case CASE(TFLOAT32, TUINT16):
+        case CASE(TFLOAT32, TUINT8):
+        case CASE(TFLOAT64, TINT16):
+        case CASE(TFLOAT64, TINT8):
+        case CASE(TFLOAT64, TUINT16):
+        case CASE(TFLOAT64, TUINT8):
+                // convert via int32.
+                cvt = types[TINT32];
+                goto hard;
+
+        case CASE(TFLOAT32, TUINT32):
+        case CASE(TFLOAT64, TUINT32):
+                // convert via int64.
+                cvt = types[TINT64];
+                goto hardmem;
+
+        case CASE(TFLOAT32, TINT32):
+                a = ACVTTSS2SL;
+                goto rdst;
+
+        case CASE(TFLOAT64, TINT32):
+                a = ACVTTSD2SL;
+                goto rdst;
+
+        /*
+         * integer to float
+         */
+        case CASE(TINT8, TFLOAT32):
+        case CASE(TINT8, TFLOAT64):
+        case CASE(TINT16, TFLOAT32):
+        case CASE(TINT16, TFLOAT64):
+        case CASE(TUINT16, TFLOAT32):
+        case CASE(TUINT16, TFLOAT64):
+        case CASE(TUINT8, TFLOAT32):
+        case CASE(TUINT8, TFLOAT64):
+                // convert via int32 memory
+                cvt = types[TINT32];
+                goto hard;
+
+        case CASE(TUINT32, TFLOAT32):
+        case CASE(TUINT32, TFLOAT64):
+                // convert via int64 memory
+                cvt = types[TINT64];
+                goto hardmem;
+
+        case CASE(TINT32, TFLOAT32):
+                a = ACVTSL2SS;
+                goto rdst;
+
+        case CASE(TINT32, TFLOAT64):
+                a = ACVTSL2SD;
+                goto rdst;
+
+        /*
+         * float to float
+         */
+        case CASE(TFLOAT32, TFLOAT32):
+                a = AMOVSS;
+                break;
+
+        case CASE(TFLOAT64, TFLOAT64):
+                a = AMOVSD;
+                break;
+
+        case CASE(TFLOAT32, TFLOAT64):
+                a = ACVTSS2SD;
+                goto rdst;
+
+        case CASE(TFLOAT64, TFLOAT32):
+                a = ACVTSD2SS;
+                goto rdst;
+        }
+
+        gins(a, f, t);
+        return;
+
+hard:
+        // requires register intermediate
+        regalloc(&r1, cvt, t);
+        gmove(f, &r1);
+        gmove(&r1, t);
+        regfree(&r1);
+        return;
+
+hardmem:
+        // requires memory intermediate
+        tempname(&r1, cvt);
+        gmove(f, &r1);
+        gmove(&r1, t);
         return;
 
 rdst:
         // requires register destination
         regalloc(&r1, t->type, t);
         gins(a, f, &r1);
         gmove(&r1, t);
         regfree(&r1);
         return;
-
-hard:
-        // requires register intermediate
-        regalloc(&r1, cvt, t);
-        gmove(f, &r1);
-        gmove(&r1, t);
-        regfree(&r1);
-        return;
-
-hardmem:
-        // requires memory intermediate
-        tempname(&r1, cvt);
-        gmove(f, &r1);
-        gmove(&r1, t);
-        return;
-
-fatal:
-        // should not happen
-        fatal("gmove %N -> %N", f, t);
 }
 
 int
 samaddr(Node *f, Node *t)
 {
 
         if(f->op != t->op)
                 return 0;
 
         switch(f->op) {
@@ skipping 10 matching lines @@
  */
 Prog*
 gins(int as, Node *f, Node *t)
 {
         Prog *p;
         Addr af, at;
         int w;
 
         if(as == AFMOVF && f && f->op == OREGISTER && t && t->op == OREGISTER)
                 fatal("gins MOVF reg, reg");
+        if(as == ACVTSD2SS && f && f->op == OLITERAL)
+                fatal("gins CVTSD2SS const");
+        if(as == AMOVSD && t && t->op == OREGISTER && t->val.u.reg == D_F0)
+                fatal("gins MOVSD into F0");
 
         switch(as) {
         case AMOVB:
         case AMOVW:
         case AMOVL:
                 if(f != N && t != N && samaddr(f, t))
                         return nil;
                 break;
 ········
         case ALEAL:
@@ skipping 283 matching lines @@
 
 int
 sudoaddable(int as, Node *n, Addr *a)
 {
         USED(as);
         USED(n);
         USED(a);
 
         return 0;
 }