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1 // Copyright 2009 The Go Authors. All rights reserved. | 1 // Copyright 2009 The Go Authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style | 2 // Use of this source code is governed by a BSD-style |
3 // license that can be found in the LICENSE file. | 3 // license that can be found in the LICENSE file. |
4 | 4 |
5 // Software floating point interpretaton of ARM 7500 FP instructions. | 5 // Software floating point interpretaton of ARM 7500 FP instructions. |
6 // The interpretation is not bit compatible with the 7500. | 6 // The interpretation is not bit compatible with the 7500. |
7 // It uses true little-endian doubles, while the 7500 used mixed-endian. | 7 // It uses true little-endian doubles, while the 7500 used mixed-endian. |
8 | 8 |
9 #include "runtime.h" | 9 #include "runtime.h" |
10 #include "../../cmd/ld/textflag.h" | 10 #include "../../cmd/ld/textflag.h" |
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194 // unconditional branch | 194 // unconditional branch |
195 // can happen in the middle of floating point | 195 // can happen in the middle of floating point |
196 // if the linker decides it is time to lay down | 196 // if the linker decides it is time to lay down |
197 // a sequence of instruction stream constants. | 197 // a sequence of instruction stream constants. |
198 delta = i&0xffffff; | 198 delta = i&0xffffff; |
199 delta = (delta<<8) >> 8; // sign extend | 199 delta = (delta<<8) >> 8; // sign extend |
200 | 200 |
201 if(trace) | 201 if(trace) |
202 runtime·printf("*** cpu PC += %x\n", (delta+2)*4); | 202 runtime·printf("*** cpu PC += %x\n", (delta+2)*4); |
203 return delta+2; | 203 return delta+2; |
| 204 } |
| 205 if(runtime·islibrary && i == 0xe08fb00b) { |
| 206 // ADD PC, R11 |
| 207 // In shared library mode, addresses in the instruction |
| 208 // stream are pc-relative, and the linker inserts |
| 209 // this instruction to convert to absolute addresses. |
| 210 regs[11] = (uint32)((uint8*)pc + regs[11] + 8); |
| 211 if(trace) |
| 212 runtime·printf("*** cpu R[%d] += PC\n", 11); |
| 213 return 1; |
204 } | 214 } |
205 | 215 |
206 goto stage1; | 216 goto stage1; |
207 | 217 |
208 stage1: // load/store regn is cpureg, regm is 8bit offset | 218 stage1: // load/store regn is cpureg, regm is 8bit offset |
209 regd = i>>12 & 0xf; | 219 regd = i>>12 & 0xf; |
210 regn = i>>16 & 0xf; | 220 regn = i>>16 & 0xf; |
211 regm = (i & 0xff) << 2; // PLUS or MINUS ?? | 221 regm = (i & 0xff) << 2; // PLUS or MINUS ?? |
212 | 222 |
213 switch(i & 0xfff00f00) { | 223 switch(i & 0xfff00f00) { |
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611 if(skip == 0) { | 621 if(skip == 0) { |
612 runtime·printf("sfloat2 %p %x\n", lr, *lr); | 622 runtime·printf("sfloat2 %p %x\n", lr, *lr); |
613 fabort(); // not ok to fail first instruction | 623 fabort(); // not ok to fail first instruction |
614 } | 624 } |
615 | 625 |
616 lr += skip; | 626 lr += skip; |
617 while(skip = stepflt(lr, (uint32*)®s.r0)) | 627 while(skip = stepflt(lr, (uint32*)®s.r0)) |
618 lr += skip; | 628 lr += skip; |
619 return lr; | 629 return lr; |
620 } | 630 } |
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