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Delta Between Two Patch Sets: x86asm/inst.go

Issue 95350044: code review 95350044: x86asm: add Plan 9 output for objdump (Closed)
Left Patch Set: Created 9 years, 10 months ago
Right Patch Set: diff -r 776945181ffa https://code.google.com/p/rsc.x86/ Created 9 years, 10 months ago
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1 // Copyright 2014 The Go Authors. All rights reserved. 1 // Copyright 2014 The Go Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style 2 // Use of this source code is governed by a BSD-style
3 // license that can be found in the LICENSE file. 3 // license that can be found in the LICENSE file.
4 4
5 // Package x86asm implements decoding of x86 machine code. 5 // Package x86asm implements decoding of x86 machine code.
6 package x86asm 6 package x86asm
7 7
8 import ( 8 import (
9 "bytes" 9 "bytes"
10 "fmt" 10 "fmt"
11 ) 11 )
12 12
13 // An Inst is a single instruction. 13 // An Inst is a single instruction.
14 type Inst struct { 14 type Inst struct {
15 Prefix Prefixes // Prefixes applied to the instruction. 15 Prefix Prefixes // Prefixes applied to the instruction.
16 Op Op // Opcode mnemonic 16 Op Op // Opcode mnemonic
17 Opcode uint32 // Encoded opcode bits, left aligned (first byte is Op code>>24, etc) 17 Opcode uint32 // Encoded opcode bits, left aligned (first byte is Op code>>24, etc)
18 Args Args // Instruction arguments, in Intel order 18 Args Args // Instruction arguments, in Intel order
19 Mode int // processor mode in bits: 16, 32, or 64 19 Mode int // processor mode in bits: 16, 32, or 64
20 AddrSize int // address size in bits: 16, 32, or 64 20 AddrSize int // address size in bits: 16, 32, or 64
21 DataSize int // operand size in bits: 16, 32, or 64 21 DataSize int // operand size in bits: 16, 32, or 64
22 MemBytes int // size of memory argument in bytes: 1, 2, 4, 8, 16, a nd so on. 22 MemBytes int // size of memory argument in bytes: 1, 2, 4, 8, 16, a nd so on.
23 Len int // length of encoded instruction in bytes
23 } 24 }
24 25
25 // Prefixes is an array of prefixes associated with a single instruction. 26 // Prefixes is an array of prefixes associated with a single instruction.
26 // The prefixes are listed in the same order as found in the instruction: 27 // The prefixes are listed in the same order as found in the instruction:
27 // each prefix byte corresponds to one slot in the array. The first zero 28 // each prefix byte corresponds to one slot in the array. The first zero
28 // in the array marks the end of the prefixes. 29 // in the array marks the end of the prefixes.
29 type Prefixes [14]Prefix 30 type Prefixes [14]Prefix
30 31
31 // A Prefix represents an Intel instruction prefix. 32 // A Prefix represents an Intel instruction prefix.
32 // The low 8 bits are the actual prefix byte encoding, 33 // The low 8 bits are the actual prefix byte encoding,
(...skipping 598 matching lines...) Expand 10 before | Expand all | Expand 10 after
631 DR15: "DR15", 632 DR15: "DR15",
632 TR0: "TR0", 633 TR0: "TR0",
633 TR1: "TR1", 634 TR1: "TR1",
634 TR2: "TR2", 635 TR2: "TR2",
635 TR3: "TR3", 636 TR3: "TR3",
636 TR4: "TR4", 637 TR4: "TR4",
637 TR5: "TR5", 638 TR5: "TR5",
638 TR6: "TR6", 639 TR6: "TR6",
639 TR7: "TR7", 640 TR7: "TR7",
640 } 641 }
LEFTRIGHT

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