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1 /* -*- Mode:C++; c-file-style:"gnu"; indent-tabs-mode:nil; -*- */ | 1 /* -*- Mode:C++; c-file-style:"gnu"; indent-tabs-mode:nil; -*- */ |
2 /* | 2 /* |
3 * Copyright (c) 2011 Centre Tecnologic de Telecomunicacions de Catalunya (CTTC) | 3 * Copyright (c) 2011 Centre Tecnologic de Telecomunicacions de Catalunya (CTTC) |
4 * | 4 * |
5 * This program is free software; you can redistribute it and/or modify | 5 * This program is free software; you can redistribute it and/or modify |
6 * it under the terms of the GNU General Public License version 2 as | 6 * it under the terms of the GNU General Public License version 2 as |
7 * published by the Free Software Foundation; | 7 * published by the Free Software Foundation; |
8 * | 8 * |
9 * This program is distributed in the hope that it will be useful, | 9 * This program is distributed in the hope that it will be useful, |
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of | 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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551 { | 551 { |
552 if ((*it) == true ) | 552 if ((*it) == true ) |
553 { | 553 { |
554 rbgAllocatedNum++; | 554 rbgAllocatedNum++; |
555 } | 555 } |
556 } | 556 } |
557 | 557 |
558 FfMacSchedSapUser::SchedDlConfigIndParameters ret; | 558 FfMacSchedSapUser::SchedDlConfigIndParameters ret; |
559 | 559 |
560 // update UL HARQ proc id | 560 // update UL HARQ proc id |
561 std::map <uint16_t, uint8_t>::iterator itProcId; | 561 for (std::map <uint16_t, uint8_t>::iterator itProcId = m_ulHarqCurrentProcessI
d.begin (); itProcId != m_ulHarqCurrentProcessId.end (); itProcId++) |
562 for (itProcId = m_ulHarqCurrentProcessId.begin (); itProcId != m_ulHarqCurrent
ProcessId.end (); itProcId++) | |
563 { | 562 { |
564 (*itProcId).second = ((*itProcId).second + 1) % HARQ_PROC_NUM; | 563 (*itProcId).second = ((*itProcId).second + 1) % HARQ_PROC_NUM; |
565 } | 564 } |
566 | 565 |
567 // RACH Allocation | 566 // RACH Allocation |
568 uint16_t rbAllocatedNum = 0; | 567 uint16_t rbAllocatedNum = 0; |
569 std::vector <bool> ulRbMap; | 568 std::vector <bool> ulRbMap; |
570 ulRbMap.resize (m_cschedCellConfig.m_ulBandwidth, false); | 569 ulRbMap.resize (m_cschedCellConfig.m_ulBandwidth, false); |
571 ulRbMap = m_ffrSapProvider->GetAvailableUlRbg (); | 570 ulRbMap = m_ffrSapProvider->GetAvailableUlRbg (); |
572 uint8_t maxContinuousUlBandwidth = 0; | 571 uint8_t maxContinuousUlBandwidth = 0; |
573 uint8_t tmpMinBandwidth = 0; | 572 uint8_t tmpMinBandwidth = 0; |
574 uint16_t ffrRbStartOffset = 0; | 573 uint8_t ffrRbStartOffset = 0; |
575 uint16_t tmpFfrRbStartOffset = 0; | 574 uint8_t tmpFfrRbStartOffset = 0; |
576 uint16_t index = 0; | 575 uint8_t index = 0; |
577 | 576 |
578 for (std::vector<bool>::iterator it = ulRbMap.begin (); it != ulRbMap.end ();
it++) | 577 for (std::vector<bool>::iterator it = ulRbMap.begin (); it != ulRbMap.end ();
it++) |
579 { | 578 { |
580 if ((*it) == true ) | 579 if ((*it) == true ) |
581 { | 580 { |
582 rbAllocatedNum++; | 581 rbAllocatedNum++; |
583 if (tmpMinBandwidth > maxContinuousUlBandwidth) | 582 if (tmpMinBandwidth > maxContinuousUlBandwidth) |
584 { | 583 { |
585 maxContinuousUlBandwidth = tmpMinBandwidth; | 584 maxContinuousUlBandwidth = tmpMinBandwidth; |
586 ffrRbStartOffset = tmpFfrRbStartOffset; | 585 ffrRbStartOffset = tmpFfrRbStartOffset; |
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598 index++; | 597 index++; |
599 } | 598 } |
600 | 599 |
601 if (tmpMinBandwidth > maxContinuousUlBandwidth) | 600 if (tmpMinBandwidth > maxContinuousUlBandwidth) |
602 { | 601 { |
603 maxContinuousUlBandwidth = tmpMinBandwidth; | 602 maxContinuousUlBandwidth = tmpMinBandwidth; |
604 ffrRbStartOffset = tmpFfrRbStartOffset; | 603 ffrRbStartOffset = tmpFfrRbStartOffset; |
605 } | 604 } |
606 | 605 |
607 m_rachAllocationMap.resize (m_cschedCellConfig.m_ulBandwidth, 0); | 606 m_rachAllocationMap.resize (m_cschedCellConfig.m_ulBandwidth, 0); |
608 uint16_t rbStart = 0; | 607 uint8_t rbStart = 0; |
609 rbStart = ffrRbStartOffset; | 608 rbStart = ffrRbStartOffset; |
610 std::vector <struct RachListElement_s>::iterator itRach; | 609 std::vector <struct RachListElement_s>::iterator itRach; |
611 for (itRach = m_rachList.begin (); itRach != m_rachList.end (); itRach++) | 610 for (itRach = m_rachList.begin (); itRach != m_rachList.end (); itRach++) |
612 { | 611 { |
613 NS_ASSERT_MSG (m_amc->GetTbSizeFromMcs (m_ulGrantMcs, m_cschedCellConfig.m
_ulBandwidth) > (*itRach).m_estimatedSize, " Default UL Grant MCS does not allow
to send RACH messages"); | 612 NS_ASSERT_MSG (m_amc->GetUlTbSizeFromMcs (m_ulGrantMcs, m_cschedCellConfig
.m_ulBandwidth) > (*itRach).m_estimatedSize, " Default UL Grant MCS does not all
ow to send RACH messages"); |
614 BuildRarListElement_s newRar; | 613 BuildRarListElement_s newRar; |
615 newRar.m_rnti = (*itRach).m_rnti; | 614 newRar.m_rnti = (*itRach).m_rnti; |
616 // DL-RACH Allocation | 615 // DL-RACH Allocation |
617 // Ideal: no needs of configuring m_dci | 616 // Ideal: no needs of configuring m_dci |
618 // UL-RACH Allocation | 617 // UL-RACH Allocation |
619 newRar.m_grant.m_rnti = newRar.m_rnti; | 618 newRar.m_grant.m_rnti = newRar.m_rnti; |
620 newRar.m_grant.m_mcs = m_ulGrantMcs; | 619 newRar.m_grant.m_mcs = m_ulGrantMcs; |
621 uint16_t rbLen = 1; | 620 uint8_t rbLen = 1; |
622 uint16_t tbSizeBits = 0; | 621 uint16_t tbSizeBits = 0; |
623 // find lowest TB size that fits UL grant estimated size | 622 // find lowest TB size that fits UL grant estimated size |
624 while ((tbSizeBits < (*itRach).m_estimatedSize) && (rbStart + rbLen < (ffr
RbStartOffset + maxContinuousUlBandwidth))) | 623 while ((tbSizeBits < (*itRach).m_estimatedSize) && (rbStart + rbLen < (ffr
RbStartOffset + maxContinuousUlBandwidth))) |
625 { | 624 { |
626 rbLen++; | 625 rbLen++; |
627 tbSizeBits = static_cast<uint16_t>(m_amc->GetTbSizeFromMcs (m_ulGrantM
cs, rbLen)); | 626 tbSizeBits = m_amc->GetUlTbSizeFromMcs (m_ulGrantMcs, rbLen); |
628 } | 627 } |
629 if (tbSizeBits < (*itRach).m_estimatedSize) | 628 if (tbSizeBits < (*itRach).m_estimatedSize) |
630 { | 629 { |
631 // no more allocation space: finish allocation | 630 // no more allocation space: finish allocation |
632 break; | 631 break; |
633 } | 632 } |
634 newRar.m_grant.m_rbStart = static_cast<uint8_t>(rbStart); | 633 newRar.m_grant.m_rbStart = rbStart; |
635 newRar.m_grant.m_rbLen = static_cast<uint8_t>(rbLen); | 634 newRar.m_grant.m_rbLen = rbLen; |
636 newRar.m_grant.m_tbSize = tbSizeBits / 8; | 635 newRar.m_grant.m_tbSize = tbSizeBits / 8; |
637 newRar.m_grant.m_hopping = false; | 636 newRar.m_grant.m_hopping = false; |
638 newRar.m_grant.m_tpc = 0; | 637 newRar.m_grant.m_tpc = 0; |
639 newRar.m_grant.m_cqiRequest = false; | 638 newRar.m_grant.m_cqiRequest = false; |
640 newRar.m_grant.m_ulDelay = false; | 639 newRar.m_grant.m_ulDelay = false; |
641 NS_LOG_INFO (this << " UL grant allocated to RNTI " << (*itRach).m_rnti <<
" rbStart " << rbStart << " rbLen " << rbLen << " MCS " << m_ulGrantMcs << " tb
Size " << newRar.m_grant.m_tbSize); | 640 NS_LOG_INFO (this << " UL grant allocated to RNTI " << (*itRach).m_rnti <<
" rbStart " << rbStart << " rbLen " << rbLen << " MCS " << m_ulGrantMcs << " tb
Size " << newRar.m_grant.m_tbSize); |
642 for (uint16_t i = rbStart; i < rbStart + rbLen; i++) | 641 for (uint16_t i = rbStart; i < rbStart + rbLen; i++) |
643 { | 642 { |
644 m_rachAllocationMap.at (i) = (*itRach).m_rnti; | 643 m_rachAllocationMap.at (i) = (*itRach).m_rnti; |
645 } | 644 } |
646 | 645 |
647 if (m_harqOn == true) | 646 if (m_harqOn == true) |
648 { | 647 { |
649 // generate UL-DCI for HARQ retransmissions | 648 // generate UL-DCI for HARQ retransmissions |
650 UlDciListElement_s uldci; | 649 UlDciListElement_s uldci; |
651 uldci.m_rnti = newRar.m_rnti; | 650 uldci.m_rnti = newRar.m_rnti; |
652 uldci.m_rbLen = static_cast<uint8_t>(rbLen); | 651 uldci.m_rbLen = rbLen; |
653 uldci.m_rbStart = (uint8_t)rbStart; | 652 uldci.m_rbStart = rbStart; |
654 uldci.m_mcs = m_ulGrantMcs; | 653 uldci.m_mcs = m_ulGrantMcs; |
655 uldci.m_tbSize = tbSizeBits / 8; | 654 uldci.m_tbSize = tbSizeBits / 8; |
656 uldci.m_ndi = 1; | 655 uldci.m_ndi = 1; |
657 uldci.m_cceIndex = 0; | 656 uldci.m_cceIndex = 0; |
658 uldci.m_aggrLevel = 1; | 657 uldci.m_aggrLevel = 1; |
659 uldci.m_ueTxAntennaSelection = 3; // antenna selection OFF | 658 uldci.m_ueTxAntennaSelection = 3; // antenna selection OFF |
660 uldci.m_hopping = false; | 659 uldci.m_hopping = false; |
661 uldci.m_n2Dmrs = 0; | 660 uldci.m_n2Dmrs = 0; |
662 uldci.m_tpc = 0; // no power control | 661 uldci.m_tpc = 0; // no power control |
663 uldci.m_cqiRequest = false; // only period CQI at this stage | 662 uldci.m_cqiRequest = false; // only period CQI at this stage |
664 uldci.m_ulIndex = 0; // TDD parameter | 663 uldci.m_ulIndex = 0; // TDD parameter |
665 uldci.m_dai = 1; // TDD parameter | 664 uldci.m_dai = 1; // TDD parameter |
666 uldci.m_freqHopping = 0; | 665 uldci.m_freqHopping = 0; |
667 uldci.m_pdcchPowerOffset = 0; // not used | 666 uldci.m_pdcchPowerOffset = 0; // not used |
668 | 667 |
669 uint8_t harqId = 0; | 668 uint8_t harqId = 0; |
670 std::map <uint16_t, uint8_t>::iterator itProcId1; | 669 std::map <uint16_t, uint8_t>::iterator itProcId; |
671 itProcId1 = m_ulHarqCurrentProcessId.find (uldci.m_rnti); | 670 itProcId = m_ulHarqCurrentProcessId.find (uldci.m_rnti); |
672 if (itProcId1 == m_ulHarqCurrentProcessId.end ()) | 671 if (itProcId == m_ulHarqCurrentProcessId.end ()) |
673 { | 672 { |
674 NS_FATAL_ERROR ("No info find in HARQ buffer for UE " << uldci.m_r
nti); | 673 NS_FATAL_ERROR ("No info find in HARQ buffer for UE " << uldci.m_r
nti); |
675 } | 674 } |
676 harqId = (*itProcId1).second; | 675 harqId = (*itProcId).second; |
677 std::map <uint16_t, UlHarqProcessesDciBuffer_t>::iterator itDci = m_ul
HarqProcessesDciBuffer.find (uldci.m_rnti); | 676 std::map <uint16_t, UlHarqProcessesDciBuffer_t>::iterator itDci = m_ul
HarqProcessesDciBuffer.find (uldci.m_rnti); |
678 if (itDci == m_ulHarqProcessesDciBuffer.end ()) | 677 if (itDci == m_ulHarqProcessesDciBuffer.end ()) |
679 { | 678 { |
680 NS_FATAL_ERROR ("Unable to find RNTI entry in UL DCI HARQ buffer f
or RNTI " << uldci.m_rnti); | 679 NS_FATAL_ERROR ("Unable to find RNTI entry in UL DCI HARQ buffer f
or RNTI " << uldci.m_rnti); |
681 } | 680 } |
682 (*itDci).second.at (harqId) = uldci; | 681 (*itDci).second.at (harqId) = uldci; |
683 } | 682 } |
684 | 683 |
685 rbStart = rbStart + rbLen; | 684 rbStart = rbStart + rbLen; |
686 ret.m_buildRarList.push_back (newRar); | 685 ret.m_buildRarList.push_back (newRar); |
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1063 | 1062 |
1064 if (itMax == m_flowStatsDl.end ()) | 1063 if (itMax == m_flowStatsDl.end ()) |
1065 { | 1064 { |
1066 // all UEs are allocated RBG or all UEs already allocated for HARQ or with
out HARQ process available | 1065 // all UEs are allocated RBG or all UEs already allocated for HARQ or with
out HARQ process available |
1067 return; | 1066 return; |
1068 } | 1067 } |
1069 else | 1068 else |
1070 { | 1069 { |
1071 // assign all RBGs to this UE | 1070 // assign all RBGs to this UE |
1072 std::vector <uint16_t> tempMap; | 1071 std::vector <uint16_t> tempMap; |
1073 for (int i = 0; i < rbgNum; i++) | 1072 for (uint16_t i = 0; i < rbgNum; i++) |
1074 { | 1073 { |
1075 if ( rbgMap.at (i) == true) // this RBG is allocated in RACH procedure | 1074 if ( rbgMap.at (i) == true) // this RBG is allocated in RACH procedure |
1076 continue; | 1075 continue; |
1077 | 1076 |
1078 if ((m_ffrSapProvider->IsDlRbgAvailableForUe (i, (*itMax).first)) == f
alse) | 1077 if ((m_ffrSapProvider->IsDlRbgAvailableForUe (i, (*itMax).first)) == f
alse) |
1079 continue; | 1078 continue; |
1080 | 1079 |
1081 tempMap.push_back (static_cast<uint16_t>(i)); | 1080 tempMap.push_back (i); |
1082 rbgMap.at (i) = true; | 1081 rbgMap.at (i) = true; |
1083 } | 1082 } |
1084 allocationMap.insert (std::pair <uint16_t, std::vector <uint16_t> > ((*itM
ax).first, tempMap)); | 1083 allocationMap.insert (std::pair <uint16_t, std::vector <uint16_t> > ((*itM
ax).first, tempMap)); |
1085 } | 1084 } |
1086 | 1085 |
1087 | 1086 |
1088 | 1087 |
1089 // generate the transmission opportunities by grouping the RBGs of the same RN
TI and | 1088 // generate the transmission opportunities by grouping the RBGs of the same RN
TI and |
1090 // creating the correspondent DCIs | 1089 // creating the correspondent DCIs |
1091 std::map <uint16_t, std::vector <uint16_t> >::iterator itMap = allocationMap.b
egin (); | 1090 std::map <uint16_t, std::vector <uint16_t> >::iterator itMap = allocationMap.b
egin (); |
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1151 else | 1150 else |
1152 { | 1151 { |
1153 for (uint8_t j = 0; j < nLayer; j++) | 1152 for (uint8_t j = 0; j < nLayer; j++) |
1154 { | 1153 { |
1155 worstCqi.at (j) = 1; // try with lowest MCS in RBG with no info on
channel | 1154 worstCqi.at (j) = 1; // try with lowest MCS in RBG with no info on
channel |
1156 } | 1155 } |
1157 } | 1156 } |
1158 uint32_t bytesTxed = 0; | 1157 uint32_t bytesTxed = 0; |
1159 for (uint8_t j = 0; j < nLayer; j++) | 1158 for (uint8_t j = 0; j < nLayer; j++) |
1160 { | 1159 { |
1161 newDci.m_mcs.push_back (static_cast<uint8_t>(m_amc->GetMcsFromCqi (wor
stCqi.at (j)))); | 1160 newDci.m_mcs.push_back (m_amc->GetMcsFromCqi (worstCqi.at (j))); |
1162 int tbSize = (m_amc->GetTbSizeFromMcs (newDci.m_mcs.at (j), RgbPerRnti
* rbgSize) / 8); // (size of TB in bytes according to table 7.1.7.2.1-1 of 36.2
13)· | 1161 int tbSize = (m_amc->GetDlTbSizeFromMcs (newDci.m_mcs.at (j), RgbPerRn
ti * rbgSize) / 8); // (size of TB in bytes according to table 7.1.7.2.1-1 of 36
.213)· |
1163 newDci.m_tbsSize.push_back (static_cast<uint16_t>(tbSize)); | 1162 newDci.m_tbsSize.push_back (static_cast<uint16_t>(tbSize)); |
1164 bytesTxed += tbSize; | 1163 bytesTxed += tbSize; |
1165 } | 1164 } |
1166 | 1165 |
1167 newDci.m_resAlloc = 0; // only allocation type 0 at this stage | 1166 newDci.m_resAlloc = 0; // only allocation type 0 at this stage |
1168 newDci.m_rbBitmap = 0; // TBD (32 bit bitmap see 7.1.6 of 36.213) | 1167 newDci.m_rbBitmap = 0; // TBD (32 bit bitmap see 7.1.6 of 36.213) |
1169 uint32_t rbgMask = 0; | 1168 uint32_t rbgMask = 0; |
1170 for (uint16_t k = 0; k < (*itMap).second.size (); k++) | 1169 for (uint16_t k = 0; k < (*itMap).second.size (); k++) |
1171 { | 1170 { |
1172 rbgMask = rbgMask + (0x1 << (*itMap).second.at (k)); | 1171 rbgMask = rbgMask + (0x1 << (*itMap).second.at (k)); |
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1518 | 1517 |
1519 | 1518 |
1520 // Divide the remaining resources equally among the active users starting from
the subsequent one served last scheduling trigger | 1519 // Divide the remaining resources equally among the active users starting from
the subsequent one served last scheduling trigger |
1521 uint16_t tempRbPerFlow = static_cast<uint16_t>((ffrUlBandwidth) / (nflows + rn
tiAllocated.size ())); | 1520 uint16_t tempRbPerFlow = static_cast<uint16_t>((ffrUlBandwidth) / (nflows + rn
tiAllocated.size ())); |
1522 uint16_t rbPerFlow = (minContinuousUlBandwidth < tempRbPerFlow) ? minContinuou
sUlBandwidth : tempRbPerFlow; | 1521 uint16_t rbPerFlow = (minContinuousUlBandwidth < tempRbPerFlow) ? minContinuou
sUlBandwidth : tempRbPerFlow; |
1523 | 1522 |
1524 if (rbPerFlow < 3) | 1523 if (rbPerFlow < 3) |
1525 { | 1524 { |
1526 rbPerFlow = 3; // at least 3 rbg per flow (till available resource) to en
sure TxOpportunity >= 7 bytes | 1525 rbPerFlow = 3; // at least 3 rbg per flow (till available resource) to en
sure TxOpportunity >= 7 bytes |
1527 } | 1526 } |
1528 int rbAllocated = 0; | 1527 uint16_t rbAllocated = 0; |
1529 | 1528 |
1530 std::map <uint16_t, tdtbfqsFlowPerf_t>::iterator itStats; | 1529 std::map <uint16_t, tdtbfqsFlowPerf_t>::iterator itStats; |
1531 if (m_nextRntiUl != 0) | 1530 if (m_nextRntiUl != 0) |
1532 { | 1531 { |
1533 for (it = m_ceBsrRxed.begin (); it != m_ceBsrRxed.end (); it++) | 1532 for (it = m_ceBsrRxed.begin (); it != m_ceBsrRxed.end (); it++) |
1534 { | 1533 { |
1535 if ((*it).first == m_nextRntiUl) | 1534 if ((*it).first == m_nextRntiUl) |
1536 { | 1535 { |
1537 break; | 1536 break; |
1538 } | 1537 } |
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1558 if (it == m_ceBsrRxed.end ()) | 1557 if (it == m_ceBsrRxed.end ()) |
1559 { | 1558 { |
1560 // restart from the first | 1559 // restart from the first |
1561 it = m_ceBsrRxed.begin (); | 1560 it = m_ceBsrRxed.begin (); |
1562 } | 1561 } |
1563 continue; | 1562 continue; |
1564 } | 1563 } |
1565 if (rbAllocated + rbPerFlow - 1 > m_cschedCellConfig.m_ulBandwidth) | 1564 if (rbAllocated + rbPerFlow - 1 > m_cschedCellConfig.m_ulBandwidth) |
1566 { | 1565 { |
1567 // limit to physical resources last resource assignment | 1566 // limit to physical resources last resource assignment |
1568 rbPerFlow = static_cast<uint16_t>(m_cschedCellConfig.m_ulBandwidth - r
bAllocated); | 1567 rbPerFlow = m_cschedCellConfig.m_ulBandwidth - rbAllocated; |
1569 // at least 3 rbg per flow to ensure TxOpportunity >= 7 bytes | 1568 // at least 3 rbg per flow to ensure TxOpportunity >= 7 bytes |
1570 if (rbPerFlow < 3) | 1569 if (rbPerFlow < 3) |
1571 { | 1570 { |
1572 // terminate allocation | 1571 // terminate allocation |
1573 rbPerFlow = 0;······ | 1572 rbPerFlow = 0;······ |
1574 } | 1573 } |
1575 } | 1574 } |
1576 | 1575 |
1577 rbAllocated = 0; | 1576 rbAllocated = 0; |
1578 UlDciListElement_s uldci; | 1577 UlDciListElement_s uldci; |
1579 uldci.m_rnti = (*it).first; | 1578 uldci.m_rnti = (*it).first; |
1580 uldci.m_rbLen = static_cast<uint8_t>(rbPerFlow); | 1579 uldci.m_rbLen = static_cast<uint8_t>(rbPerFlow); |
1581 uldci.m_rbStart = 0; | 1580 uldci.m_rbStart = 0; |
1582 bool allocated = false; | 1581 bool allocated = false; |
1583 NS_LOG_INFO (this << " RB Allocated " << rbAllocated << " rbPerFlow " << r
bPerFlow << " flows " << nflows); | 1582 NS_LOG_INFO (this << " RB Allocated " << rbAllocated << " rbPerFlow " << r
bPerFlow << " flows " << nflows); |
1584 while ((!allocated)&&((rbAllocated + rbPerFlow - m_cschedCellConfig.m_ulBa
ndwidth) < 1) && (rbPerFlow != 0)) | 1583 while ((!allocated)&&((rbAllocated + rbPerFlow - m_cschedCellConfig.m_ulBa
ndwidth) < 1) && (rbPerFlow != 0)) |
1585 { | 1584 { |
1586 // check availability | 1585 // check availability |
1587 bool free = true; | 1586 bool free = true; |
1588 for (uint16_t j = static_cast<uint16_t>(rbAllocated); j < static_cast<
uint16_t>(rbAllocated + rbPerFlow); j++) | 1587 for (uint16_t j = rbAllocated; j < rbAllocated + rbPerFlow; j++) |
1589 { | 1588 { |
1590 if (rbMap.at (j) == true) | 1589 if (rbMap.at (j) == true) |
1591 { | 1590 { |
1592 free = false; | 1591 free = false; |
1593 break; | 1592 break; |
1594 } | 1593 } |
1595 if ((m_ffrSapProvider->IsUlRbgAvailableForUe (j, (*it).first)) ==
false) | 1594 if ((m_ffrSapProvider->IsUlRbgAvailableForUe (j, (*it).first)) ==
false) |
1596 { | 1595 { |
1597 free = false; | 1596 free = false; |
1598 break; | 1597 break; |
1599 } | 1598 } |
1600 } | 1599 } |
1601 if (free) | 1600 if (free) |
1602 { | 1601 { |
1603 NS_LOG_INFO (this << "RNTI: "<< (*it).first<< " RB Allocated "
<< rbAllocated << " rbPerFlow " << rbPerFlow << " flows " << nflows); | 1602 NS_LOG_INFO (this << "RNTI: "<< (*it).first<< " RB Allocated "
<< rbAllocated << " rbPerFlow " << rbPerFlow << " flows " << nflows); |
1604 uldci.m_rbStart = static_cast<uint8_t>(rbAllocated); | 1603 uldci.m_rbStart = static_cast<uint8_t>(rbAllocated); |
1605 | 1604 |
1606 for (uint16_t j = static_cast<uint16_t>(rbAllocated); j < static_c
ast<uint16_t>(rbAllocated + rbPerFlow); j++) | 1605 for (uint16_t j = rbAllocated; j < rbAllocated + rbPerFlow; j++) |
1607 { | 1606 { |
1608 rbMap.at (j) = true; | 1607 rbMap.at (j) = true; |
1609 // store info on allocation for managing ul-cqi interpretation | 1608 // store info on allocation for managing ul-cqi interpretation |
1610 rbgAllocationMap.at (j) = (*it).first; | 1609 rbgAllocationMap.at (j) = (*it).first; |
1611 } | 1610 } |
1612 rbAllocated += rbPerFlow; | 1611 rbAllocated += rbPerFlow; |
1613 allocated = true; | 1612 allocated = true; |
1614 break; | 1613 break; |
1615 } | 1614 } |
1616 rbAllocated++; | 1615 rbAllocated++; |
1617 if (rbAllocated + rbPerFlow - 1 > m_cschedCellConfig.m_ulBandwidth) | 1616 if (rbAllocated + rbPerFlow - 1 > m_cschedCellConfig.m_ulBandwidth) |
1618 { | 1617 { |
1619 // limit to physical resources last resource assignment | 1618 // limit to physical resources last resource assignment |
1620 rbPerFlow = static_cast<uint16_t>(m_cschedCellConfig.m_ulBandwidth
- rbAllocated); | 1619 rbPerFlow = m_cschedCellConfig.m_ulBandwidth - rbAllocated; |
1621 // at least 3 rbg per flow to ensure TxOpportunity >= 7 bytes | 1620 // at least 3 rbg per flow to ensure TxOpportunity >= 7 bytes |
1622 if (rbPerFlow < 3) | 1621 if (rbPerFlow < 3) |
1623 { | 1622 { |
1624 // terminate allocation | 1623 // terminate allocation |
1625 rbPerFlow = 0;················· | 1624 rbPerFlow = 0;················· |
1626 } | 1625 } |
1627 } | 1626 } |
1628 } | 1627 } |
1629 if (!allocated) | 1628 if (!allocated) |
1630 { | 1629 { |
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1683 it = m_ceBsrRxed.begin (); | 1682 it = m_ceBsrRxed.begin (); |
1684 } | 1683 } |
1685 NS_LOG_DEBUG (this << " UE discared for CQI=0, RNTI " << uldci.m_r
nti); | 1684 NS_LOG_DEBUG (this << " UE discared for CQI=0, RNTI " << uldci.m_r
nti); |
1686 // remove UE from allocation map | 1685 // remove UE from allocation map |
1687 for (uint16_t i = uldci.m_rbStart; i < uldci.m_rbStart + uldci.m_r
bLen; i++) | 1686 for (uint16_t i = uldci.m_rbStart; i < uldci.m_rbStart + uldci.m_r
bLen; i++) |
1688 { | 1687 { |
1689 rbgAllocationMap.at (i) = 0; | 1688 rbgAllocationMap.at (i) = 0; |
1690 } | 1689 } |
1691 continue; // CQI == 0 means "out of range" (see table 7.2.3-1 of 3
6.213) | 1690 continue; // CQI == 0 means "out of range" (see table 7.2.3-1 of 3
6.213) |
1692 } | 1691 } |
1693 uldci.m_mcs = static_cast<uint8_t>(m_amc->GetMcsFromCqi (cqi)); | 1692 uldci.m_mcs = m_amc->GetMcsFromCqi (cqi); |
1694 } | 1693 } |
1695 | 1694 |
1696 uldci.m_tbSize = static_cast<uint16_t>(m_amc->GetTbSizeFromMcs (uldci.m_mc
s, rbPerFlow) / 8); | 1695 uldci.m_tbSize = (m_amc->GetUlTbSizeFromMcs (uldci.m_mcs, rbPerFlow) / 8); |
1697 UpdateUlRlcBufferInfo (uldci.m_rnti, uldci.m_tbSize); | 1696 UpdateUlRlcBufferInfo (uldci.m_rnti, uldci.m_tbSize); |
1698 uldci.m_ndi = 1; | 1697 uldci.m_ndi = 1; |
1699 uldci.m_cceIndex = 0; | 1698 uldci.m_cceIndex = 0; |
1700 uldci.m_aggrLevel = 1; | 1699 uldci.m_aggrLevel = 1; |
1701 uldci.m_ueTxAntennaSelection = 3; // antenna selection OFF | 1700 uldci.m_ueTxAntennaSelection = 3; // antenna selection OFF |
1702 uldci.m_hopping = false; | 1701 uldci.m_hopping = false; |
1703 uldci.m_n2Dmrs = 0; | 1702 uldci.m_n2Dmrs = 0; |
1704 uldci.m_tpc = 0; // no power control | 1703 uldci.m_tpc = 0; // no power control |
1705 uldci.m_cqiRequest = false; // only period CQI at this stage | 1704 uldci.m_cqiRequest = false; // only period CQI at this stage |
1706 uldci.m_ulIndex = 0; // TDD parameter | 1705 uldci.m_ulIndex = 0; // TDD parameter |
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2131 { | 2130 { |
2132 NS_LOG_FUNCTION (this << " RNTI " << rnti << " txMode " << (uint16_t)txMode); | 2131 NS_LOG_FUNCTION (this << " RNTI " << rnti << " txMode " << (uint16_t)txMode); |
2133 FfMacCschedSapUser::CschedUeConfigUpdateIndParameters params; | 2132 FfMacCschedSapUser::CschedUeConfigUpdateIndParameters params; |
2134 params.m_rnti = rnti; | 2133 params.m_rnti = rnti; |
2135 params.m_transmissionMode = txMode; | 2134 params.m_transmissionMode = txMode; |
2136 m_cschedSapUser->CschedUeConfigUpdateInd (params); | 2135 m_cschedSapUser->CschedUeConfigUpdateInd (params); |
2137 } | 2136 } |
2138 | 2137 |
2139 | 2138 |
2140 } | 2139 } |
LEFT | RIGHT |