LEFT | RIGHT |
1 // DO NOT EDIT. Generated by code.google.com/p/rsc/cmd/bundle | 1 // DO NOT EDIT. Generated by code.google.com/p/rsc/cmd/bundle |
2 // bundle -p main -x arm_ rsc.io/arm/armasm | 2 // bundle -p main -x arm_ rsc.io/arm/armasm |
3 | 3 |
4 /* decode.go */ | 4 /* decode.go */ |
5 | 5 |
6 // Copyright 2014 The Go Authors. All rights reserved. | 6 // Copyright 2014 The Go Authors. All rights reserved. |
7 // Use of this source code is governed by a BSD-style | 7 // Use of this source code is governed by a BSD-style |
8 // license that can be found in the LICENSE file. | 8 // license that can be found in the LICENSE file. |
9 | 9 |
10 package main | 10 package main |
(...skipping 119 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
130 // _pm_ means ± (usually keyed by the U bit). | 130 // _pm_ means ± (usually keyed by the U bit). |
131 // The _W suffix indicates a general addressing mode based on the P and W bits. | 131 // The _W suffix indicates a general addressing mode based on the P and W bits. |
132 // The _offset and _postindex suffixes force the given addressing mode. | 132 // The _offset and _postindex suffixes force the given addressing mode. |
133 // The rest should be somewhat self-explanatory, at least given | 133 // The rest should be somewhat self-explanatory, at least given |
134 // the decodeArg function. | 134 // the decodeArg function. |
135 type arm_instArg uint8 | 135 type arm_instArg uint8 |
136 | 136 |
137 const ( | 137 const ( |
138 _ arm_instArg = iota | 138 _ arm_instArg = iota |
139 arm_arg_APSR | 139 arm_arg_APSR |
| 140 arm_arg_FPSCR |
| 141 arm_arg_Dn_half |
140 arm_arg_R1_0 | 142 arm_arg_R1_0 |
141 arm_arg_R1_12 | 143 arm_arg_R1_12 |
142 arm_arg_R2_0 | 144 arm_arg_R2_0 |
143 arm_arg_R2_12 | 145 arm_arg_R2_12 |
144 arm_arg_R_0 | 146 arm_arg_R_0 |
145 arm_arg_R_12 | 147 arm_arg_R_12 |
| 148 arm_arg_R_12_nzcv |
146 arm_arg_R_16 | 149 arm_arg_R_16 |
147 arm_arg_R_16_WB | 150 arm_arg_R_16_WB |
148 arm_arg_R_8 | 151 arm_arg_R_8 |
149 arm_arg_R_rotate | 152 arm_arg_R_rotate |
150 arm_arg_R_shift_R | 153 arm_arg_R_shift_R |
151 arm_arg_R_shift_imm | 154 arm_arg_R_shift_imm |
152 arm_arg_SP | 155 arm_arg_SP |
| 156 arm_arg_Sd |
| 157 arm_arg_Sd_Dd |
| 158 arm_arg_Dd_Sd |
| 159 arm_arg_Sm |
| 160 arm_arg_Sm_Dm |
| 161 arm_arg_Sn |
| 162 arm_arg_Sn_Dn |
153 arm_arg_const | 163 arm_arg_const |
154 arm_arg_endian | 164 arm_arg_endian |
| 165 arm_arg_fbits |
| 166 arm_arg_fp_0 |
155 arm_arg_imm24 | 167 arm_arg_imm24 |
156 arm_arg_imm5 | 168 arm_arg_imm5 |
157 arm_arg_imm5_32 | 169 arm_arg_imm5_32 |
158 arm_arg_imm5_nz | 170 arm_arg_imm5_nz |
159 arm_arg_imm_12at8_4at0 | 171 arm_arg_imm_12at8_4at0 |
160 arm_arg_imm_4at16_12at0 | 172 arm_arg_imm_4at16_12at0 |
| 173 arm_arg_imm_vfp |
161 arm_arg_label24 | 174 arm_arg_label24 |
162 arm_arg_label24H | 175 arm_arg_label24H |
163 arm_arg_label_m_12 | 176 arm_arg_label_m_12 |
164 arm_arg_label_p_12 | 177 arm_arg_label_p_12 |
165 arm_arg_label_pm_12 | 178 arm_arg_label_pm_12 |
166 arm_arg_label_pm_4_4 | 179 arm_arg_label_pm_4_4 |
167 arm_arg_lsb_width | 180 arm_arg_lsb_width |
168 arm_arg_mem_R | 181 arm_arg_mem_R |
169 arm_arg_mem_R_pm_R_W | 182 arm_arg_mem_R_pm_R_W |
170 arm_arg_mem_R_pm_R_postindex | 183 arm_arg_mem_R_pm_R_postindex |
171 arm_arg_mem_R_pm_R_shift_imm_W | 184 arm_arg_mem_R_pm_R_shift_imm_W |
172 arm_arg_mem_R_pm_R_shift_imm_offset | 185 arm_arg_mem_R_pm_R_shift_imm_offset |
173 arm_arg_mem_R_pm_R_shift_imm_postindex | 186 arm_arg_mem_R_pm_R_shift_imm_postindex |
174 arm_arg_mem_R_pm_imm12_W | 187 arm_arg_mem_R_pm_imm12_W |
175 arm_arg_mem_R_pm_imm12_offset | 188 arm_arg_mem_R_pm_imm12_offset |
176 arm_arg_mem_R_pm_imm12_postindex | 189 arm_arg_mem_R_pm_imm12_postindex |
177 arm_arg_mem_R_pm_imm8_W | 190 arm_arg_mem_R_pm_imm8_W |
178 arm_arg_mem_R_pm_imm8_postindex | 191 arm_arg_mem_R_pm_imm8_postindex |
| 192 arm_arg_mem_R_pm_imm8at0_offset |
179 arm_arg_option | 193 arm_arg_option |
180 arm_arg_registers | 194 arm_arg_registers |
181 arm_arg_registers1 | 195 arm_arg_registers1 |
182 arm_arg_registers2 | 196 arm_arg_registers2 |
183 arm_arg_satimm4 | 197 arm_arg_satimm4 |
184 arm_arg_satimm5 | 198 arm_arg_satimm5 |
185 arm_arg_satimm4m1 | 199 arm_arg_satimm4m1 |
186 arm_arg_satimm5m1 | 200 arm_arg_satimm5m1 |
187 arm_arg_widthm1 | 201 arm_arg_widthm1 |
188 ) | 202 ) |
189 | 203 |
190 // decodeArg decodes the arg described by aop from the instruction bits x. | 204 // decodeArg decodes the arg described by aop from the instruction bits x. |
191 // It returns nil if x cannot be decoded according to aop. | 205 // It returns nil if x cannot be decoded according to aop. |
192 func arm_decodeArg(aop arm_instArg, x uint32) arm_Arg { | 206 func arm_decodeArg(aop arm_instArg, x uint32) arm_Arg { |
193 switch aop { | 207 switch aop { |
194 default: | 208 default: |
195 return nil | 209 return nil |
196 | 210 |
197 case arm_arg_APSR: | 211 case arm_arg_APSR: |
198 return arm_APSR | 212 return arm_APSR |
| 213 case arm_arg_FPSCR: |
| 214 return arm_FPSCR |
199 | 215 |
200 case arm_arg_R_0: | 216 case arm_arg_R_0: |
201 return arm_Reg(x & (1<<4 - 1)) | 217 return arm_Reg(x & (1<<4 - 1)) |
202 case arm_arg_R_8: | 218 case arm_arg_R_8: |
203 return arm_Reg((x >> 8) & (1<<4 - 1)) | 219 return arm_Reg((x >> 8) & (1<<4 - 1)) |
204 case arm_arg_R_12: | 220 case arm_arg_R_12: |
205 return arm_Reg((x >> 12) & (1<<4 - 1)) | 221 return arm_Reg((x >> 12) & (1<<4 - 1)) |
206 case arm_arg_R_16: | 222 case arm_arg_R_16: |
207 return arm_Reg((x >> 16) & (1<<4 - 1)) | 223 return arm_Reg((x >> 16) & (1<<4 - 1)) |
208 | 224 |
| 225 case arm_arg_R_12_nzcv: |
| 226 r := arm_Reg((x >> 12) & (1<<4 - 1)) |
| 227 if r == arm_R15 { |
| 228 return arm_APSR_nzcv |
| 229 } |
| 230 return r |
| 231 |
209 case arm_arg_R_16_WB: | 232 case arm_arg_R_16_WB: |
210 mode := arm_AddrLDM | 233 mode := arm_AddrLDM |
211 if (x>>21)&1 != 0 { | 234 if (x>>21)&1 != 0 { |
212 mode = arm_AddrLDM_WB | 235 mode = arm_AddrLDM_WB |
213 } | 236 } |
214 return arm_Mem{Base: arm_Reg((x >> 16) & (1<<4 - 1)), Mode: mode
} | 237 return arm_Mem{Base: arm_Reg((x >> 16) & (1<<4 - 1)), Mode: mode
} |
215 | 238 |
216 case arm_arg_R_rotate: | 239 case arm_arg_R_rotate: |
217 Rm := arm_Reg(x & (1<<4 - 1)) | 240 Rm := arm_Reg(x & (1<<4 - 1)) |
218 typ, count := arm_decodeShift(x) | 241 typ, count := arm_decodeShift(x) |
(...skipping 21 matching lines...) Expand all Loading... |
240 return arm_Reg((x & (1<<4 - 1))) | 263 return arm_Reg((x & (1<<4 - 1))) |
241 case arm_arg_R1_12: | 264 case arm_arg_R1_12: |
242 return arm_Reg(((x >> 12) & (1<<4 - 1))) | 265 return arm_Reg(((x >> 12) & (1<<4 - 1))) |
243 case arm_arg_R2_0: | 266 case arm_arg_R2_0: |
244 return arm_Reg((x & (1<<4 - 1)) | 1) | 267 return arm_Reg((x & (1<<4 - 1)) | 1) |
245 case arm_arg_R2_12: | 268 case arm_arg_R2_12: |
246 return arm_Reg(((x >> 12) & (1<<4 - 1)) | 1) | 269 return arm_Reg(((x >> 12) & (1<<4 - 1)) | 1) |
247 | 270 |
248 case arm_arg_SP: | 271 case arm_arg_SP: |
249 return arm_SP | 272 return arm_SP |
| 273 |
| 274 case arm_arg_Sd_Dd: |
| 275 v := (x >> 12) & (1<<4 - 1) |
| 276 vx := (x >> 22) & 1 |
| 277 sz := (x >> 8) & 1 |
| 278 if sz != 0 { |
| 279 return arm_D0 + arm_Reg(vx<<4+v) |
| 280 } else { |
| 281 return arm_S0 + arm_Reg(v<<1+vx) |
| 282 } |
| 283 |
| 284 case arm_arg_Dd_Sd: |
| 285 return arm_decodeArg(arm_arg_Sd_Dd, x^(1<<8)) |
| 286 |
| 287 case arm_arg_Sd: |
| 288 v := (x >> 12) & (1<<4 - 1) |
| 289 vx := (x >> 22) & 1 |
| 290 return arm_S0 + arm_Reg(v<<1+vx) |
| 291 |
| 292 case arm_arg_Sm_Dm: |
| 293 v := (x >> 0) & (1<<4 - 1) |
| 294 vx := (x >> 5) & 1 |
| 295 sz := (x >> 8) & 1 |
| 296 if sz != 0 { |
| 297 return arm_D0 + arm_Reg(vx<<4+v) |
| 298 } else { |
| 299 return arm_S0 + arm_Reg(v<<1+vx) |
| 300 } |
| 301 |
| 302 case arm_arg_Sm: |
| 303 v := (x >> 0) & (1<<4 - 1) |
| 304 vx := (x >> 5) & 1 |
| 305 return arm_S0 + arm_Reg(v<<1+vx) |
| 306 |
| 307 case arm_arg_Dn_half: |
| 308 v := (x >> 16) & (1<<4 - 1) |
| 309 vx := (x >> 7) & 1 |
| 310 return arm_RegX{arm_D0 + arm_Reg(vx<<4+v), int((x >> 21) & 1)} |
| 311 |
| 312 case arm_arg_Sn_Dn: |
| 313 v := (x >> 16) & (1<<4 - 1) |
| 314 vx := (x >> 7) & 1 |
| 315 sz := (x >> 8) & 1 |
| 316 if sz != 0 { |
| 317 return arm_D0 + arm_Reg(vx<<4+v) |
| 318 } else { |
| 319 return arm_S0 + arm_Reg(v<<1+vx) |
| 320 } |
| 321 |
| 322 case arm_arg_Sn: |
| 323 v := (x >> 16) & (1<<4 - 1) |
| 324 vx := (x >> 7) & 1 |
| 325 return arm_S0 + arm_Reg(v<<1+vx) |
250 | 326 |
251 case arm_arg_const: | 327 case arm_arg_const: |
252 v := x & (1<<8 - 1) | 328 v := x & (1<<8 - 1) |
253 rot := (x >> 8) & (1<<4 - 1) * 2 | 329 rot := (x >> 8) & (1<<4 - 1) * 2 |
254 if rot > 0 && v&3 == 0 { | 330 if rot > 0 && v&3 == 0 { |
255 // could rotate less | 331 // could rotate less |
256 return arm_ImmAlt{uint8(v), uint8(rot)} | 332 return arm_ImmAlt{uint8(v), uint8(rot)} |
257 } | 333 } |
258 if rot >= 24 && ((v<<(32-rot))&0xFF)>>(32-rot) == v { | 334 if rot >= 24 && ((v<<(32-rot))&0xFF)>>(32-rot) == v { |
259 // could wrap around to rot==0. | 335 // could wrap around to rot==0. |
260 return arm_ImmAlt{uint8(v), uint8(rot)} | 336 return arm_ImmAlt{uint8(v), uint8(rot)} |
261 } | 337 } |
262 return arm_Imm(v>>rot | v<<(32-rot)) | 338 return arm_Imm(v>>rot | v<<(32-rot)) |
263 | 339 |
264 case arm_arg_endian: | 340 case arm_arg_endian: |
265 return arm_Endian((x >> 9) & 1) | 341 return arm_Endian((x >> 9) & 1) |
266 | 342 |
| 343 case arm_arg_fbits: |
| 344 return arm_Imm((16 << ((x >> 7) & 1)) - ((x&(1<<4-1))<<1 | (x>>5
)&1)) |
| 345 |
| 346 case arm_arg_fp_0: |
| 347 return arm_Imm(0) |
| 348 |
267 case arm_arg_imm24: | 349 case arm_arg_imm24: |
268 return arm_Imm(x & (1<<24 - 1)) | 350 return arm_Imm(x & (1<<24 - 1)) |
269 | 351 |
270 case arm_arg_imm5: | 352 case arm_arg_imm5: |
271 return arm_Imm((x >> 7) & (1<<5 - 1)) | 353 return arm_Imm((x >> 7) & (1<<5 - 1)) |
272 | 354 |
273 case arm_arg_imm5_32: | 355 case arm_arg_imm5_32: |
274 x = (x >> 7) & (1<<5 - 1) | 356 x = (x >> 7) & (1<<5 - 1) |
275 if x == 0 { | 357 if x == 0 { |
276 x = 32 | 358 x = 32 |
277 } | 359 } |
278 return arm_Imm(x) | 360 return arm_Imm(x) |
279 | 361 |
280 case arm_arg_imm5_nz: | 362 case arm_arg_imm5_nz: |
281 x = (x >> 7) & (1<<5 - 1) | 363 x = (x >> 7) & (1<<5 - 1) |
282 if x == 0 { | 364 if x == 0 { |
283 return nil | 365 return nil |
284 } | 366 } |
285 return arm_Imm(x) | 367 return arm_Imm(x) |
286 | 368 |
287 case arm_arg_imm_4at16_12at0: | 369 case arm_arg_imm_4at16_12at0: |
288 return arm_Imm((x>>16)&(1<<4-1)<<12 | x&(1<<12-1)) | 370 return arm_Imm((x>>16)&(1<<4-1)<<12 | x&(1<<12-1)) |
289 | 371 |
290 case arm_arg_imm_12at8_4at0: | 372 case arm_arg_imm_12at8_4at0: |
291 return arm_Imm((x>>8)&(1<<12-1)<<4 | x&(1<<4-1)) | 373 return arm_Imm((x>>8)&(1<<12-1)<<4 | x&(1<<4-1)) |
| 374 |
| 375 case arm_arg_imm_vfp: |
| 376 x = (x>>16)&(1<<4-1)<<4 | x&(1<<4-1) |
| 377 return arm_Imm(x) |
292 | 378 |
293 case arm_arg_label24: | 379 case arm_arg_label24: |
294 imm := (x & (1<<24 - 1)) << 2 | 380 imm := (x & (1<<24 - 1)) << 2 |
295 return arm_PCRel(int32(imm<<6) >> 6) | 381 return arm_PCRel(int32(imm<<6) >> 6) |
296 | 382 |
297 case arm_arg_label24H: | 383 case arm_arg_label24H: |
298 h := (x >> 24) & 1 | 384 h := (x >> 24) & 1 |
299 imm := (x&(1<<24-1))<<2 | h<<1 | 385 imm := (x&(1<<24-1))<<2 | h<<1 |
300 return arm_PCRel(int32(imm<<6) >> 6) | 386 return arm_PCRel(int32(imm<<6) >> 6) |
301 | 387 |
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411 if p == 0 && w == 1 { | 497 if p == 0 && w == 1 { |
412 return nil | 498 return nil |
413 } | 499 } |
414 sign := int8(+1) | 500 sign := int8(+1) |
415 if u == 0 { | 501 if u == 0 { |
416 sign = -1 | 502 sign = -1 |
417 } | 503 } |
418 imm := int16((x>>8)&(1<<4-1)<<4 | x&(1<<4-1)) | 504 imm := int16((x>>8)&(1<<4-1)<<4 | x&(1<<4-1)) |
419 mode := arm_AddrMode(uint8(p<<1) | uint8(w^1)) | 505 mode := arm_AddrMode(uint8(p<<1) | uint8(w^1)) |
420 return arm_Mem{Base: Rn, Mode: mode, Offset: int16(sign) * imm} | 506 return arm_Mem{Base: Rn, Mode: mode, Offset: int16(sign) * imm} |
| 507 |
| 508 case arm_arg_mem_R_pm_imm8at0_offset: |
| 509 Rn := arm_Reg((x >> 16) & (1<<4 - 1)) |
| 510 u := (x >> 23) & 1 |
| 511 sign := int8(+1) |
| 512 if u == 0 { |
| 513 sign = -1 |
| 514 } |
| 515 imm := int16(x&(1<<8-1)) << 2 |
| 516 return arm_Mem{Base: Rn, Mode: arm_AddrOffset, Offset: int16(sig
n) * imm} |
421 | 517 |
422 case arm_arg_option: | 518 case arm_arg_option: |
423 return arm_Imm(x & (1<<4 - 1)) | 519 return arm_Imm(x & (1<<4 - 1)) |
424 | 520 |
425 case arm_arg_registers: | 521 case arm_arg_registers: |
426 return arm_RegList(x & (1<<16 - 1)) | 522 return arm_RegList(x & (1<<16 - 1)) |
427 | 523 |
428 case arm_arg_registers2: | 524 case arm_arg_registers2: |
429 x &= 1<<16 - 1 | 525 x &= 1<<16 - 1 |
430 n := 0 | 526 n := 0 |
(...skipping 46 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
477 } | 573 } |
478 return typ, uint8(count) | 574 return typ, uint8(count) |
479 } | 575 } |
480 | 576 |
481 /* gnu.go */ | 577 /* gnu.go */ |
482 | 578 |
483 // Copyright 2014 The Go Authors. All rights reserved. | 579 // Copyright 2014 The Go Authors. All rights reserved. |
484 // Use of this source code is governed by a BSD-style | 580 // Use of this source code is governed by a BSD-style |
485 // license that can be found in the LICENSE file. | 581 // license that can be found in the LICENSE file. |
486 | 582 |
| 583 var arm_saveDot = strings.NewReplacer( |
| 584 ".F16", "_dot_F16", |
| 585 ".F32", "_dot_F32", |
| 586 ".F64", "_dot_F64", |
| 587 ".S32", "_dot_S32", |
| 588 ".U32", "_dot_U32", |
| 589 ".FXS", "_dot_S", |
| 590 ".FXU", "_dot_U", |
| 591 ".32", "_dot_32", |
| 592 ) |
| 593 |
487 // GNUSyntax returns the GNU assembler syntax for the instruction, as defined by
GNU binutils. | 594 // GNUSyntax returns the GNU assembler syntax for the instruction, as defined by
GNU binutils. |
488 // This form typically matches the syntax defined in the ARM Reference Manual. | 595 // This form typically matches the syntax defined in the ARM Reference Manual. |
489 func arm_GNUSyntax(inst arm_Inst) string { | 596 func arm_GNUSyntax(inst arm_Inst) string { |
490 var buf bytes.Buffer | 597 var buf bytes.Buffer |
491 op := inst.Op.String() | 598 op := inst.Op.String() |
| 599 op = arm_saveDot.Replace(op) |
492 op = strings.Replace(op, ".", "", -1) | 600 op = strings.Replace(op, ".", "", -1) |
| 601 op = strings.Replace(op, "_dot_", ".", -1) |
493 op = strings.ToLower(op) | 602 op = strings.ToLower(op) |
494 buf.WriteString(op) | 603 buf.WriteString(op) |
495 sep := " " | 604 sep := " " |
496 for i, arg := range inst.Args { | 605 for i, arg := range inst.Args { |
497 if arg == nil { | 606 if arg == nil { |
498 break | 607 break |
499 } | 608 } |
500 text := arm_gnuArg(&inst, i, arg) | 609 text := arm_gnuArg(&inst, i, arg) |
501 if text == "" { | 610 if text == "" { |
502 continue | 611 continue |
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694 // the final elements in the array are nil. | 803 // the final elements in the array are nil. |
695 type arm_Args [4]arm_Arg | 804 type arm_Args [4]arm_Arg |
696 | 805 |
697 // An Arg is a single instruction argument, one of these types: | 806 // An Arg is a single instruction argument, one of these types: |
698 // Endian, Imm, Mem, PCRel, Reg, RegList, RegShift, RegShiftReg. | 807 // Endian, Imm, Mem, PCRel, Reg, RegList, RegShift, RegShiftReg. |
699 type arm_Arg interface { | 808 type arm_Arg interface { |
700 IsArg() | 809 IsArg() |
701 String() string | 810 String() string |
702 } | 811 } |
703 | 812 |
| 813 type arm_Float32Imm float32 |
| 814 |
| 815 func (arm_Float32Imm) IsArg() {} |
| 816 |
| 817 func (f arm_Float32Imm) String() string { |
| 818 return fmt.Sprintf("#%v", float32(f)) |
| 819 } |
| 820 |
| 821 type arm_Float64Imm float32 |
| 822 |
| 823 func (arm_Float64Imm) IsArg() {} |
| 824 |
| 825 func (f arm_Float64Imm) String() string { |
| 826 return fmt.Sprintf("#%v", float64(f)) |
| 827 } |
| 828 |
704 // An Imm is an integer constant. | 829 // An Imm is an integer constant. |
705 type arm_Imm uint32 | 830 type arm_Imm uint32 |
706 | 831 |
707 func (arm_Imm) IsArg() {} | 832 func (arm_Imm) IsArg() {} |
708 | 833 |
709 func (i arm_Imm) String() string { | 834 func (i arm_Imm) String() string { |
710 return fmt.Sprintf("#%#x", uint32(i)) | 835 return fmt.Sprintf("#%#x", uint32(i)) |
711 } | 836 } |
712 | 837 |
713 // A ImmAlt is an alternate encoding of an integer constant. | 838 // A ImmAlt is an alternate encoding of an integer constant. |
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751 arm_R6 | 876 arm_R6 |
752 arm_R7 | 877 arm_R7 |
753 arm_R8 | 878 arm_R8 |
754 arm_R9 | 879 arm_R9 |
755 arm_R10 | 880 arm_R10 |
756 arm_R11 | 881 arm_R11 |
757 arm_R12 | 882 arm_R12 |
758 arm_R13 | 883 arm_R13 |
759 arm_R14 | 884 arm_R14 |
760 arm_R15 | 885 arm_R15 |
| 886 |
| 887 arm_S0 |
| 888 arm_S1 |
| 889 arm_S2 |
| 890 arm_S3 |
| 891 arm_S4 |
| 892 arm_S5 |
| 893 arm_S6 |
| 894 arm_S7 |
| 895 arm_S8 |
| 896 arm_S9 |
| 897 arm_S10 |
| 898 arm_S11 |
| 899 arm_S12 |
| 900 arm_S13 |
| 901 arm_S14 |
| 902 arm_S15 |
| 903 arm_S16 |
| 904 arm_S17 |
| 905 arm_S18 |
| 906 arm_S19 |
| 907 arm_S20 |
| 908 arm_S21 |
| 909 arm_S22 |
| 910 arm_S23 |
| 911 arm_S24 |
| 912 arm_S25 |
| 913 arm_S26 |
| 914 arm_S27 |
| 915 arm_S28 |
| 916 arm_S29 |
| 917 arm_S30 |
| 918 arm_S31 |
| 919 |
| 920 arm_D0 |
| 921 arm_D1 |
| 922 arm_D2 |
| 923 arm_D3 |
| 924 arm_D4 |
| 925 arm_D5 |
| 926 arm_D6 |
| 927 arm_D7 |
| 928 arm_D8 |
| 929 arm_D9 |
| 930 arm_D10 |
| 931 arm_D11 |
| 932 arm_D12 |
| 933 arm_D13 |
| 934 arm_D14 |
| 935 arm_D15 |
| 936 arm_D16 |
| 937 arm_D17 |
| 938 arm_D18 |
| 939 arm_D19 |
| 940 arm_D20 |
| 941 arm_D21 |
| 942 arm_D22 |
| 943 arm_D23 |
| 944 arm_D24 |
| 945 arm_D25 |
| 946 arm_D26 |
| 947 arm_D27 |
| 948 arm_D28 |
| 949 arm_D29 |
| 950 arm_D30 |
| 951 arm_D31 |
| 952 |
761 arm_APSR | 953 arm_APSR |
| 954 arm_APSR_nzcv |
| 955 arm_FPSCR |
762 | 956 |
763 arm_SP = arm_R13 | 957 arm_SP = arm_R13 |
764 arm_LR = arm_R14 | 958 arm_LR = arm_R14 |
765 arm_PC = arm_R15 | 959 arm_PC = arm_R15 |
766 ) | 960 ) |
767 | 961 |
768 func (arm_Reg) IsArg() {} | 962 func (arm_Reg) IsArg() {} |
769 | 963 |
770 func (r arm_Reg) String() string { | 964 func (r arm_Reg) String() string { |
771 switch r { | 965 switch r { |
772 case arm_APSR: | 966 case arm_APSR: |
773 return "APSR" | 967 return "APSR" |
| 968 case arm_APSR_nzcv: |
| 969 return "APSR_nzcv" |
| 970 case arm_FPSCR: |
| 971 return "FPSCR" |
774 case arm_SP: | 972 case arm_SP: |
775 return "SP" | 973 return "SP" |
776 case arm_PC: | 974 case arm_PC: |
777 return "PC" | 975 return "PC" |
778 case arm_LR: | 976 case arm_LR: |
779 return "LR" | 977 return "LR" |
780 } | 978 } |
781 » if r < 16 { | 979 » if arm_R0 <= r && r <= arm_R15 { |
782 » » return fmt.Sprintf("R%d", int(r)) | 980 » » return fmt.Sprintf("R%d", int(r-arm_R0)) |
| 981 » } |
| 982 » if arm_S0 <= r && r <= arm_S31 { |
| 983 » » return fmt.Sprintf("S%d", int(r-arm_S0)) |
| 984 » } |
| 985 » if arm_D0 <= r && r <= arm_D31 { |
| 986 » » return fmt.Sprintf("D%d", int(r-arm_D0)) |
783 } | 987 } |
784 return fmt.Sprintf("Reg(%d)", int(r)) | 988 return fmt.Sprintf("Reg(%d)", int(r)) |
| 989 } |
| 990 |
| 991 // A RegX represents a fraction of a multi-value register. |
| 992 // The Index field specifies the index number, |
| 993 // but the size of the fraction is not specified. |
| 994 // It must be inferred from the instruction and the register type. |
| 995 // For example, in a VMOV instruction, RegX{D5, 1} represents |
| 996 // the top 32 bits of the 64-bit D5 register. |
| 997 type arm_RegX struct { |
| 998 Reg arm_Reg |
| 999 Index int |
| 1000 } |
| 1001 |
| 1002 func (arm_RegX) IsArg() {} |
| 1003 |
| 1004 func (r arm_RegX) String() string { |
| 1005 return fmt.Sprintf("%s[%d]", r.Reg, r.Index) |
785 } | 1006 } |
786 | 1007 |
787 // A RegList is a register list. | 1008 // A RegList is a register list. |
788 // Bits at indexes x = 0 through 15 indicate whether the corresponding Rx regist
er is in the list. | 1009 // Bits at indexes x = 0 through 15 indicate whether the corresponding Rx regist
er is in the list. |
789 type arm_RegList uint16 | 1010 type arm_RegList uint16 |
790 | 1011 |
791 func (arm_RegList) IsArg() {} | 1012 func (arm_RegList) IsArg() {} |
792 | 1013 |
793 func (r arm_RegList) String() string { | 1014 func (r arm_RegList) String() string { |
794 var buf bytes.Buffer | 1015 var buf bytes.Buffer |
(...skipping 3455 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
4250 arm_UMULL_S_VS | 4471 arm_UMULL_S_VS |
4251 arm_UMULL_S_VC | 4472 arm_UMULL_S_VC |
4252 arm_UMULL_S_HI | 4473 arm_UMULL_S_HI |
4253 arm_UMULL_S_LS | 4474 arm_UMULL_S_LS |
4254 arm_UMULL_S_GE | 4475 arm_UMULL_S_GE |
4255 arm_UMULL_S_LT | 4476 arm_UMULL_S_LT |
4256 arm_UMULL_S_GT | 4477 arm_UMULL_S_GT |
4257 arm_UMULL_S_LE | 4478 arm_UMULL_S_LE |
4258 arm_UMULL_S | 4479 arm_UMULL_S |
4259 arm_UMULL_S_ZZ | 4480 arm_UMULL_S_ZZ |
| 4481 arm_UNDEF |
| 4482 _ |
| 4483 _ |
| 4484 _ |
| 4485 _ |
| 4486 _ |
| 4487 _ |
| 4488 _ |
| 4489 _ |
| 4490 _ |
| 4491 _ |
| 4492 _ |
| 4493 _ |
| 4494 _ |
| 4495 _ |
| 4496 _ |
4260 arm_UQADD16_EQ | 4497 arm_UQADD16_EQ |
4261 arm_UQADD16_NE | 4498 arm_UQADD16_NE |
4262 arm_UQADD16_CS | 4499 arm_UQADD16_CS |
4263 arm_UQADD16_CC | 4500 arm_UQADD16_CC |
4264 arm_UQADD16_MI | 4501 arm_UQADD16_MI |
4265 arm_UQADD16_PL | 4502 arm_UQADD16_PL |
4266 arm_UQADD16_VS | 4503 arm_UQADD16_VS |
4267 arm_UQADD16_VC | 4504 arm_UQADD16_VC |
4268 arm_UQADD16_HI | 4505 arm_UQADD16_HI |
4269 arm_UQADD16_LS | 4506 arm_UQADD16_LS |
(...skipping 284 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
4554 arm_UXTH_VS | 4791 arm_UXTH_VS |
4555 arm_UXTH_VC | 4792 arm_UXTH_VC |
4556 arm_UXTH_HI | 4793 arm_UXTH_HI |
4557 arm_UXTH_LS | 4794 arm_UXTH_LS |
4558 arm_UXTH_GE | 4795 arm_UXTH_GE |
4559 arm_UXTH_LT | 4796 arm_UXTH_LT |
4560 arm_UXTH_GT | 4797 arm_UXTH_GT |
4561 arm_UXTH_LE | 4798 arm_UXTH_LE |
4562 arm_UXTH | 4799 arm_UXTH |
4563 arm_UXTH_ZZ | 4800 arm_UXTH_ZZ |
| 4801 arm_VABS_EQ_F32 |
| 4802 arm_VABS_NE_F32 |
| 4803 arm_VABS_CS_F32 |
| 4804 arm_VABS_CC_F32 |
| 4805 arm_VABS_MI_F32 |
| 4806 arm_VABS_PL_F32 |
| 4807 arm_VABS_VS_F32 |
| 4808 arm_VABS_VC_F32 |
| 4809 arm_VABS_HI_F32 |
| 4810 arm_VABS_LS_F32 |
| 4811 arm_VABS_GE_F32 |
| 4812 arm_VABS_LT_F32 |
| 4813 arm_VABS_GT_F32 |
| 4814 arm_VABS_LE_F32 |
| 4815 arm_VABS_F32 |
| 4816 arm_VABS_ZZ_F32 |
| 4817 arm_VABS_EQ_F64 |
| 4818 arm_VABS_NE_F64 |
| 4819 arm_VABS_CS_F64 |
| 4820 arm_VABS_CC_F64 |
| 4821 arm_VABS_MI_F64 |
| 4822 arm_VABS_PL_F64 |
| 4823 arm_VABS_VS_F64 |
| 4824 arm_VABS_VC_F64 |
| 4825 arm_VABS_HI_F64 |
| 4826 arm_VABS_LS_F64 |
| 4827 arm_VABS_GE_F64 |
| 4828 arm_VABS_LT_F64 |
| 4829 arm_VABS_GT_F64 |
| 4830 arm_VABS_LE_F64 |
| 4831 arm_VABS_F64 |
| 4832 arm_VABS_ZZ_F64 |
| 4833 arm_VADD_EQ_F32 |
| 4834 arm_VADD_NE_F32 |
| 4835 arm_VADD_CS_F32 |
| 4836 arm_VADD_CC_F32 |
| 4837 arm_VADD_MI_F32 |
| 4838 arm_VADD_PL_F32 |
| 4839 arm_VADD_VS_F32 |
| 4840 arm_VADD_VC_F32 |
| 4841 arm_VADD_HI_F32 |
| 4842 arm_VADD_LS_F32 |
| 4843 arm_VADD_GE_F32 |
| 4844 arm_VADD_LT_F32 |
| 4845 arm_VADD_GT_F32 |
| 4846 arm_VADD_LE_F32 |
| 4847 arm_VADD_F32 |
| 4848 arm_VADD_ZZ_F32 |
| 4849 arm_VADD_EQ_F64 |
| 4850 arm_VADD_NE_F64 |
| 4851 arm_VADD_CS_F64 |
| 4852 arm_VADD_CC_F64 |
| 4853 arm_VADD_MI_F64 |
| 4854 arm_VADD_PL_F64 |
| 4855 arm_VADD_VS_F64 |
| 4856 arm_VADD_VC_F64 |
| 4857 arm_VADD_HI_F64 |
| 4858 arm_VADD_LS_F64 |
| 4859 arm_VADD_GE_F64 |
| 4860 arm_VADD_LT_F64 |
| 4861 arm_VADD_GT_F64 |
| 4862 arm_VADD_LE_F64 |
| 4863 arm_VADD_F64 |
| 4864 arm_VADD_ZZ_F64 |
| 4865 arm_VCMP_EQ_F32 |
| 4866 arm_VCMP_NE_F32 |
| 4867 arm_VCMP_CS_F32 |
| 4868 arm_VCMP_CC_F32 |
| 4869 arm_VCMP_MI_F32 |
| 4870 arm_VCMP_PL_F32 |
| 4871 arm_VCMP_VS_F32 |
| 4872 arm_VCMP_VC_F32 |
| 4873 arm_VCMP_HI_F32 |
| 4874 arm_VCMP_LS_F32 |
| 4875 arm_VCMP_GE_F32 |
| 4876 arm_VCMP_LT_F32 |
| 4877 arm_VCMP_GT_F32 |
| 4878 arm_VCMP_LE_F32 |
| 4879 arm_VCMP_F32 |
| 4880 arm_VCMP_ZZ_F32 |
| 4881 arm_VCMP_EQ_F64 |
| 4882 arm_VCMP_NE_F64 |
| 4883 arm_VCMP_CS_F64 |
| 4884 arm_VCMP_CC_F64 |
| 4885 arm_VCMP_MI_F64 |
| 4886 arm_VCMP_PL_F64 |
| 4887 arm_VCMP_VS_F64 |
| 4888 arm_VCMP_VC_F64 |
| 4889 arm_VCMP_HI_F64 |
| 4890 arm_VCMP_LS_F64 |
| 4891 arm_VCMP_GE_F64 |
| 4892 arm_VCMP_LT_F64 |
| 4893 arm_VCMP_GT_F64 |
| 4894 arm_VCMP_LE_F64 |
| 4895 arm_VCMP_F64 |
| 4896 arm_VCMP_ZZ_F64 |
| 4897 arm_VCMP_E_EQ_F32 |
| 4898 arm_VCMP_E_NE_F32 |
| 4899 arm_VCMP_E_CS_F32 |
| 4900 arm_VCMP_E_CC_F32 |
| 4901 arm_VCMP_E_MI_F32 |
| 4902 arm_VCMP_E_PL_F32 |
| 4903 arm_VCMP_E_VS_F32 |
| 4904 arm_VCMP_E_VC_F32 |
| 4905 arm_VCMP_E_HI_F32 |
| 4906 arm_VCMP_E_LS_F32 |
| 4907 arm_VCMP_E_GE_F32 |
| 4908 arm_VCMP_E_LT_F32 |
| 4909 arm_VCMP_E_GT_F32 |
| 4910 arm_VCMP_E_LE_F32 |
| 4911 arm_VCMP_E_F32 |
| 4912 arm_VCMP_E_ZZ_F32 |
| 4913 arm_VCMP_E_EQ_F64 |
| 4914 arm_VCMP_E_NE_F64 |
| 4915 arm_VCMP_E_CS_F64 |
| 4916 arm_VCMP_E_CC_F64 |
| 4917 arm_VCMP_E_MI_F64 |
| 4918 arm_VCMP_E_PL_F64 |
| 4919 arm_VCMP_E_VS_F64 |
| 4920 arm_VCMP_E_VC_F64 |
| 4921 arm_VCMP_E_HI_F64 |
| 4922 arm_VCMP_E_LS_F64 |
| 4923 arm_VCMP_E_GE_F64 |
| 4924 arm_VCMP_E_LT_F64 |
| 4925 arm_VCMP_E_GT_F64 |
| 4926 arm_VCMP_E_LE_F64 |
| 4927 arm_VCMP_E_F64 |
| 4928 arm_VCMP_E_ZZ_F64 |
| 4929 arm_VCVT_EQ_F32_FXS16 |
| 4930 arm_VCVT_NE_F32_FXS16 |
| 4931 arm_VCVT_CS_F32_FXS16 |
| 4932 arm_VCVT_CC_F32_FXS16 |
| 4933 arm_VCVT_MI_F32_FXS16 |
| 4934 arm_VCVT_PL_F32_FXS16 |
| 4935 arm_VCVT_VS_F32_FXS16 |
| 4936 arm_VCVT_VC_F32_FXS16 |
| 4937 arm_VCVT_HI_F32_FXS16 |
| 4938 arm_VCVT_LS_F32_FXS16 |
| 4939 arm_VCVT_GE_F32_FXS16 |
| 4940 arm_VCVT_LT_F32_FXS16 |
| 4941 arm_VCVT_GT_F32_FXS16 |
| 4942 arm_VCVT_LE_F32_FXS16 |
| 4943 arm_VCVT_F32_FXS16 |
| 4944 arm_VCVT_ZZ_F32_FXS16 |
| 4945 arm_VCVT_EQ_F32_FXS32 |
| 4946 arm_VCVT_NE_F32_FXS32 |
| 4947 arm_VCVT_CS_F32_FXS32 |
| 4948 arm_VCVT_CC_F32_FXS32 |
| 4949 arm_VCVT_MI_F32_FXS32 |
| 4950 arm_VCVT_PL_F32_FXS32 |
| 4951 arm_VCVT_VS_F32_FXS32 |
| 4952 arm_VCVT_VC_F32_FXS32 |
| 4953 arm_VCVT_HI_F32_FXS32 |
| 4954 arm_VCVT_LS_F32_FXS32 |
| 4955 arm_VCVT_GE_F32_FXS32 |
| 4956 arm_VCVT_LT_F32_FXS32 |
| 4957 arm_VCVT_GT_F32_FXS32 |
| 4958 arm_VCVT_LE_F32_FXS32 |
| 4959 arm_VCVT_F32_FXS32 |
| 4960 arm_VCVT_ZZ_F32_FXS32 |
| 4961 arm_VCVT_EQ_F32_FXU16 |
| 4962 arm_VCVT_NE_F32_FXU16 |
| 4963 arm_VCVT_CS_F32_FXU16 |
| 4964 arm_VCVT_CC_F32_FXU16 |
| 4965 arm_VCVT_MI_F32_FXU16 |
| 4966 arm_VCVT_PL_F32_FXU16 |
| 4967 arm_VCVT_VS_F32_FXU16 |
| 4968 arm_VCVT_VC_F32_FXU16 |
| 4969 arm_VCVT_HI_F32_FXU16 |
| 4970 arm_VCVT_LS_F32_FXU16 |
| 4971 arm_VCVT_GE_F32_FXU16 |
| 4972 arm_VCVT_LT_F32_FXU16 |
| 4973 arm_VCVT_GT_F32_FXU16 |
| 4974 arm_VCVT_LE_F32_FXU16 |
| 4975 arm_VCVT_F32_FXU16 |
| 4976 arm_VCVT_ZZ_F32_FXU16 |
| 4977 arm_VCVT_EQ_F32_FXU32 |
| 4978 arm_VCVT_NE_F32_FXU32 |
| 4979 arm_VCVT_CS_F32_FXU32 |
| 4980 arm_VCVT_CC_F32_FXU32 |
| 4981 arm_VCVT_MI_F32_FXU32 |
| 4982 arm_VCVT_PL_F32_FXU32 |
| 4983 arm_VCVT_VS_F32_FXU32 |
| 4984 arm_VCVT_VC_F32_FXU32 |
| 4985 arm_VCVT_HI_F32_FXU32 |
| 4986 arm_VCVT_LS_F32_FXU32 |
| 4987 arm_VCVT_GE_F32_FXU32 |
| 4988 arm_VCVT_LT_F32_FXU32 |
| 4989 arm_VCVT_GT_F32_FXU32 |
| 4990 arm_VCVT_LE_F32_FXU32 |
| 4991 arm_VCVT_F32_FXU32 |
| 4992 arm_VCVT_ZZ_F32_FXU32 |
| 4993 arm_VCVT_EQ_F64_FXS16 |
| 4994 arm_VCVT_NE_F64_FXS16 |
| 4995 arm_VCVT_CS_F64_FXS16 |
| 4996 arm_VCVT_CC_F64_FXS16 |
| 4997 arm_VCVT_MI_F64_FXS16 |
| 4998 arm_VCVT_PL_F64_FXS16 |
| 4999 arm_VCVT_VS_F64_FXS16 |
| 5000 arm_VCVT_VC_F64_FXS16 |
| 5001 arm_VCVT_HI_F64_FXS16 |
| 5002 arm_VCVT_LS_F64_FXS16 |
| 5003 arm_VCVT_GE_F64_FXS16 |
| 5004 arm_VCVT_LT_F64_FXS16 |
| 5005 arm_VCVT_GT_F64_FXS16 |
| 5006 arm_VCVT_LE_F64_FXS16 |
| 5007 arm_VCVT_F64_FXS16 |
| 5008 arm_VCVT_ZZ_F64_FXS16 |
| 5009 arm_VCVT_EQ_F64_FXS32 |
| 5010 arm_VCVT_NE_F64_FXS32 |
| 5011 arm_VCVT_CS_F64_FXS32 |
| 5012 arm_VCVT_CC_F64_FXS32 |
| 5013 arm_VCVT_MI_F64_FXS32 |
| 5014 arm_VCVT_PL_F64_FXS32 |
| 5015 arm_VCVT_VS_F64_FXS32 |
| 5016 arm_VCVT_VC_F64_FXS32 |
| 5017 arm_VCVT_HI_F64_FXS32 |
| 5018 arm_VCVT_LS_F64_FXS32 |
| 5019 arm_VCVT_GE_F64_FXS32 |
| 5020 arm_VCVT_LT_F64_FXS32 |
| 5021 arm_VCVT_GT_F64_FXS32 |
| 5022 arm_VCVT_LE_F64_FXS32 |
| 5023 arm_VCVT_F64_FXS32 |
| 5024 arm_VCVT_ZZ_F64_FXS32 |
| 5025 arm_VCVT_EQ_F64_FXU16 |
| 5026 arm_VCVT_NE_F64_FXU16 |
| 5027 arm_VCVT_CS_F64_FXU16 |
| 5028 arm_VCVT_CC_F64_FXU16 |
| 5029 arm_VCVT_MI_F64_FXU16 |
| 5030 arm_VCVT_PL_F64_FXU16 |
| 5031 arm_VCVT_VS_F64_FXU16 |
| 5032 arm_VCVT_VC_F64_FXU16 |
| 5033 arm_VCVT_HI_F64_FXU16 |
| 5034 arm_VCVT_LS_F64_FXU16 |
| 5035 arm_VCVT_GE_F64_FXU16 |
| 5036 arm_VCVT_LT_F64_FXU16 |
| 5037 arm_VCVT_GT_F64_FXU16 |
| 5038 arm_VCVT_LE_F64_FXU16 |
| 5039 arm_VCVT_F64_FXU16 |
| 5040 arm_VCVT_ZZ_F64_FXU16 |
| 5041 arm_VCVT_EQ_F64_FXU32 |
| 5042 arm_VCVT_NE_F64_FXU32 |
| 5043 arm_VCVT_CS_F64_FXU32 |
| 5044 arm_VCVT_CC_F64_FXU32 |
| 5045 arm_VCVT_MI_F64_FXU32 |
| 5046 arm_VCVT_PL_F64_FXU32 |
| 5047 arm_VCVT_VS_F64_FXU32 |
| 5048 arm_VCVT_VC_F64_FXU32 |
| 5049 arm_VCVT_HI_F64_FXU32 |
| 5050 arm_VCVT_LS_F64_FXU32 |
| 5051 arm_VCVT_GE_F64_FXU32 |
| 5052 arm_VCVT_LT_F64_FXU32 |
| 5053 arm_VCVT_GT_F64_FXU32 |
| 5054 arm_VCVT_LE_F64_FXU32 |
| 5055 arm_VCVT_F64_FXU32 |
| 5056 arm_VCVT_ZZ_F64_FXU32 |
| 5057 arm_VCVT_EQ_F32_U32 |
| 5058 arm_VCVT_NE_F32_U32 |
| 5059 arm_VCVT_CS_F32_U32 |
| 5060 arm_VCVT_CC_F32_U32 |
| 5061 arm_VCVT_MI_F32_U32 |
| 5062 arm_VCVT_PL_F32_U32 |
| 5063 arm_VCVT_VS_F32_U32 |
| 5064 arm_VCVT_VC_F32_U32 |
| 5065 arm_VCVT_HI_F32_U32 |
| 5066 arm_VCVT_LS_F32_U32 |
| 5067 arm_VCVT_GE_F32_U32 |
| 5068 arm_VCVT_LT_F32_U32 |
| 5069 arm_VCVT_GT_F32_U32 |
| 5070 arm_VCVT_LE_F32_U32 |
| 5071 arm_VCVT_F32_U32 |
| 5072 arm_VCVT_ZZ_F32_U32 |
| 5073 arm_VCVT_EQ_F32_S32 |
| 5074 arm_VCVT_NE_F32_S32 |
| 5075 arm_VCVT_CS_F32_S32 |
| 5076 arm_VCVT_CC_F32_S32 |
| 5077 arm_VCVT_MI_F32_S32 |
| 5078 arm_VCVT_PL_F32_S32 |
| 5079 arm_VCVT_VS_F32_S32 |
| 5080 arm_VCVT_VC_F32_S32 |
| 5081 arm_VCVT_HI_F32_S32 |
| 5082 arm_VCVT_LS_F32_S32 |
| 5083 arm_VCVT_GE_F32_S32 |
| 5084 arm_VCVT_LT_F32_S32 |
| 5085 arm_VCVT_GT_F32_S32 |
| 5086 arm_VCVT_LE_F32_S32 |
| 5087 arm_VCVT_F32_S32 |
| 5088 arm_VCVT_ZZ_F32_S32 |
| 5089 arm_VCVT_EQ_F64_U32 |
| 5090 arm_VCVT_NE_F64_U32 |
| 5091 arm_VCVT_CS_F64_U32 |
| 5092 arm_VCVT_CC_F64_U32 |
| 5093 arm_VCVT_MI_F64_U32 |
| 5094 arm_VCVT_PL_F64_U32 |
| 5095 arm_VCVT_VS_F64_U32 |
| 5096 arm_VCVT_VC_F64_U32 |
| 5097 arm_VCVT_HI_F64_U32 |
| 5098 arm_VCVT_LS_F64_U32 |
| 5099 arm_VCVT_GE_F64_U32 |
| 5100 arm_VCVT_LT_F64_U32 |
| 5101 arm_VCVT_GT_F64_U32 |
| 5102 arm_VCVT_LE_F64_U32 |
| 5103 arm_VCVT_F64_U32 |
| 5104 arm_VCVT_ZZ_F64_U32 |
| 5105 arm_VCVT_EQ_F64_S32 |
| 5106 arm_VCVT_NE_F64_S32 |
| 5107 arm_VCVT_CS_F64_S32 |
| 5108 arm_VCVT_CC_F64_S32 |
| 5109 arm_VCVT_MI_F64_S32 |
| 5110 arm_VCVT_PL_F64_S32 |
| 5111 arm_VCVT_VS_F64_S32 |
| 5112 arm_VCVT_VC_F64_S32 |
| 5113 arm_VCVT_HI_F64_S32 |
| 5114 arm_VCVT_LS_F64_S32 |
| 5115 arm_VCVT_GE_F64_S32 |
| 5116 arm_VCVT_LT_F64_S32 |
| 5117 arm_VCVT_GT_F64_S32 |
| 5118 arm_VCVT_LE_F64_S32 |
| 5119 arm_VCVT_F64_S32 |
| 5120 arm_VCVT_ZZ_F64_S32 |
| 5121 arm_VCVT_EQ_F64_F32 |
| 5122 arm_VCVT_NE_F64_F32 |
| 5123 arm_VCVT_CS_F64_F32 |
| 5124 arm_VCVT_CC_F64_F32 |
| 5125 arm_VCVT_MI_F64_F32 |
| 5126 arm_VCVT_PL_F64_F32 |
| 5127 arm_VCVT_VS_F64_F32 |
| 5128 arm_VCVT_VC_F64_F32 |
| 5129 arm_VCVT_HI_F64_F32 |
| 5130 arm_VCVT_LS_F64_F32 |
| 5131 arm_VCVT_GE_F64_F32 |
| 5132 arm_VCVT_LT_F64_F32 |
| 5133 arm_VCVT_GT_F64_F32 |
| 5134 arm_VCVT_LE_F64_F32 |
| 5135 arm_VCVT_F64_F32 |
| 5136 arm_VCVT_ZZ_F64_F32 |
| 5137 arm_VCVT_EQ_F32_F64 |
| 5138 arm_VCVT_NE_F32_F64 |
| 5139 arm_VCVT_CS_F32_F64 |
| 5140 arm_VCVT_CC_F32_F64 |
| 5141 arm_VCVT_MI_F32_F64 |
| 5142 arm_VCVT_PL_F32_F64 |
| 5143 arm_VCVT_VS_F32_F64 |
| 5144 arm_VCVT_VC_F32_F64 |
| 5145 arm_VCVT_HI_F32_F64 |
| 5146 arm_VCVT_LS_F32_F64 |
| 5147 arm_VCVT_GE_F32_F64 |
| 5148 arm_VCVT_LT_F32_F64 |
| 5149 arm_VCVT_GT_F32_F64 |
| 5150 arm_VCVT_LE_F32_F64 |
| 5151 arm_VCVT_F32_F64 |
| 5152 arm_VCVT_ZZ_F32_F64 |
| 5153 arm_VCVT_EQ_FXS16_F32 |
| 5154 arm_VCVT_NE_FXS16_F32 |
| 5155 arm_VCVT_CS_FXS16_F32 |
| 5156 arm_VCVT_CC_FXS16_F32 |
| 5157 arm_VCVT_MI_FXS16_F32 |
| 5158 arm_VCVT_PL_FXS16_F32 |
| 5159 arm_VCVT_VS_FXS16_F32 |
| 5160 arm_VCVT_VC_FXS16_F32 |
| 5161 arm_VCVT_HI_FXS16_F32 |
| 5162 arm_VCVT_LS_FXS16_F32 |
| 5163 arm_VCVT_GE_FXS16_F32 |
| 5164 arm_VCVT_LT_FXS16_F32 |
| 5165 arm_VCVT_GT_FXS16_F32 |
| 5166 arm_VCVT_LE_FXS16_F32 |
| 5167 arm_VCVT_FXS16_F32 |
| 5168 arm_VCVT_ZZ_FXS16_F32 |
| 5169 arm_VCVT_EQ_FXS16_F64 |
| 5170 arm_VCVT_NE_FXS16_F64 |
| 5171 arm_VCVT_CS_FXS16_F64 |
| 5172 arm_VCVT_CC_FXS16_F64 |
| 5173 arm_VCVT_MI_FXS16_F64 |
| 5174 arm_VCVT_PL_FXS16_F64 |
| 5175 arm_VCVT_VS_FXS16_F64 |
| 5176 arm_VCVT_VC_FXS16_F64 |
| 5177 arm_VCVT_HI_FXS16_F64 |
| 5178 arm_VCVT_LS_FXS16_F64 |
| 5179 arm_VCVT_GE_FXS16_F64 |
| 5180 arm_VCVT_LT_FXS16_F64 |
| 5181 arm_VCVT_GT_FXS16_F64 |
| 5182 arm_VCVT_LE_FXS16_F64 |
| 5183 arm_VCVT_FXS16_F64 |
| 5184 arm_VCVT_ZZ_FXS16_F64 |
| 5185 arm_VCVT_EQ_FXS32_F32 |
| 5186 arm_VCVT_NE_FXS32_F32 |
| 5187 arm_VCVT_CS_FXS32_F32 |
| 5188 arm_VCVT_CC_FXS32_F32 |
| 5189 arm_VCVT_MI_FXS32_F32 |
| 5190 arm_VCVT_PL_FXS32_F32 |
| 5191 arm_VCVT_VS_FXS32_F32 |
| 5192 arm_VCVT_VC_FXS32_F32 |
| 5193 arm_VCVT_HI_FXS32_F32 |
| 5194 arm_VCVT_LS_FXS32_F32 |
| 5195 arm_VCVT_GE_FXS32_F32 |
| 5196 arm_VCVT_LT_FXS32_F32 |
| 5197 arm_VCVT_GT_FXS32_F32 |
| 5198 arm_VCVT_LE_FXS32_F32 |
| 5199 arm_VCVT_FXS32_F32 |
| 5200 arm_VCVT_ZZ_FXS32_F32 |
| 5201 arm_VCVT_EQ_FXS32_F64 |
| 5202 arm_VCVT_NE_FXS32_F64 |
| 5203 arm_VCVT_CS_FXS32_F64 |
| 5204 arm_VCVT_CC_FXS32_F64 |
| 5205 arm_VCVT_MI_FXS32_F64 |
| 5206 arm_VCVT_PL_FXS32_F64 |
| 5207 arm_VCVT_VS_FXS32_F64 |
| 5208 arm_VCVT_VC_FXS32_F64 |
| 5209 arm_VCVT_HI_FXS32_F64 |
| 5210 arm_VCVT_LS_FXS32_F64 |
| 5211 arm_VCVT_GE_FXS32_F64 |
| 5212 arm_VCVT_LT_FXS32_F64 |
| 5213 arm_VCVT_GT_FXS32_F64 |
| 5214 arm_VCVT_LE_FXS32_F64 |
| 5215 arm_VCVT_FXS32_F64 |
| 5216 arm_VCVT_ZZ_FXS32_F64 |
| 5217 arm_VCVT_EQ_FXU16_F32 |
| 5218 arm_VCVT_NE_FXU16_F32 |
| 5219 arm_VCVT_CS_FXU16_F32 |
| 5220 arm_VCVT_CC_FXU16_F32 |
| 5221 arm_VCVT_MI_FXU16_F32 |
| 5222 arm_VCVT_PL_FXU16_F32 |
| 5223 arm_VCVT_VS_FXU16_F32 |
| 5224 arm_VCVT_VC_FXU16_F32 |
| 5225 arm_VCVT_HI_FXU16_F32 |
| 5226 arm_VCVT_LS_FXU16_F32 |
| 5227 arm_VCVT_GE_FXU16_F32 |
| 5228 arm_VCVT_LT_FXU16_F32 |
| 5229 arm_VCVT_GT_FXU16_F32 |
| 5230 arm_VCVT_LE_FXU16_F32 |
| 5231 arm_VCVT_FXU16_F32 |
| 5232 arm_VCVT_ZZ_FXU16_F32 |
| 5233 arm_VCVT_EQ_FXU16_F64 |
| 5234 arm_VCVT_NE_FXU16_F64 |
| 5235 arm_VCVT_CS_FXU16_F64 |
| 5236 arm_VCVT_CC_FXU16_F64 |
| 5237 arm_VCVT_MI_FXU16_F64 |
| 5238 arm_VCVT_PL_FXU16_F64 |
| 5239 arm_VCVT_VS_FXU16_F64 |
| 5240 arm_VCVT_VC_FXU16_F64 |
| 5241 arm_VCVT_HI_FXU16_F64 |
| 5242 arm_VCVT_LS_FXU16_F64 |
| 5243 arm_VCVT_GE_FXU16_F64 |
| 5244 arm_VCVT_LT_FXU16_F64 |
| 5245 arm_VCVT_GT_FXU16_F64 |
| 5246 arm_VCVT_LE_FXU16_F64 |
| 5247 arm_VCVT_FXU16_F64 |
| 5248 arm_VCVT_ZZ_FXU16_F64 |
| 5249 arm_VCVT_EQ_FXU32_F32 |
| 5250 arm_VCVT_NE_FXU32_F32 |
| 5251 arm_VCVT_CS_FXU32_F32 |
| 5252 arm_VCVT_CC_FXU32_F32 |
| 5253 arm_VCVT_MI_FXU32_F32 |
| 5254 arm_VCVT_PL_FXU32_F32 |
| 5255 arm_VCVT_VS_FXU32_F32 |
| 5256 arm_VCVT_VC_FXU32_F32 |
| 5257 arm_VCVT_HI_FXU32_F32 |
| 5258 arm_VCVT_LS_FXU32_F32 |
| 5259 arm_VCVT_GE_FXU32_F32 |
| 5260 arm_VCVT_LT_FXU32_F32 |
| 5261 arm_VCVT_GT_FXU32_F32 |
| 5262 arm_VCVT_LE_FXU32_F32 |
| 5263 arm_VCVT_FXU32_F32 |
| 5264 arm_VCVT_ZZ_FXU32_F32 |
| 5265 arm_VCVT_EQ_FXU32_F64 |
| 5266 arm_VCVT_NE_FXU32_F64 |
| 5267 arm_VCVT_CS_FXU32_F64 |
| 5268 arm_VCVT_CC_FXU32_F64 |
| 5269 arm_VCVT_MI_FXU32_F64 |
| 5270 arm_VCVT_PL_FXU32_F64 |
| 5271 arm_VCVT_VS_FXU32_F64 |
| 5272 arm_VCVT_VC_FXU32_F64 |
| 5273 arm_VCVT_HI_FXU32_F64 |
| 5274 arm_VCVT_LS_FXU32_F64 |
| 5275 arm_VCVT_GE_FXU32_F64 |
| 5276 arm_VCVT_LT_FXU32_F64 |
| 5277 arm_VCVT_GT_FXU32_F64 |
| 5278 arm_VCVT_LE_FXU32_F64 |
| 5279 arm_VCVT_FXU32_F64 |
| 5280 arm_VCVT_ZZ_FXU32_F64 |
| 5281 arm_VCVTB_EQ_F32_F16 |
| 5282 arm_VCVTB_NE_F32_F16 |
| 5283 arm_VCVTB_CS_F32_F16 |
| 5284 arm_VCVTB_CC_F32_F16 |
| 5285 arm_VCVTB_MI_F32_F16 |
| 5286 arm_VCVTB_PL_F32_F16 |
| 5287 arm_VCVTB_VS_F32_F16 |
| 5288 arm_VCVTB_VC_F32_F16 |
| 5289 arm_VCVTB_HI_F32_F16 |
| 5290 arm_VCVTB_LS_F32_F16 |
| 5291 arm_VCVTB_GE_F32_F16 |
| 5292 arm_VCVTB_LT_F32_F16 |
| 5293 arm_VCVTB_GT_F32_F16 |
| 5294 arm_VCVTB_LE_F32_F16 |
| 5295 arm_VCVTB_F32_F16 |
| 5296 arm_VCVTB_ZZ_F32_F16 |
| 5297 arm_VCVTB_EQ_F16_F32 |
| 5298 arm_VCVTB_NE_F16_F32 |
| 5299 arm_VCVTB_CS_F16_F32 |
| 5300 arm_VCVTB_CC_F16_F32 |
| 5301 arm_VCVTB_MI_F16_F32 |
| 5302 arm_VCVTB_PL_F16_F32 |
| 5303 arm_VCVTB_VS_F16_F32 |
| 5304 arm_VCVTB_VC_F16_F32 |
| 5305 arm_VCVTB_HI_F16_F32 |
| 5306 arm_VCVTB_LS_F16_F32 |
| 5307 arm_VCVTB_GE_F16_F32 |
| 5308 arm_VCVTB_LT_F16_F32 |
| 5309 arm_VCVTB_GT_F16_F32 |
| 5310 arm_VCVTB_LE_F16_F32 |
| 5311 arm_VCVTB_F16_F32 |
| 5312 arm_VCVTB_ZZ_F16_F32 |
| 5313 arm_VCVTT_EQ_F32_F16 |
| 5314 arm_VCVTT_NE_F32_F16 |
| 5315 arm_VCVTT_CS_F32_F16 |
| 5316 arm_VCVTT_CC_F32_F16 |
| 5317 arm_VCVTT_MI_F32_F16 |
| 5318 arm_VCVTT_PL_F32_F16 |
| 5319 arm_VCVTT_VS_F32_F16 |
| 5320 arm_VCVTT_VC_F32_F16 |
| 5321 arm_VCVTT_HI_F32_F16 |
| 5322 arm_VCVTT_LS_F32_F16 |
| 5323 arm_VCVTT_GE_F32_F16 |
| 5324 arm_VCVTT_LT_F32_F16 |
| 5325 arm_VCVTT_GT_F32_F16 |
| 5326 arm_VCVTT_LE_F32_F16 |
| 5327 arm_VCVTT_F32_F16 |
| 5328 arm_VCVTT_ZZ_F32_F16 |
| 5329 arm_VCVTT_EQ_F16_F32 |
| 5330 arm_VCVTT_NE_F16_F32 |
| 5331 arm_VCVTT_CS_F16_F32 |
| 5332 arm_VCVTT_CC_F16_F32 |
| 5333 arm_VCVTT_MI_F16_F32 |
| 5334 arm_VCVTT_PL_F16_F32 |
| 5335 arm_VCVTT_VS_F16_F32 |
| 5336 arm_VCVTT_VC_F16_F32 |
| 5337 arm_VCVTT_HI_F16_F32 |
| 5338 arm_VCVTT_LS_F16_F32 |
| 5339 arm_VCVTT_GE_F16_F32 |
| 5340 arm_VCVTT_LT_F16_F32 |
| 5341 arm_VCVTT_GT_F16_F32 |
| 5342 arm_VCVTT_LE_F16_F32 |
| 5343 arm_VCVTT_F16_F32 |
| 5344 arm_VCVTT_ZZ_F16_F32 |
| 5345 arm_VCVTR_EQ_U32_F32 |
| 5346 arm_VCVTR_NE_U32_F32 |
| 5347 arm_VCVTR_CS_U32_F32 |
| 5348 arm_VCVTR_CC_U32_F32 |
| 5349 arm_VCVTR_MI_U32_F32 |
| 5350 arm_VCVTR_PL_U32_F32 |
| 5351 arm_VCVTR_VS_U32_F32 |
| 5352 arm_VCVTR_VC_U32_F32 |
| 5353 arm_VCVTR_HI_U32_F32 |
| 5354 arm_VCVTR_LS_U32_F32 |
| 5355 arm_VCVTR_GE_U32_F32 |
| 5356 arm_VCVTR_LT_U32_F32 |
| 5357 arm_VCVTR_GT_U32_F32 |
| 5358 arm_VCVTR_LE_U32_F32 |
| 5359 arm_VCVTR_U32_F32 |
| 5360 arm_VCVTR_ZZ_U32_F32 |
| 5361 arm_VCVTR_EQ_U32_F64 |
| 5362 arm_VCVTR_NE_U32_F64 |
| 5363 arm_VCVTR_CS_U32_F64 |
| 5364 arm_VCVTR_CC_U32_F64 |
| 5365 arm_VCVTR_MI_U32_F64 |
| 5366 arm_VCVTR_PL_U32_F64 |
| 5367 arm_VCVTR_VS_U32_F64 |
| 5368 arm_VCVTR_VC_U32_F64 |
| 5369 arm_VCVTR_HI_U32_F64 |
| 5370 arm_VCVTR_LS_U32_F64 |
| 5371 arm_VCVTR_GE_U32_F64 |
| 5372 arm_VCVTR_LT_U32_F64 |
| 5373 arm_VCVTR_GT_U32_F64 |
| 5374 arm_VCVTR_LE_U32_F64 |
| 5375 arm_VCVTR_U32_F64 |
| 5376 arm_VCVTR_ZZ_U32_F64 |
| 5377 arm_VCVTR_EQ_S32_F32 |
| 5378 arm_VCVTR_NE_S32_F32 |
| 5379 arm_VCVTR_CS_S32_F32 |
| 5380 arm_VCVTR_CC_S32_F32 |
| 5381 arm_VCVTR_MI_S32_F32 |
| 5382 arm_VCVTR_PL_S32_F32 |
| 5383 arm_VCVTR_VS_S32_F32 |
| 5384 arm_VCVTR_VC_S32_F32 |
| 5385 arm_VCVTR_HI_S32_F32 |
| 5386 arm_VCVTR_LS_S32_F32 |
| 5387 arm_VCVTR_GE_S32_F32 |
| 5388 arm_VCVTR_LT_S32_F32 |
| 5389 arm_VCVTR_GT_S32_F32 |
| 5390 arm_VCVTR_LE_S32_F32 |
| 5391 arm_VCVTR_S32_F32 |
| 5392 arm_VCVTR_ZZ_S32_F32 |
| 5393 arm_VCVTR_EQ_S32_F64 |
| 5394 arm_VCVTR_NE_S32_F64 |
| 5395 arm_VCVTR_CS_S32_F64 |
| 5396 arm_VCVTR_CC_S32_F64 |
| 5397 arm_VCVTR_MI_S32_F64 |
| 5398 arm_VCVTR_PL_S32_F64 |
| 5399 arm_VCVTR_VS_S32_F64 |
| 5400 arm_VCVTR_VC_S32_F64 |
| 5401 arm_VCVTR_HI_S32_F64 |
| 5402 arm_VCVTR_LS_S32_F64 |
| 5403 arm_VCVTR_GE_S32_F64 |
| 5404 arm_VCVTR_LT_S32_F64 |
| 5405 arm_VCVTR_GT_S32_F64 |
| 5406 arm_VCVTR_LE_S32_F64 |
| 5407 arm_VCVTR_S32_F64 |
| 5408 arm_VCVTR_ZZ_S32_F64 |
| 5409 arm_VCVT_EQ_U32_F32 |
| 5410 arm_VCVT_NE_U32_F32 |
| 5411 arm_VCVT_CS_U32_F32 |
| 5412 arm_VCVT_CC_U32_F32 |
| 5413 arm_VCVT_MI_U32_F32 |
| 5414 arm_VCVT_PL_U32_F32 |
| 5415 arm_VCVT_VS_U32_F32 |
| 5416 arm_VCVT_VC_U32_F32 |
| 5417 arm_VCVT_HI_U32_F32 |
| 5418 arm_VCVT_LS_U32_F32 |
| 5419 arm_VCVT_GE_U32_F32 |
| 5420 arm_VCVT_LT_U32_F32 |
| 5421 arm_VCVT_GT_U32_F32 |
| 5422 arm_VCVT_LE_U32_F32 |
| 5423 arm_VCVT_U32_F32 |
| 5424 arm_VCVT_ZZ_U32_F32 |
| 5425 arm_VCVT_EQ_U32_F64 |
| 5426 arm_VCVT_NE_U32_F64 |
| 5427 arm_VCVT_CS_U32_F64 |
| 5428 arm_VCVT_CC_U32_F64 |
| 5429 arm_VCVT_MI_U32_F64 |
| 5430 arm_VCVT_PL_U32_F64 |
| 5431 arm_VCVT_VS_U32_F64 |
| 5432 arm_VCVT_VC_U32_F64 |
| 5433 arm_VCVT_HI_U32_F64 |
| 5434 arm_VCVT_LS_U32_F64 |
| 5435 arm_VCVT_GE_U32_F64 |
| 5436 arm_VCVT_LT_U32_F64 |
| 5437 arm_VCVT_GT_U32_F64 |
| 5438 arm_VCVT_LE_U32_F64 |
| 5439 arm_VCVT_U32_F64 |
| 5440 arm_VCVT_ZZ_U32_F64 |
| 5441 arm_VCVT_EQ_S32_F32 |
| 5442 arm_VCVT_NE_S32_F32 |
| 5443 arm_VCVT_CS_S32_F32 |
| 5444 arm_VCVT_CC_S32_F32 |
| 5445 arm_VCVT_MI_S32_F32 |
| 5446 arm_VCVT_PL_S32_F32 |
| 5447 arm_VCVT_VS_S32_F32 |
| 5448 arm_VCVT_VC_S32_F32 |
| 5449 arm_VCVT_HI_S32_F32 |
| 5450 arm_VCVT_LS_S32_F32 |
| 5451 arm_VCVT_GE_S32_F32 |
| 5452 arm_VCVT_LT_S32_F32 |
| 5453 arm_VCVT_GT_S32_F32 |
| 5454 arm_VCVT_LE_S32_F32 |
| 5455 arm_VCVT_S32_F32 |
| 5456 arm_VCVT_ZZ_S32_F32 |
| 5457 arm_VCVT_EQ_S32_F64 |
| 5458 arm_VCVT_NE_S32_F64 |
| 5459 arm_VCVT_CS_S32_F64 |
| 5460 arm_VCVT_CC_S32_F64 |
| 5461 arm_VCVT_MI_S32_F64 |
| 5462 arm_VCVT_PL_S32_F64 |
| 5463 arm_VCVT_VS_S32_F64 |
| 5464 arm_VCVT_VC_S32_F64 |
| 5465 arm_VCVT_HI_S32_F64 |
| 5466 arm_VCVT_LS_S32_F64 |
| 5467 arm_VCVT_GE_S32_F64 |
| 5468 arm_VCVT_LT_S32_F64 |
| 5469 arm_VCVT_GT_S32_F64 |
| 5470 arm_VCVT_LE_S32_F64 |
| 5471 arm_VCVT_S32_F64 |
| 5472 arm_VCVT_ZZ_S32_F64 |
| 5473 arm_VDIV_EQ_F32 |
| 5474 arm_VDIV_NE_F32 |
| 5475 arm_VDIV_CS_F32 |
| 5476 arm_VDIV_CC_F32 |
| 5477 arm_VDIV_MI_F32 |
| 5478 arm_VDIV_PL_F32 |
| 5479 arm_VDIV_VS_F32 |
| 5480 arm_VDIV_VC_F32 |
| 5481 arm_VDIV_HI_F32 |
| 5482 arm_VDIV_LS_F32 |
| 5483 arm_VDIV_GE_F32 |
| 5484 arm_VDIV_LT_F32 |
| 5485 arm_VDIV_GT_F32 |
| 5486 arm_VDIV_LE_F32 |
| 5487 arm_VDIV_F32 |
| 5488 arm_VDIV_ZZ_F32 |
| 5489 arm_VDIV_EQ_F64 |
| 5490 arm_VDIV_NE_F64 |
| 5491 arm_VDIV_CS_F64 |
| 5492 arm_VDIV_CC_F64 |
| 5493 arm_VDIV_MI_F64 |
| 5494 arm_VDIV_PL_F64 |
| 5495 arm_VDIV_VS_F64 |
| 5496 arm_VDIV_VC_F64 |
| 5497 arm_VDIV_HI_F64 |
| 5498 arm_VDIV_LS_F64 |
| 5499 arm_VDIV_GE_F64 |
| 5500 arm_VDIV_LT_F64 |
| 5501 arm_VDIV_GT_F64 |
| 5502 arm_VDIV_LE_F64 |
| 5503 arm_VDIV_F64 |
| 5504 arm_VDIV_ZZ_F64 |
| 5505 arm_VLDR_EQ |
| 5506 arm_VLDR_NE |
| 5507 arm_VLDR_CS |
| 5508 arm_VLDR_CC |
| 5509 arm_VLDR_MI |
| 5510 arm_VLDR_PL |
| 5511 arm_VLDR_VS |
| 5512 arm_VLDR_VC |
| 5513 arm_VLDR_HI |
| 5514 arm_VLDR_LS |
| 5515 arm_VLDR_GE |
| 5516 arm_VLDR_LT |
| 5517 arm_VLDR_GT |
| 5518 arm_VLDR_LE |
| 5519 arm_VLDR |
| 5520 arm_VLDR_ZZ |
| 5521 arm_VMLA_EQ_F32 |
| 5522 arm_VMLA_NE_F32 |
| 5523 arm_VMLA_CS_F32 |
| 5524 arm_VMLA_CC_F32 |
| 5525 arm_VMLA_MI_F32 |
| 5526 arm_VMLA_PL_F32 |
| 5527 arm_VMLA_VS_F32 |
| 5528 arm_VMLA_VC_F32 |
| 5529 arm_VMLA_HI_F32 |
| 5530 arm_VMLA_LS_F32 |
| 5531 arm_VMLA_GE_F32 |
| 5532 arm_VMLA_LT_F32 |
| 5533 arm_VMLA_GT_F32 |
| 5534 arm_VMLA_LE_F32 |
| 5535 arm_VMLA_F32 |
| 5536 arm_VMLA_ZZ_F32 |
| 5537 arm_VMLA_EQ_F64 |
| 5538 arm_VMLA_NE_F64 |
| 5539 arm_VMLA_CS_F64 |
| 5540 arm_VMLA_CC_F64 |
| 5541 arm_VMLA_MI_F64 |
| 5542 arm_VMLA_PL_F64 |
| 5543 arm_VMLA_VS_F64 |
| 5544 arm_VMLA_VC_F64 |
| 5545 arm_VMLA_HI_F64 |
| 5546 arm_VMLA_LS_F64 |
| 5547 arm_VMLA_GE_F64 |
| 5548 arm_VMLA_LT_F64 |
| 5549 arm_VMLA_GT_F64 |
| 5550 arm_VMLA_LE_F64 |
| 5551 arm_VMLA_F64 |
| 5552 arm_VMLA_ZZ_F64 |
| 5553 arm_VMLS_EQ_F32 |
| 5554 arm_VMLS_NE_F32 |
| 5555 arm_VMLS_CS_F32 |
| 5556 arm_VMLS_CC_F32 |
| 5557 arm_VMLS_MI_F32 |
| 5558 arm_VMLS_PL_F32 |
| 5559 arm_VMLS_VS_F32 |
| 5560 arm_VMLS_VC_F32 |
| 5561 arm_VMLS_HI_F32 |
| 5562 arm_VMLS_LS_F32 |
| 5563 arm_VMLS_GE_F32 |
| 5564 arm_VMLS_LT_F32 |
| 5565 arm_VMLS_GT_F32 |
| 5566 arm_VMLS_LE_F32 |
| 5567 arm_VMLS_F32 |
| 5568 arm_VMLS_ZZ_F32 |
| 5569 arm_VMLS_EQ_F64 |
| 5570 arm_VMLS_NE_F64 |
| 5571 arm_VMLS_CS_F64 |
| 5572 arm_VMLS_CC_F64 |
| 5573 arm_VMLS_MI_F64 |
| 5574 arm_VMLS_PL_F64 |
| 5575 arm_VMLS_VS_F64 |
| 5576 arm_VMLS_VC_F64 |
| 5577 arm_VMLS_HI_F64 |
| 5578 arm_VMLS_LS_F64 |
| 5579 arm_VMLS_GE_F64 |
| 5580 arm_VMLS_LT_F64 |
| 5581 arm_VMLS_GT_F64 |
| 5582 arm_VMLS_LE_F64 |
| 5583 arm_VMLS_F64 |
| 5584 arm_VMLS_ZZ_F64 |
| 5585 arm_VMOV_EQ |
| 5586 arm_VMOV_NE |
| 5587 arm_VMOV_CS |
| 5588 arm_VMOV_CC |
| 5589 arm_VMOV_MI |
| 5590 arm_VMOV_PL |
| 5591 arm_VMOV_VS |
| 5592 arm_VMOV_VC |
| 5593 arm_VMOV_HI |
| 5594 arm_VMOV_LS |
| 5595 arm_VMOV_GE |
| 5596 arm_VMOV_LT |
| 5597 arm_VMOV_GT |
| 5598 arm_VMOV_LE |
| 5599 arm_VMOV |
| 5600 arm_VMOV_ZZ |
| 5601 arm_VMOV_EQ_32 |
| 5602 arm_VMOV_NE_32 |
| 5603 arm_VMOV_CS_32 |
| 5604 arm_VMOV_CC_32 |
| 5605 arm_VMOV_MI_32 |
| 5606 arm_VMOV_PL_32 |
| 5607 arm_VMOV_VS_32 |
| 5608 arm_VMOV_VC_32 |
| 5609 arm_VMOV_HI_32 |
| 5610 arm_VMOV_LS_32 |
| 5611 arm_VMOV_GE_32 |
| 5612 arm_VMOV_LT_32 |
| 5613 arm_VMOV_GT_32 |
| 5614 arm_VMOV_LE_32 |
| 5615 arm_VMOV_32 |
| 5616 arm_VMOV_ZZ_32 |
| 5617 arm_VMOV_EQ_F32 |
| 5618 arm_VMOV_NE_F32 |
| 5619 arm_VMOV_CS_F32 |
| 5620 arm_VMOV_CC_F32 |
| 5621 arm_VMOV_MI_F32 |
| 5622 arm_VMOV_PL_F32 |
| 5623 arm_VMOV_VS_F32 |
| 5624 arm_VMOV_VC_F32 |
| 5625 arm_VMOV_HI_F32 |
| 5626 arm_VMOV_LS_F32 |
| 5627 arm_VMOV_GE_F32 |
| 5628 arm_VMOV_LT_F32 |
| 5629 arm_VMOV_GT_F32 |
| 5630 arm_VMOV_LE_F32 |
| 5631 arm_VMOV_F32 |
| 5632 arm_VMOV_ZZ_F32 |
| 5633 arm_VMOV_EQ_F64 |
| 5634 arm_VMOV_NE_F64 |
| 5635 arm_VMOV_CS_F64 |
| 5636 arm_VMOV_CC_F64 |
| 5637 arm_VMOV_MI_F64 |
| 5638 arm_VMOV_PL_F64 |
| 5639 arm_VMOV_VS_F64 |
| 5640 arm_VMOV_VC_F64 |
| 5641 arm_VMOV_HI_F64 |
| 5642 arm_VMOV_LS_F64 |
| 5643 arm_VMOV_GE_F64 |
| 5644 arm_VMOV_LT_F64 |
| 5645 arm_VMOV_GT_F64 |
| 5646 arm_VMOV_LE_F64 |
| 5647 arm_VMOV_F64 |
| 5648 arm_VMOV_ZZ_F64 |
| 5649 arm_VMRS_EQ |
| 5650 arm_VMRS_NE |
| 5651 arm_VMRS_CS |
| 5652 arm_VMRS_CC |
| 5653 arm_VMRS_MI |
| 5654 arm_VMRS_PL |
| 5655 arm_VMRS_VS |
| 5656 arm_VMRS_VC |
| 5657 arm_VMRS_HI |
| 5658 arm_VMRS_LS |
| 5659 arm_VMRS_GE |
| 5660 arm_VMRS_LT |
| 5661 arm_VMRS_GT |
| 5662 arm_VMRS_LE |
| 5663 arm_VMRS |
| 5664 arm_VMRS_ZZ |
| 5665 arm_VMSR_EQ |
| 5666 arm_VMSR_NE |
| 5667 arm_VMSR_CS |
| 5668 arm_VMSR_CC |
| 5669 arm_VMSR_MI |
| 5670 arm_VMSR_PL |
| 5671 arm_VMSR_VS |
| 5672 arm_VMSR_VC |
| 5673 arm_VMSR_HI |
| 5674 arm_VMSR_LS |
| 5675 arm_VMSR_GE |
| 5676 arm_VMSR_LT |
| 5677 arm_VMSR_GT |
| 5678 arm_VMSR_LE |
| 5679 arm_VMSR |
| 5680 arm_VMSR_ZZ |
| 5681 arm_VMUL_EQ_F32 |
| 5682 arm_VMUL_NE_F32 |
| 5683 arm_VMUL_CS_F32 |
| 5684 arm_VMUL_CC_F32 |
| 5685 arm_VMUL_MI_F32 |
| 5686 arm_VMUL_PL_F32 |
| 5687 arm_VMUL_VS_F32 |
| 5688 arm_VMUL_VC_F32 |
| 5689 arm_VMUL_HI_F32 |
| 5690 arm_VMUL_LS_F32 |
| 5691 arm_VMUL_GE_F32 |
| 5692 arm_VMUL_LT_F32 |
| 5693 arm_VMUL_GT_F32 |
| 5694 arm_VMUL_LE_F32 |
| 5695 arm_VMUL_F32 |
| 5696 arm_VMUL_ZZ_F32 |
| 5697 arm_VMUL_EQ_F64 |
| 5698 arm_VMUL_NE_F64 |
| 5699 arm_VMUL_CS_F64 |
| 5700 arm_VMUL_CC_F64 |
| 5701 arm_VMUL_MI_F64 |
| 5702 arm_VMUL_PL_F64 |
| 5703 arm_VMUL_VS_F64 |
| 5704 arm_VMUL_VC_F64 |
| 5705 arm_VMUL_HI_F64 |
| 5706 arm_VMUL_LS_F64 |
| 5707 arm_VMUL_GE_F64 |
| 5708 arm_VMUL_LT_F64 |
| 5709 arm_VMUL_GT_F64 |
| 5710 arm_VMUL_LE_F64 |
| 5711 arm_VMUL_F64 |
| 5712 arm_VMUL_ZZ_F64 |
| 5713 arm_VNEG_EQ_F32 |
| 5714 arm_VNEG_NE_F32 |
| 5715 arm_VNEG_CS_F32 |
| 5716 arm_VNEG_CC_F32 |
| 5717 arm_VNEG_MI_F32 |
| 5718 arm_VNEG_PL_F32 |
| 5719 arm_VNEG_VS_F32 |
| 5720 arm_VNEG_VC_F32 |
| 5721 arm_VNEG_HI_F32 |
| 5722 arm_VNEG_LS_F32 |
| 5723 arm_VNEG_GE_F32 |
| 5724 arm_VNEG_LT_F32 |
| 5725 arm_VNEG_GT_F32 |
| 5726 arm_VNEG_LE_F32 |
| 5727 arm_VNEG_F32 |
| 5728 arm_VNEG_ZZ_F32 |
| 5729 arm_VNEG_EQ_F64 |
| 5730 arm_VNEG_NE_F64 |
| 5731 arm_VNEG_CS_F64 |
| 5732 arm_VNEG_CC_F64 |
| 5733 arm_VNEG_MI_F64 |
| 5734 arm_VNEG_PL_F64 |
| 5735 arm_VNEG_VS_F64 |
| 5736 arm_VNEG_VC_F64 |
| 5737 arm_VNEG_HI_F64 |
| 5738 arm_VNEG_LS_F64 |
| 5739 arm_VNEG_GE_F64 |
| 5740 arm_VNEG_LT_F64 |
| 5741 arm_VNEG_GT_F64 |
| 5742 arm_VNEG_LE_F64 |
| 5743 arm_VNEG_F64 |
| 5744 arm_VNEG_ZZ_F64 |
| 5745 arm_VNMLS_EQ_F32 |
| 5746 arm_VNMLS_NE_F32 |
| 5747 arm_VNMLS_CS_F32 |
| 5748 arm_VNMLS_CC_F32 |
| 5749 arm_VNMLS_MI_F32 |
| 5750 arm_VNMLS_PL_F32 |
| 5751 arm_VNMLS_VS_F32 |
| 5752 arm_VNMLS_VC_F32 |
| 5753 arm_VNMLS_HI_F32 |
| 5754 arm_VNMLS_LS_F32 |
| 5755 arm_VNMLS_GE_F32 |
| 5756 arm_VNMLS_LT_F32 |
| 5757 arm_VNMLS_GT_F32 |
| 5758 arm_VNMLS_LE_F32 |
| 5759 arm_VNMLS_F32 |
| 5760 arm_VNMLS_ZZ_F32 |
| 5761 arm_VNMLS_EQ_F64 |
| 5762 arm_VNMLS_NE_F64 |
| 5763 arm_VNMLS_CS_F64 |
| 5764 arm_VNMLS_CC_F64 |
| 5765 arm_VNMLS_MI_F64 |
| 5766 arm_VNMLS_PL_F64 |
| 5767 arm_VNMLS_VS_F64 |
| 5768 arm_VNMLS_VC_F64 |
| 5769 arm_VNMLS_HI_F64 |
| 5770 arm_VNMLS_LS_F64 |
| 5771 arm_VNMLS_GE_F64 |
| 5772 arm_VNMLS_LT_F64 |
| 5773 arm_VNMLS_GT_F64 |
| 5774 arm_VNMLS_LE_F64 |
| 5775 arm_VNMLS_F64 |
| 5776 arm_VNMLS_ZZ_F64 |
| 5777 arm_VNMLA_EQ_F32 |
| 5778 arm_VNMLA_NE_F32 |
| 5779 arm_VNMLA_CS_F32 |
| 5780 arm_VNMLA_CC_F32 |
| 5781 arm_VNMLA_MI_F32 |
| 5782 arm_VNMLA_PL_F32 |
| 5783 arm_VNMLA_VS_F32 |
| 5784 arm_VNMLA_VC_F32 |
| 5785 arm_VNMLA_HI_F32 |
| 5786 arm_VNMLA_LS_F32 |
| 5787 arm_VNMLA_GE_F32 |
| 5788 arm_VNMLA_LT_F32 |
| 5789 arm_VNMLA_GT_F32 |
| 5790 arm_VNMLA_LE_F32 |
| 5791 arm_VNMLA_F32 |
| 5792 arm_VNMLA_ZZ_F32 |
| 5793 arm_VNMLA_EQ_F64 |
| 5794 arm_VNMLA_NE_F64 |
| 5795 arm_VNMLA_CS_F64 |
| 5796 arm_VNMLA_CC_F64 |
| 5797 arm_VNMLA_MI_F64 |
| 5798 arm_VNMLA_PL_F64 |
| 5799 arm_VNMLA_VS_F64 |
| 5800 arm_VNMLA_VC_F64 |
| 5801 arm_VNMLA_HI_F64 |
| 5802 arm_VNMLA_LS_F64 |
| 5803 arm_VNMLA_GE_F64 |
| 5804 arm_VNMLA_LT_F64 |
| 5805 arm_VNMLA_GT_F64 |
| 5806 arm_VNMLA_LE_F64 |
| 5807 arm_VNMLA_F64 |
| 5808 arm_VNMLA_ZZ_F64 |
| 5809 arm_VNMUL_EQ_F32 |
| 5810 arm_VNMUL_NE_F32 |
| 5811 arm_VNMUL_CS_F32 |
| 5812 arm_VNMUL_CC_F32 |
| 5813 arm_VNMUL_MI_F32 |
| 5814 arm_VNMUL_PL_F32 |
| 5815 arm_VNMUL_VS_F32 |
| 5816 arm_VNMUL_VC_F32 |
| 5817 arm_VNMUL_HI_F32 |
| 5818 arm_VNMUL_LS_F32 |
| 5819 arm_VNMUL_GE_F32 |
| 5820 arm_VNMUL_LT_F32 |
| 5821 arm_VNMUL_GT_F32 |
| 5822 arm_VNMUL_LE_F32 |
| 5823 arm_VNMUL_F32 |
| 5824 arm_VNMUL_ZZ_F32 |
| 5825 arm_VNMUL_EQ_F64 |
| 5826 arm_VNMUL_NE_F64 |
| 5827 arm_VNMUL_CS_F64 |
| 5828 arm_VNMUL_CC_F64 |
| 5829 arm_VNMUL_MI_F64 |
| 5830 arm_VNMUL_PL_F64 |
| 5831 arm_VNMUL_VS_F64 |
| 5832 arm_VNMUL_VC_F64 |
| 5833 arm_VNMUL_HI_F64 |
| 5834 arm_VNMUL_LS_F64 |
| 5835 arm_VNMUL_GE_F64 |
| 5836 arm_VNMUL_LT_F64 |
| 5837 arm_VNMUL_GT_F64 |
| 5838 arm_VNMUL_LE_F64 |
| 5839 arm_VNMUL_F64 |
| 5840 arm_VNMUL_ZZ_F64 |
| 5841 arm_VSQRT_EQ_F32 |
| 5842 arm_VSQRT_NE_F32 |
| 5843 arm_VSQRT_CS_F32 |
| 5844 arm_VSQRT_CC_F32 |
| 5845 arm_VSQRT_MI_F32 |
| 5846 arm_VSQRT_PL_F32 |
| 5847 arm_VSQRT_VS_F32 |
| 5848 arm_VSQRT_VC_F32 |
| 5849 arm_VSQRT_HI_F32 |
| 5850 arm_VSQRT_LS_F32 |
| 5851 arm_VSQRT_GE_F32 |
| 5852 arm_VSQRT_LT_F32 |
| 5853 arm_VSQRT_GT_F32 |
| 5854 arm_VSQRT_LE_F32 |
| 5855 arm_VSQRT_F32 |
| 5856 arm_VSQRT_ZZ_F32 |
| 5857 arm_VSQRT_EQ_F64 |
| 5858 arm_VSQRT_NE_F64 |
| 5859 arm_VSQRT_CS_F64 |
| 5860 arm_VSQRT_CC_F64 |
| 5861 arm_VSQRT_MI_F64 |
| 5862 arm_VSQRT_PL_F64 |
| 5863 arm_VSQRT_VS_F64 |
| 5864 arm_VSQRT_VC_F64 |
| 5865 arm_VSQRT_HI_F64 |
| 5866 arm_VSQRT_LS_F64 |
| 5867 arm_VSQRT_GE_F64 |
| 5868 arm_VSQRT_LT_F64 |
| 5869 arm_VSQRT_GT_F64 |
| 5870 arm_VSQRT_LE_F64 |
| 5871 arm_VSQRT_F64 |
| 5872 arm_VSQRT_ZZ_F64 |
| 5873 arm_VSTR_EQ |
| 5874 arm_VSTR_NE |
| 5875 arm_VSTR_CS |
| 5876 arm_VSTR_CC |
| 5877 arm_VSTR_MI |
| 5878 arm_VSTR_PL |
| 5879 arm_VSTR_VS |
| 5880 arm_VSTR_VC |
| 5881 arm_VSTR_HI |
| 5882 arm_VSTR_LS |
| 5883 arm_VSTR_GE |
| 5884 arm_VSTR_LT |
| 5885 arm_VSTR_GT |
| 5886 arm_VSTR_LE |
| 5887 arm_VSTR |
| 5888 arm_VSTR_ZZ |
| 5889 arm_VSUB_EQ_F32 |
| 5890 arm_VSUB_NE_F32 |
| 5891 arm_VSUB_CS_F32 |
| 5892 arm_VSUB_CC_F32 |
| 5893 arm_VSUB_MI_F32 |
| 5894 arm_VSUB_PL_F32 |
| 5895 arm_VSUB_VS_F32 |
| 5896 arm_VSUB_VC_F32 |
| 5897 arm_VSUB_HI_F32 |
| 5898 arm_VSUB_LS_F32 |
| 5899 arm_VSUB_GE_F32 |
| 5900 arm_VSUB_LT_F32 |
| 5901 arm_VSUB_GT_F32 |
| 5902 arm_VSUB_LE_F32 |
| 5903 arm_VSUB_F32 |
| 5904 arm_VSUB_ZZ_F32 |
| 5905 arm_VSUB_EQ_F64 |
| 5906 arm_VSUB_NE_F64 |
| 5907 arm_VSUB_CS_F64 |
| 5908 arm_VSUB_CC_F64 |
| 5909 arm_VSUB_MI_F64 |
| 5910 arm_VSUB_PL_F64 |
| 5911 arm_VSUB_VS_F64 |
| 5912 arm_VSUB_VC_F64 |
| 5913 arm_VSUB_HI_F64 |
| 5914 arm_VSUB_LS_F64 |
| 5915 arm_VSUB_GE_F64 |
| 5916 arm_VSUB_LT_F64 |
| 5917 arm_VSUB_GT_F64 |
| 5918 arm_VSUB_LE_F64 |
| 5919 arm_VSUB_F64 |
| 5920 arm_VSUB_ZZ_F64 |
4564 arm_WFE_EQ | 5921 arm_WFE_EQ |
4565 arm_WFE_NE | 5922 arm_WFE_NE |
4566 arm_WFE_CS | 5923 arm_WFE_CS |
4567 arm_WFE_CC | 5924 arm_WFE_CC |
4568 arm_WFE_MI | 5925 arm_WFE_MI |
4569 arm_WFE_PL | 5926 arm_WFE_PL |
4570 arm_WFE_VS | 5927 arm_WFE_VS |
4571 arm_WFE_VC | 5928 arm_WFE_VC |
4572 arm_WFE_HI | 5929 arm_WFE_HI |
4573 arm_WFE_LS | 5930 arm_WFE_LS |
(...skipping 31 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
4605 arm_YIELD_LS | 5962 arm_YIELD_LS |
4606 arm_YIELD_GE | 5963 arm_YIELD_GE |
4607 arm_YIELD_LT | 5964 arm_YIELD_LT |
4608 arm_YIELD_GT | 5965 arm_YIELD_GT |
4609 arm_YIELD_LE | 5966 arm_YIELD_LE |
4610 arm_YIELD | 5967 arm_YIELD |
4611 arm_YIELD_ZZ | 5968 arm_YIELD_ZZ |
4612 ) | 5969 ) |
4613 | 5970 |
4614 var arm_opstr = [...]string{ | 5971 var arm_opstr = [...]string{ |
4615 arm_ADC_EQ: "ADC.EQ", | 5972 arm_ADC_EQ: "ADC.EQ", |
4616 arm_ADC_NE: "ADC.NE", | 5973 arm_ADC_NE: "ADC.NE", |
4617 arm_ADC_CS: "ADC.CS", | 5974 arm_ADC_CS: "ADC.CS", |
4618 arm_ADC_CC: "ADC.CC", | 5975 arm_ADC_CC: "ADC.CC", |
4619 arm_ADC_MI: "ADC.MI", | 5976 arm_ADC_MI: "ADC.MI", |
4620 arm_ADC_PL: "ADC.PL", | 5977 arm_ADC_PL: "ADC.PL", |
4621 arm_ADC_VS: "ADC.VS", | 5978 arm_ADC_VS: "ADC.VS", |
4622 arm_ADC_VC: "ADC.VC", | 5979 arm_ADC_VC: "ADC.VC", |
4623 arm_ADC_HI: "ADC.HI", | 5980 arm_ADC_HI: "ADC.HI", |
4624 arm_ADC_LS: "ADC.LS", | 5981 arm_ADC_LS: "ADC.LS", |
4625 arm_ADC_GE: "ADC.GE", | 5982 arm_ADC_GE: "ADC.GE", |
4626 arm_ADC_LT: "ADC.LT", | 5983 arm_ADC_LT: "ADC.LT", |
4627 arm_ADC_GT: "ADC.GT", | 5984 arm_ADC_GT: "ADC.GT", |
4628 arm_ADC_LE: "ADC.LE", | 5985 arm_ADC_LE: "ADC.LE", |
4629 arm_ADC: "ADC", | 5986 arm_ADC: "ADC", |
4630 arm_ADC_ZZ: "ADC.ZZ", | 5987 arm_ADC_ZZ: "ADC.ZZ", |
4631 arm_ADC_S_EQ: "ADC.S.EQ", | 5988 arm_ADC_S_EQ: "ADC.S.EQ", |
4632 arm_ADC_S_NE: "ADC.S.NE", | 5989 arm_ADC_S_NE: "ADC.S.NE", |
4633 arm_ADC_S_CS: "ADC.S.CS", | 5990 arm_ADC_S_CS: "ADC.S.CS", |
4634 arm_ADC_S_CC: "ADC.S.CC", | 5991 arm_ADC_S_CC: "ADC.S.CC", |
4635 arm_ADC_S_MI: "ADC.S.MI", | 5992 arm_ADC_S_MI: "ADC.S.MI", |
4636 arm_ADC_S_PL: "ADC.S.PL", | 5993 arm_ADC_S_PL: "ADC.S.PL", |
4637 arm_ADC_S_VS: "ADC.S.VS", | 5994 arm_ADC_S_VS: "ADC.S.VS", |
4638 arm_ADC_S_VC: "ADC.S.VC", | 5995 arm_ADC_S_VC: "ADC.S.VC", |
4639 arm_ADC_S_HI: "ADC.S.HI", | 5996 arm_ADC_S_HI: "ADC.S.HI", |
4640 arm_ADC_S_LS: "ADC.S.LS", | 5997 arm_ADC_S_LS: "ADC.S.LS", |
4641 arm_ADC_S_GE: "ADC.S.GE", | 5998 arm_ADC_S_GE: "ADC.S.GE", |
4642 arm_ADC_S_LT: "ADC.S.LT", | 5999 arm_ADC_S_LT: "ADC.S.LT", |
4643 arm_ADC_S_GT: "ADC.S.GT", | 6000 arm_ADC_S_GT: "ADC.S.GT", |
4644 arm_ADC_S_LE: "ADC.S.LE", | 6001 arm_ADC_S_LE: "ADC.S.LE", |
4645 arm_ADC_S: "ADC.S", | 6002 arm_ADC_S: "ADC.S", |
4646 arm_ADC_S_ZZ: "ADC.S.ZZ", | 6003 arm_ADC_S_ZZ: "ADC.S.ZZ", |
4647 arm_ADD_EQ: "ADD.EQ", | 6004 arm_ADD_EQ: "ADD.EQ", |
4648 arm_ADD_NE: "ADD.NE", | 6005 arm_ADD_NE: "ADD.NE", |
4649 arm_ADD_CS: "ADD.CS", | 6006 arm_ADD_CS: "ADD.CS", |
4650 arm_ADD_CC: "ADD.CC", | 6007 arm_ADD_CC: "ADD.CC", |
4651 arm_ADD_MI: "ADD.MI", | 6008 arm_ADD_MI: "ADD.MI", |
4652 arm_ADD_PL: "ADD.PL", | 6009 arm_ADD_PL: "ADD.PL", |
4653 arm_ADD_VS: "ADD.VS", | 6010 arm_ADD_VS: "ADD.VS", |
4654 arm_ADD_VC: "ADD.VC", | 6011 arm_ADD_VC: "ADD.VC", |
4655 arm_ADD_HI: "ADD.HI", | 6012 arm_ADD_HI: "ADD.HI", |
4656 arm_ADD_LS: "ADD.LS", | 6013 arm_ADD_LS: "ADD.LS", |
4657 arm_ADD_GE: "ADD.GE", | 6014 arm_ADD_GE: "ADD.GE", |
4658 arm_ADD_LT: "ADD.LT", | 6015 arm_ADD_LT: "ADD.LT", |
4659 arm_ADD_GT: "ADD.GT", | 6016 arm_ADD_GT: "ADD.GT", |
4660 arm_ADD_LE: "ADD.LE", | 6017 arm_ADD_LE: "ADD.LE", |
4661 arm_ADD: "ADD", | 6018 arm_ADD: "ADD", |
4662 arm_ADD_ZZ: "ADD.ZZ", | 6019 arm_ADD_ZZ: "ADD.ZZ", |
4663 arm_ADD_S_EQ: "ADD.S.EQ", | 6020 arm_ADD_S_EQ: "ADD.S.EQ", |
4664 arm_ADD_S_NE: "ADD.S.NE", | 6021 arm_ADD_S_NE: "ADD.S.NE", |
4665 arm_ADD_S_CS: "ADD.S.CS", | 6022 arm_ADD_S_CS: "ADD.S.CS", |
4666 arm_ADD_S_CC: "ADD.S.CC", | 6023 arm_ADD_S_CC: "ADD.S.CC", |
4667 arm_ADD_S_MI: "ADD.S.MI", | 6024 arm_ADD_S_MI: "ADD.S.MI", |
4668 arm_ADD_S_PL: "ADD.S.PL", | 6025 arm_ADD_S_PL: "ADD.S.PL", |
4669 arm_ADD_S_VS: "ADD.S.VS", | 6026 arm_ADD_S_VS: "ADD.S.VS", |
4670 arm_ADD_S_VC: "ADD.S.VC", | 6027 arm_ADD_S_VC: "ADD.S.VC", |
4671 arm_ADD_S_HI: "ADD.S.HI", | 6028 arm_ADD_S_HI: "ADD.S.HI", |
4672 arm_ADD_S_LS: "ADD.S.LS", | 6029 arm_ADD_S_LS: "ADD.S.LS", |
4673 arm_ADD_S_GE: "ADD.S.GE", | 6030 arm_ADD_S_GE: "ADD.S.GE", |
4674 arm_ADD_S_LT: "ADD.S.LT", | 6031 arm_ADD_S_LT: "ADD.S.LT", |
4675 arm_ADD_S_GT: "ADD.S.GT", | 6032 arm_ADD_S_GT: "ADD.S.GT", |
4676 arm_ADD_S_LE: "ADD.S.LE", | 6033 arm_ADD_S_LE: "ADD.S.LE", |
4677 arm_ADD_S: "ADD.S", | 6034 arm_ADD_S: "ADD.S", |
4678 arm_ADD_S_ZZ: "ADD.S.ZZ", | 6035 arm_ADD_S_ZZ: "ADD.S.ZZ", |
4679 arm_AND_EQ: "AND.EQ", | 6036 arm_AND_EQ: "AND.EQ", |
4680 arm_AND_NE: "AND.NE", | 6037 arm_AND_NE: "AND.NE", |
4681 arm_AND_CS: "AND.CS", | 6038 arm_AND_CS: "AND.CS", |
4682 arm_AND_CC: "AND.CC", | 6039 arm_AND_CC: "AND.CC", |
4683 arm_AND_MI: "AND.MI", | 6040 arm_AND_MI: "AND.MI", |
4684 arm_AND_PL: "AND.PL", | 6041 arm_AND_PL: "AND.PL", |
4685 arm_AND_VS: "AND.VS", | 6042 arm_AND_VS: "AND.VS", |
4686 arm_AND_VC: "AND.VC", | 6043 arm_AND_VC: "AND.VC", |
4687 arm_AND_HI: "AND.HI", | 6044 arm_AND_HI: "AND.HI", |
4688 arm_AND_LS: "AND.LS", | 6045 arm_AND_LS: "AND.LS", |
4689 arm_AND_GE: "AND.GE", | 6046 arm_AND_GE: "AND.GE", |
4690 arm_AND_LT: "AND.LT", | 6047 arm_AND_LT: "AND.LT", |
4691 arm_AND_GT: "AND.GT", | 6048 arm_AND_GT: "AND.GT", |
4692 arm_AND_LE: "AND.LE", | 6049 arm_AND_LE: "AND.LE", |
4693 arm_AND: "AND", | 6050 arm_AND: "AND", |
4694 arm_AND_ZZ: "AND.ZZ", | 6051 arm_AND_ZZ: "AND.ZZ", |
4695 arm_AND_S_EQ: "AND.S.EQ", | 6052 arm_AND_S_EQ: "AND.S.EQ", |
4696 arm_AND_S_NE: "AND.S.NE", | 6053 arm_AND_S_NE: "AND.S.NE", |
4697 arm_AND_S_CS: "AND.S.CS", | 6054 arm_AND_S_CS: "AND.S.CS", |
4698 arm_AND_S_CC: "AND.S.CC", | 6055 arm_AND_S_CC: "AND.S.CC", |
4699 arm_AND_S_MI: "AND.S.MI", | 6056 arm_AND_S_MI: "AND.S.MI", |
4700 arm_AND_S_PL: "AND.S.PL", | 6057 arm_AND_S_PL: "AND.S.PL", |
4701 arm_AND_S_VS: "AND.S.VS", | 6058 arm_AND_S_VS: "AND.S.VS", |
4702 arm_AND_S_VC: "AND.S.VC", | 6059 arm_AND_S_VC: "AND.S.VC", |
4703 arm_AND_S_HI: "AND.S.HI", | 6060 arm_AND_S_HI: "AND.S.HI", |
4704 arm_AND_S_LS: "AND.S.LS", | 6061 arm_AND_S_LS: "AND.S.LS", |
4705 arm_AND_S_GE: "AND.S.GE", | 6062 arm_AND_S_GE: "AND.S.GE", |
4706 arm_AND_S_LT: "AND.S.LT", | 6063 arm_AND_S_LT: "AND.S.LT", |
4707 arm_AND_S_GT: "AND.S.GT", | 6064 arm_AND_S_GT: "AND.S.GT", |
4708 arm_AND_S_LE: "AND.S.LE", | 6065 arm_AND_S_LE: "AND.S.LE", |
4709 arm_AND_S: "AND.S", | 6066 arm_AND_S: "AND.S", |
4710 arm_AND_S_ZZ: "AND.S.ZZ", | 6067 arm_AND_S_ZZ: "AND.S.ZZ", |
4711 arm_ASR_EQ: "ASR.EQ", | 6068 arm_ASR_EQ: "ASR.EQ", |
4712 arm_ASR_NE: "ASR.NE", | 6069 arm_ASR_NE: "ASR.NE", |
4713 arm_ASR_CS: "ASR.CS", | 6070 arm_ASR_CS: "ASR.CS", |
4714 arm_ASR_CC: "ASR.CC", | 6071 arm_ASR_CC: "ASR.CC", |
4715 arm_ASR_MI: "ASR.MI", | 6072 arm_ASR_MI: "ASR.MI", |
4716 arm_ASR_PL: "ASR.PL", | 6073 arm_ASR_PL: "ASR.PL", |
4717 arm_ASR_VS: "ASR.VS", | 6074 arm_ASR_VS: "ASR.VS", |
4718 arm_ASR_VC: "ASR.VC", | 6075 arm_ASR_VC: "ASR.VC", |
4719 arm_ASR_HI: "ASR.HI", | 6076 arm_ASR_HI: "ASR.HI", |
4720 arm_ASR_LS: "ASR.LS", | 6077 arm_ASR_LS: "ASR.LS", |
4721 arm_ASR_GE: "ASR.GE", | 6078 arm_ASR_GE: "ASR.GE", |
4722 arm_ASR_LT: "ASR.LT", | 6079 arm_ASR_LT: "ASR.LT", |
4723 arm_ASR_GT: "ASR.GT", | 6080 arm_ASR_GT: "ASR.GT", |
4724 arm_ASR_LE: "ASR.LE", | 6081 arm_ASR_LE: "ASR.LE", |
4725 arm_ASR: "ASR", | 6082 arm_ASR: "ASR", |
4726 arm_ASR_ZZ: "ASR.ZZ", | 6083 arm_ASR_ZZ: "ASR.ZZ", |
4727 arm_ASR_S_EQ: "ASR.S.EQ", | 6084 arm_ASR_S_EQ: "ASR.S.EQ", |
4728 arm_ASR_S_NE: "ASR.S.NE", | 6085 arm_ASR_S_NE: "ASR.S.NE", |
4729 arm_ASR_S_CS: "ASR.S.CS", | 6086 arm_ASR_S_CS: "ASR.S.CS", |
4730 arm_ASR_S_CC: "ASR.S.CC", | 6087 arm_ASR_S_CC: "ASR.S.CC", |
4731 arm_ASR_S_MI: "ASR.S.MI", | 6088 arm_ASR_S_MI: "ASR.S.MI", |
4732 arm_ASR_S_PL: "ASR.S.PL", | 6089 arm_ASR_S_PL: "ASR.S.PL", |
4733 arm_ASR_S_VS: "ASR.S.VS", | 6090 arm_ASR_S_VS: "ASR.S.VS", |
4734 arm_ASR_S_VC: "ASR.S.VC", | 6091 arm_ASR_S_VC: "ASR.S.VC", |
4735 arm_ASR_S_HI: "ASR.S.HI", | 6092 arm_ASR_S_HI: "ASR.S.HI", |
4736 arm_ASR_S_LS: "ASR.S.LS", | 6093 arm_ASR_S_LS: "ASR.S.LS", |
4737 arm_ASR_S_GE: "ASR.S.GE", | 6094 arm_ASR_S_GE: "ASR.S.GE", |
4738 arm_ASR_S_LT: "ASR.S.LT", | 6095 arm_ASR_S_LT: "ASR.S.LT", |
4739 arm_ASR_S_GT: "ASR.S.GT", | 6096 arm_ASR_S_GT: "ASR.S.GT", |
4740 arm_ASR_S_LE: "ASR.S.LE", | 6097 arm_ASR_S_LE: "ASR.S.LE", |
4741 arm_ASR_S: "ASR.S", | 6098 arm_ASR_S: "ASR.S", |
4742 arm_ASR_S_ZZ: "ASR.S.ZZ", | 6099 arm_ASR_S_ZZ: "ASR.S.ZZ", |
4743 arm_B_EQ: "B.EQ", | 6100 arm_B_EQ: "B.EQ", |
4744 arm_B_NE: "B.NE", | 6101 arm_B_NE: "B.NE", |
4745 arm_B_CS: "B.CS", | 6102 arm_B_CS: "B.CS", |
4746 arm_B_CC: "B.CC", | 6103 arm_B_CC: "B.CC", |
4747 arm_B_MI: "B.MI", | 6104 arm_B_MI: "B.MI", |
4748 arm_B_PL: "B.PL", | 6105 arm_B_PL: "B.PL", |
4749 arm_B_VS: "B.VS", | 6106 arm_B_VS: "B.VS", |
4750 arm_B_VC: "B.VC", | 6107 arm_B_VC: "B.VC", |
4751 arm_B_HI: "B.HI", | 6108 arm_B_HI: "B.HI", |
4752 arm_B_LS: "B.LS", | 6109 arm_B_LS: "B.LS", |
4753 arm_B_GE: "B.GE", | 6110 arm_B_GE: "B.GE", |
4754 arm_B_LT: "B.LT", | 6111 arm_B_LT: "B.LT", |
4755 arm_B_GT: "B.GT", | 6112 arm_B_GT: "B.GT", |
4756 arm_B_LE: "B.LE", | 6113 arm_B_LE: "B.LE", |
4757 arm_B: "B", | 6114 arm_B: "B", |
4758 arm_B_ZZ: "B.ZZ", | 6115 arm_B_ZZ: "B.ZZ", |
4759 arm_BFC_EQ: "BFC.EQ", | 6116 arm_BFC_EQ: "BFC.EQ", |
4760 arm_BFC_NE: "BFC.NE", | 6117 arm_BFC_NE: "BFC.NE", |
4761 arm_BFC_CS: "BFC.CS", | 6118 arm_BFC_CS: "BFC.CS", |
4762 arm_BFC_CC: "BFC.CC", | 6119 arm_BFC_CC: "BFC.CC", |
4763 arm_BFC_MI: "BFC.MI", | 6120 arm_BFC_MI: "BFC.MI", |
4764 arm_BFC_PL: "BFC.PL", | 6121 arm_BFC_PL: "BFC.PL", |
4765 arm_BFC_VS: "BFC.VS", | 6122 arm_BFC_VS: "BFC.VS", |
4766 arm_BFC_VC: "BFC.VC", | 6123 arm_BFC_VC: "BFC.VC", |
4767 arm_BFC_HI: "BFC.HI", | 6124 arm_BFC_HI: "BFC.HI", |
4768 arm_BFC_LS: "BFC.LS", | 6125 arm_BFC_LS: "BFC.LS", |
4769 arm_BFC_GE: "BFC.GE", | 6126 arm_BFC_GE: "BFC.GE", |
4770 arm_BFC_LT: "BFC.LT", | 6127 arm_BFC_LT: "BFC.LT", |
4771 arm_BFC_GT: "BFC.GT", | 6128 arm_BFC_GT: "BFC.GT", |
4772 arm_BFC_LE: "BFC.LE", | 6129 arm_BFC_LE: "BFC.LE", |
4773 arm_BFC: "BFC", | 6130 arm_BFC: "BFC", |
4774 arm_BFC_ZZ: "BFC.ZZ", | 6131 arm_BFC_ZZ: "BFC.ZZ", |
4775 arm_BFI_EQ: "BFI.EQ", | 6132 arm_BFI_EQ: "BFI.EQ", |
4776 arm_BFI_NE: "BFI.NE", | 6133 arm_BFI_NE: "BFI.NE", |
4777 arm_BFI_CS: "BFI.CS", | 6134 arm_BFI_CS: "BFI.CS", |
4778 arm_BFI_CC: "BFI.CC", | 6135 arm_BFI_CC: "BFI.CC", |
4779 arm_BFI_MI: "BFI.MI", | 6136 arm_BFI_MI: "BFI.MI", |
4780 arm_BFI_PL: "BFI.PL", | 6137 arm_BFI_PL: "BFI.PL", |
4781 arm_BFI_VS: "BFI.VS", | 6138 arm_BFI_VS: "BFI.VS", |
4782 arm_BFI_VC: "BFI.VC", | 6139 arm_BFI_VC: "BFI.VC", |
4783 arm_BFI_HI: "BFI.HI", | 6140 arm_BFI_HI: "BFI.HI", |
4784 arm_BFI_LS: "BFI.LS", | 6141 arm_BFI_LS: "BFI.LS", |
4785 arm_BFI_GE: "BFI.GE", | 6142 arm_BFI_GE: "BFI.GE", |
4786 arm_BFI_LT: "BFI.LT", | 6143 arm_BFI_LT: "BFI.LT", |
4787 arm_BFI_GT: "BFI.GT", | 6144 arm_BFI_GT: "BFI.GT", |
4788 arm_BFI_LE: "BFI.LE", | 6145 arm_BFI_LE: "BFI.LE", |
4789 arm_BFI: "BFI", | 6146 arm_BFI: "BFI", |
4790 arm_BFI_ZZ: "BFI.ZZ", | 6147 arm_BFI_ZZ: "BFI.ZZ", |
4791 arm_BIC_EQ: "BIC.EQ", | 6148 arm_BIC_EQ: "BIC.EQ", |
4792 arm_BIC_NE: "BIC.NE", | 6149 arm_BIC_NE: "BIC.NE", |
4793 arm_BIC_CS: "BIC.CS", | 6150 arm_BIC_CS: "BIC.CS", |
4794 arm_BIC_CC: "BIC.CC", | 6151 arm_BIC_CC: "BIC.CC", |
4795 arm_BIC_MI: "BIC.MI", | 6152 arm_BIC_MI: "BIC.MI", |
4796 arm_BIC_PL: "BIC.PL", | 6153 arm_BIC_PL: "BIC.PL", |
4797 arm_BIC_VS: "BIC.VS", | 6154 arm_BIC_VS: "BIC.VS", |
4798 arm_BIC_VC: "BIC.VC", | 6155 arm_BIC_VC: "BIC.VC", |
4799 arm_BIC_HI: "BIC.HI", | 6156 arm_BIC_HI: "BIC.HI", |
4800 arm_BIC_LS: "BIC.LS", | 6157 arm_BIC_LS: "BIC.LS", |
4801 arm_BIC_GE: "BIC.GE", | 6158 arm_BIC_GE: "BIC.GE", |
4802 arm_BIC_LT: "BIC.LT", | 6159 arm_BIC_LT: "BIC.LT", |
4803 arm_BIC_GT: "BIC.GT", | 6160 arm_BIC_GT: "BIC.GT", |
4804 arm_BIC_LE: "BIC.LE", | 6161 arm_BIC_LE: "BIC.LE", |
4805 arm_BIC: "BIC", | 6162 arm_BIC: "BIC", |
4806 arm_BIC_ZZ: "BIC.ZZ", | 6163 arm_BIC_ZZ: "BIC.ZZ", |
4807 arm_BIC_S_EQ: "BIC.S.EQ", | 6164 arm_BIC_S_EQ: "BIC.S.EQ", |
4808 arm_BIC_S_NE: "BIC.S.NE", | 6165 arm_BIC_S_NE: "BIC.S.NE", |
4809 arm_BIC_S_CS: "BIC.S.CS", | 6166 arm_BIC_S_CS: "BIC.S.CS", |
4810 arm_BIC_S_CC: "BIC.S.CC", | 6167 arm_BIC_S_CC: "BIC.S.CC", |
4811 arm_BIC_S_MI: "BIC.S.MI", | 6168 arm_BIC_S_MI: "BIC.S.MI", |
4812 arm_BIC_S_PL: "BIC.S.PL", | 6169 arm_BIC_S_PL: "BIC.S.PL", |
4813 arm_BIC_S_VS: "BIC.S.VS", | 6170 arm_BIC_S_VS: "BIC.S.VS", |
4814 arm_BIC_S_VC: "BIC.S.VC", | 6171 arm_BIC_S_VC: "BIC.S.VC", |
4815 arm_BIC_S_HI: "BIC.S.HI", | 6172 arm_BIC_S_HI: "BIC.S.HI", |
4816 arm_BIC_S_LS: "BIC.S.LS", | 6173 arm_BIC_S_LS: "BIC.S.LS", |
4817 arm_BIC_S_GE: "BIC.S.GE", | 6174 arm_BIC_S_GE: "BIC.S.GE", |
4818 arm_BIC_S_LT: "BIC.S.LT", | 6175 arm_BIC_S_LT: "BIC.S.LT", |
4819 arm_BIC_S_GT: "BIC.S.GT", | 6176 arm_BIC_S_GT: "BIC.S.GT", |
4820 arm_BIC_S_LE: "BIC.S.LE", | 6177 arm_BIC_S_LE: "BIC.S.LE", |
4821 arm_BIC_S: "BIC.S", | 6178 arm_BIC_S: "BIC.S", |
4822 arm_BIC_S_ZZ: "BIC.S.ZZ", | 6179 arm_BIC_S_ZZ: "BIC.S.ZZ", |
4823 arm_BKPT_EQ: "BKPT.EQ", | 6180 arm_BKPT_EQ: "BKPT.EQ", |
4824 arm_BKPT_NE: "BKPT.NE", | 6181 arm_BKPT_NE: "BKPT.NE", |
4825 arm_BKPT_CS: "BKPT.CS", | 6182 arm_BKPT_CS: "BKPT.CS", |
4826 arm_BKPT_CC: "BKPT.CC", | 6183 arm_BKPT_CC: "BKPT.CC", |
4827 arm_BKPT_MI: "BKPT.MI", | 6184 arm_BKPT_MI: "BKPT.MI", |
4828 arm_BKPT_PL: "BKPT.PL", | 6185 arm_BKPT_PL: "BKPT.PL", |
4829 arm_BKPT_VS: "BKPT.VS", | 6186 arm_BKPT_VS: "BKPT.VS", |
4830 arm_BKPT_VC: "BKPT.VC", | 6187 arm_BKPT_VC: "BKPT.VC", |
4831 arm_BKPT_HI: "BKPT.HI", | 6188 arm_BKPT_HI: "BKPT.HI", |
4832 arm_BKPT_LS: "BKPT.LS", | 6189 arm_BKPT_LS: "BKPT.LS", |
4833 arm_BKPT_GE: "BKPT.GE", | 6190 arm_BKPT_GE: "BKPT.GE", |
4834 arm_BKPT_LT: "BKPT.LT", | 6191 arm_BKPT_LT: "BKPT.LT", |
4835 arm_BKPT_GT: "BKPT.GT", | 6192 arm_BKPT_GT: "BKPT.GT", |
4836 arm_BKPT_LE: "BKPT.LE", | 6193 arm_BKPT_LE: "BKPT.LE", |
4837 arm_BKPT: "BKPT", | 6194 arm_BKPT: "BKPT", |
4838 arm_BKPT_ZZ: "BKPT.ZZ", | 6195 arm_BKPT_ZZ: "BKPT.ZZ", |
4839 arm_BL_EQ: "BL.EQ", | 6196 arm_BL_EQ: "BL.EQ", |
4840 arm_BL_NE: "BL.NE", | 6197 arm_BL_NE: "BL.NE", |
4841 arm_BL_CS: "BL.CS", | 6198 arm_BL_CS: "BL.CS", |
4842 arm_BL_CC: "BL.CC", | 6199 arm_BL_CC: "BL.CC", |
4843 arm_BL_MI: "BL.MI", | 6200 arm_BL_MI: "BL.MI", |
4844 arm_BL_PL: "BL.PL", | 6201 arm_BL_PL: "BL.PL", |
4845 arm_BL_VS: "BL.VS", | 6202 arm_BL_VS: "BL.VS", |
4846 arm_BL_VC: "BL.VC", | 6203 arm_BL_VC: "BL.VC", |
4847 arm_BL_HI: "BL.HI", | 6204 arm_BL_HI: "BL.HI", |
4848 arm_BL_LS: "BL.LS", | 6205 arm_BL_LS: "BL.LS", |
4849 arm_BL_GE: "BL.GE", | 6206 arm_BL_GE: "BL.GE", |
4850 arm_BL_LT: "BL.LT", | 6207 arm_BL_LT: "BL.LT", |
4851 arm_BL_GT: "BL.GT", | 6208 arm_BL_GT: "BL.GT", |
4852 arm_BL_LE: "BL.LE", | 6209 arm_BL_LE: "BL.LE", |
4853 arm_BL: "BL", | 6210 arm_BL: "BL", |
4854 arm_BL_ZZ: "BL.ZZ", | 6211 arm_BL_ZZ: "BL.ZZ", |
4855 arm_BLX_EQ: "BLX.EQ", | 6212 arm_BLX_EQ: "BLX.EQ", |
4856 arm_BLX_NE: "BLX.NE", | 6213 arm_BLX_NE: "BLX.NE", |
4857 arm_BLX_CS: "BLX.CS", | 6214 arm_BLX_CS: "BLX.CS", |
4858 arm_BLX_CC: "BLX.CC", | 6215 arm_BLX_CC: "BLX.CC", |
4859 arm_BLX_MI: "BLX.MI", | 6216 arm_BLX_MI: "BLX.MI", |
4860 arm_BLX_PL: "BLX.PL", | 6217 arm_BLX_PL: "BLX.PL", |
4861 arm_BLX_VS: "BLX.VS", | 6218 arm_BLX_VS: "BLX.VS", |
4862 arm_BLX_VC: "BLX.VC", | 6219 arm_BLX_VC: "BLX.VC", |
4863 arm_BLX_HI: "BLX.HI", | 6220 arm_BLX_HI: "BLX.HI", |
4864 arm_BLX_LS: "BLX.LS", | 6221 arm_BLX_LS: "BLX.LS", |
4865 arm_BLX_GE: "BLX.GE", | 6222 arm_BLX_GE: "BLX.GE", |
4866 arm_BLX_LT: "BLX.LT", | 6223 arm_BLX_LT: "BLX.LT", |
4867 arm_BLX_GT: "BLX.GT", | 6224 arm_BLX_GT: "BLX.GT", |
4868 arm_BLX_LE: "BLX.LE", | 6225 arm_BLX_LE: "BLX.LE", |
4869 arm_BLX: "BLX", | 6226 arm_BLX: "BLX", |
4870 arm_BLX_ZZ: "BLX.ZZ", | 6227 arm_BLX_ZZ: "BLX.ZZ", |
4871 arm_BX_EQ: "BX.EQ", | 6228 arm_BX_EQ: "BX.EQ", |
4872 arm_BX_NE: "BX.NE", | 6229 arm_BX_NE: "BX.NE", |
4873 arm_BX_CS: "BX.CS", | 6230 arm_BX_CS: "BX.CS", |
4874 arm_BX_CC: "BX.CC", | 6231 arm_BX_CC: "BX.CC", |
4875 arm_BX_MI: "BX.MI", | 6232 arm_BX_MI: "BX.MI", |
4876 arm_BX_PL: "BX.PL", | 6233 arm_BX_PL: "BX.PL", |
4877 arm_BX_VS: "BX.VS", | 6234 arm_BX_VS: "BX.VS", |
4878 arm_BX_VC: "BX.VC", | 6235 arm_BX_VC: "BX.VC", |
4879 arm_BX_HI: "BX.HI", | 6236 arm_BX_HI: "BX.HI", |
4880 arm_BX_LS: "BX.LS", | 6237 arm_BX_LS: "BX.LS", |
4881 arm_BX_GE: "BX.GE", | 6238 arm_BX_GE: "BX.GE", |
4882 arm_BX_LT: "BX.LT", | 6239 arm_BX_LT: "BX.LT", |
4883 arm_BX_GT: "BX.GT", | 6240 arm_BX_GT: "BX.GT", |
4884 arm_BX_LE: "BX.LE", | 6241 arm_BX_LE: "BX.LE", |
4885 arm_BX: "BX", | 6242 arm_BX: "BX", |
4886 arm_BX_ZZ: "BX.ZZ", | 6243 arm_BX_ZZ: "BX.ZZ", |
4887 arm_BXJ_EQ: "BXJ.EQ", | 6244 arm_BXJ_EQ: "BXJ.EQ", |
4888 arm_BXJ_NE: "BXJ.NE", | 6245 arm_BXJ_NE: "BXJ.NE", |
4889 arm_BXJ_CS: "BXJ.CS", | 6246 arm_BXJ_CS: "BXJ.CS", |
4890 arm_BXJ_CC: "BXJ.CC", | 6247 arm_BXJ_CC: "BXJ.CC", |
4891 arm_BXJ_MI: "BXJ.MI", | 6248 arm_BXJ_MI: "BXJ.MI", |
4892 arm_BXJ_PL: "BXJ.PL", | 6249 arm_BXJ_PL: "BXJ.PL", |
4893 arm_BXJ_VS: "BXJ.VS", | 6250 arm_BXJ_VS: "BXJ.VS", |
4894 arm_BXJ_VC: "BXJ.VC", | 6251 arm_BXJ_VC: "BXJ.VC", |
4895 arm_BXJ_HI: "BXJ.HI", | 6252 arm_BXJ_HI: "BXJ.HI", |
4896 arm_BXJ_LS: "BXJ.LS", | 6253 arm_BXJ_LS: "BXJ.LS", |
4897 arm_BXJ_GE: "BXJ.GE", | 6254 arm_BXJ_GE: "BXJ.GE", |
4898 arm_BXJ_LT: "BXJ.LT", | 6255 arm_BXJ_LT: "BXJ.LT", |
4899 arm_BXJ_GT: "BXJ.GT", | 6256 arm_BXJ_GT: "BXJ.GT", |
4900 arm_BXJ_LE: "BXJ.LE", | 6257 arm_BXJ_LE: "BXJ.LE", |
4901 arm_BXJ: "BXJ", | 6258 arm_BXJ: "BXJ", |
4902 arm_BXJ_ZZ: "BXJ.ZZ", | 6259 arm_BXJ_ZZ: "BXJ.ZZ", |
4903 arm_CLREX: "CLREX", | 6260 arm_CLREX: "CLREX", |
4904 arm_CLZ_EQ: "CLZ.EQ", | 6261 arm_CLZ_EQ: "CLZ.EQ", |
4905 arm_CLZ_NE: "CLZ.NE", | 6262 arm_CLZ_NE: "CLZ.NE", |
4906 arm_CLZ_CS: "CLZ.CS", | 6263 arm_CLZ_CS: "CLZ.CS", |
4907 arm_CLZ_CC: "CLZ.CC", | 6264 arm_CLZ_CC: "CLZ.CC", |
4908 arm_CLZ_MI: "CLZ.MI", | 6265 arm_CLZ_MI: "CLZ.MI", |
4909 arm_CLZ_PL: "CLZ.PL", | 6266 arm_CLZ_PL: "CLZ.PL", |
4910 arm_CLZ_VS: "CLZ.VS", | 6267 arm_CLZ_VS: "CLZ.VS", |
4911 arm_CLZ_VC: "CLZ.VC", | 6268 arm_CLZ_VC: "CLZ.VC", |
4912 arm_CLZ_HI: "CLZ.HI", | 6269 arm_CLZ_HI: "CLZ.HI", |
4913 arm_CLZ_LS: "CLZ.LS", | 6270 arm_CLZ_LS: "CLZ.LS", |
4914 arm_CLZ_GE: "CLZ.GE", | 6271 arm_CLZ_GE: "CLZ.GE", |
4915 arm_CLZ_LT: "CLZ.LT", | 6272 arm_CLZ_LT: "CLZ.LT", |
4916 arm_CLZ_GT: "CLZ.GT", | 6273 arm_CLZ_GT: "CLZ.GT", |
4917 arm_CLZ_LE: "CLZ.LE", | 6274 arm_CLZ_LE: "CLZ.LE", |
4918 arm_CLZ: "CLZ", | 6275 arm_CLZ: "CLZ", |
4919 arm_CLZ_ZZ: "CLZ.ZZ", | 6276 arm_CLZ_ZZ: "CLZ.ZZ", |
4920 arm_CMN_EQ: "CMN.EQ", | 6277 arm_CMN_EQ: "CMN.EQ", |
4921 arm_CMN_NE: "CMN.NE", | 6278 arm_CMN_NE: "CMN.NE", |
4922 arm_CMN_CS: "CMN.CS", | 6279 arm_CMN_CS: "CMN.CS", |
4923 arm_CMN_CC: "CMN.CC", | 6280 arm_CMN_CC: "CMN.CC", |
4924 arm_CMN_MI: "CMN.MI", | 6281 arm_CMN_MI: "CMN.MI", |
4925 arm_CMN_PL: "CMN.PL", | 6282 arm_CMN_PL: "CMN.PL", |
4926 arm_CMN_VS: "CMN.VS", | 6283 arm_CMN_VS: "CMN.VS", |
4927 arm_CMN_VC: "CMN.VC", | 6284 arm_CMN_VC: "CMN.VC", |
4928 arm_CMN_HI: "CMN.HI", | 6285 arm_CMN_HI: "CMN.HI", |
4929 arm_CMN_LS: "CMN.LS", | 6286 arm_CMN_LS: "CMN.LS", |
4930 arm_CMN_GE: "CMN.GE", | 6287 arm_CMN_GE: "CMN.GE", |
4931 arm_CMN_LT: "CMN.LT", | 6288 arm_CMN_LT: "CMN.LT", |
4932 arm_CMN_GT: "CMN.GT", | 6289 arm_CMN_GT: "CMN.GT", |
4933 arm_CMN_LE: "CMN.LE", | 6290 arm_CMN_LE: "CMN.LE", |
4934 arm_CMN: "CMN", | 6291 arm_CMN: "CMN", |
4935 arm_CMN_ZZ: "CMN.ZZ", | 6292 arm_CMN_ZZ: "CMN.ZZ", |
4936 arm_CMP_EQ: "CMP.EQ", | 6293 arm_CMP_EQ: "CMP.EQ", |
4937 arm_CMP_NE: "CMP.NE", | 6294 arm_CMP_NE: "CMP.NE", |
4938 arm_CMP_CS: "CMP.CS", | 6295 arm_CMP_CS: "CMP.CS", |
4939 arm_CMP_CC: "CMP.CC", | 6296 arm_CMP_CC: "CMP.CC", |
4940 arm_CMP_MI: "CMP.MI", | 6297 arm_CMP_MI: "CMP.MI", |
4941 arm_CMP_PL: "CMP.PL", | 6298 arm_CMP_PL: "CMP.PL", |
4942 arm_CMP_VS: "CMP.VS", | 6299 arm_CMP_VS: "CMP.VS", |
4943 arm_CMP_VC: "CMP.VC", | 6300 arm_CMP_VC: "CMP.VC", |
4944 arm_CMP_HI: "CMP.HI", | 6301 arm_CMP_HI: "CMP.HI", |
4945 arm_CMP_LS: "CMP.LS", | 6302 arm_CMP_LS: "CMP.LS", |
4946 arm_CMP_GE: "CMP.GE", | 6303 arm_CMP_GE: "CMP.GE", |
4947 arm_CMP_LT: "CMP.LT", | 6304 arm_CMP_LT: "CMP.LT", |
4948 arm_CMP_GT: "CMP.GT", | 6305 arm_CMP_GT: "CMP.GT", |
4949 arm_CMP_LE: "CMP.LE", | 6306 arm_CMP_LE: "CMP.LE", |
4950 arm_CMP: "CMP", | 6307 arm_CMP: "CMP", |
4951 arm_CMP_ZZ: "CMP.ZZ", | 6308 arm_CMP_ZZ: "CMP.ZZ", |
4952 arm_DBG_EQ: "DBG.EQ", | 6309 arm_DBG_EQ: "DBG.EQ", |
4953 arm_DBG_NE: "DBG.NE", | 6310 arm_DBG_NE: "DBG.NE", |
4954 arm_DBG_CS: "DBG.CS", | 6311 arm_DBG_CS: "DBG.CS", |
4955 arm_DBG_CC: "DBG.CC", | 6312 arm_DBG_CC: "DBG.CC", |
4956 arm_DBG_MI: "DBG.MI", | 6313 arm_DBG_MI: "DBG.MI", |
4957 arm_DBG_PL: "DBG.PL", | 6314 arm_DBG_PL: "DBG.PL", |
4958 arm_DBG_VS: "DBG.VS", | 6315 arm_DBG_VS: "DBG.VS", |
4959 arm_DBG_VC: "DBG.VC", | 6316 arm_DBG_VC: "DBG.VC", |
4960 arm_DBG_HI: "DBG.HI", | 6317 arm_DBG_HI: "DBG.HI", |
4961 arm_DBG_LS: "DBG.LS", | 6318 arm_DBG_LS: "DBG.LS", |
4962 arm_DBG_GE: "DBG.GE", | 6319 arm_DBG_GE: "DBG.GE", |
4963 arm_DBG_LT: "DBG.LT", | 6320 arm_DBG_LT: "DBG.LT", |
4964 arm_DBG_GT: "DBG.GT", | 6321 arm_DBG_GT: "DBG.GT", |
4965 arm_DBG_LE: "DBG.LE", | 6322 arm_DBG_LE: "DBG.LE", |
4966 arm_DBG: "DBG", | 6323 arm_DBG: "DBG", |
4967 arm_DBG_ZZ: "DBG.ZZ", | 6324 arm_DBG_ZZ: "DBG.ZZ", |
4968 arm_DMB: "DMB", | 6325 arm_DMB: "DMB", |
4969 arm_DSB: "DSB", | 6326 arm_DSB: "DSB", |
4970 arm_EOR_EQ: "EOR.EQ", | 6327 arm_EOR_EQ: "EOR.EQ", |
4971 arm_EOR_NE: "EOR.NE", | 6328 arm_EOR_NE: "EOR.NE", |
4972 arm_EOR_CS: "EOR.CS", | 6329 arm_EOR_CS: "EOR.CS", |
4973 arm_EOR_CC: "EOR.CC", | 6330 arm_EOR_CC: "EOR.CC", |
4974 arm_EOR_MI: "EOR.MI", | 6331 arm_EOR_MI: "EOR.MI", |
4975 arm_EOR_PL: "EOR.PL", | 6332 arm_EOR_PL: "EOR.PL", |
4976 arm_EOR_VS: "EOR.VS", | 6333 arm_EOR_VS: "EOR.VS", |
4977 arm_EOR_VC: "EOR.VC", | 6334 arm_EOR_VC: "EOR.VC", |
4978 arm_EOR_HI: "EOR.HI", | 6335 arm_EOR_HI: "EOR.HI", |
4979 arm_EOR_LS: "EOR.LS", | 6336 arm_EOR_LS: "EOR.LS", |
4980 arm_EOR_GE: "EOR.GE", | 6337 arm_EOR_GE: "EOR.GE", |
4981 arm_EOR_LT: "EOR.LT", | 6338 arm_EOR_LT: "EOR.LT", |
4982 arm_EOR_GT: "EOR.GT", | 6339 arm_EOR_GT: "EOR.GT", |
4983 arm_EOR_LE: "EOR.LE", | 6340 arm_EOR_LE: "EOR.LE", |
4984 arm_EOR: "EOR", | 6341 arm_EOR: "EOR", |
4985 arm_EOR_ZZ: "EOR.ZZ", | 6342 arm_EOR_ZZ: "EOR.ZZ", |
4986 arm_EOR_S_EQ: "EOR.S.EQ", | 6343 arm_EOR_S_EQ: "EOR.S.EQ", |
4987 arm_EOR_S_NE: "EOR.S.NE", | 6344 arm_EOR_S_NE: "EOR.S.NE", |
4988 arm_EOR_S_CS: "EOR.S.CS", | 6345 arm_EOR_S_CS: "EOR.S.CS", |
4989 arm_EOR_S_CC: "EOR.S.CC", | 6346 arm_EOR_S_CC: "EOR.S.CC", |
4990 arm_EOR_S_MI: "EOR.S.MI", | 6347 arm_EOR_S_MI: "EOR.S.MI", |
4991 arm_EOR_S_PL: "EOR.S.PL", | 6348 arm_EOR_S_PL: "EOR.S.PL", |
4992 arm_EOR_S_VS: "EOR.S.VS", | 6349 arm_EOR_S_VS: "EOR.S.VS", |
4993 arm_EOR_S_VC: "EOR.S.VC", | 6350 arm_EOR_S_VC: "EOR.S.VC", |
4994 arm_EOR_S_HI: "EOR.S.HI", | 6351 arm_EOR_S_HI: "EOR.S.HI", |
4995 arm_EOR_S_LS: "EOR.S.LS", | 6352 arm_EOR_S_LS: "EOR.S.LS", |
4996 arm_EOR_S_GE: "EOR.S.GE", | 6353 arm_EOR_S_GE: "EOR.S.GE", |
4997 arm_EOR_S_LT: "EOR.S.LT", | 6354 arm_EOR_S_LT: "EOR.S.LT", |
4998 arm_EOR_S_GT: "EOR.S.GT", | 6355 arm_EOR_S_GT: "EOR.S.GT", |
4999 arm_EOR_S_LE: "EOR.S.LE", | 6356 arm_EOR_S_LE: "EOR.S.LE", |
5000 arm_EOR_S: "EOR.S", | 6357 arm_EOR_S: "EOR.S", |
5001 arm_EOR_S_ZZ: "EOR.S.ZZ", | 6358 arm_EOR_S_ZZ: "EOR.S.ZZ", |
5002 arm_ISB: "ISB", | 6359 arm_ISB: "ISB", |
5003 arm_LDM_EQ: "LDM.EQ", | 6360 arm_LDM_EQ: "LDM.EQ", |
5004 arm_LDM_NE: "LDM.NE", | 6361 arm_LDM_NE: "LDM.NE", |
5005 arm_LDM_CS: "LDM.CS", | 6362 arm_LDM_CS: "LDM.CS", |
5006 arm_LDM_CC: "LDM.CC", | 6363 arm_LDM_CC: "LDM.CC", |
5007 arm_LDM_MI: "LDM.MI", | 6364 arm_LDM_MI: "LDM.MI", |
5008 arm_LDM_PL: "LDM.PL", | 6365 arm_LDM_PL: "LDM.PL", |
5009 arm_LDM_VS: "LDM.VS", | 6366 arm_LDM_VS: "LDM.VS", |
5010 arm_LDM_VC: "LDM.VC", | 6367 arm_LDM_VC: "LDM.VC", |
5011 arm_LDM_HI: "LDM.HI", | 6368 arm_LDM_HI: "LDM.HI", |
5012 arm_LDM_LS: "LDM.LS", | 6369 arm_LDM_LS: "LDM.LS", |
5013 arm_LDM_GE: "LDM.GE", | 6370 arm_LDM_GE: "LDM.GE", |
5014 arm_LDM_LT: "LDM.LT", | 6371 arm_LDM_LT: "LDM.LT", |
5015 arm_LDM_GT: "LDM.GT", | 6372 arm_LDM_GT: "LDM.GT", |
5016 arm_LDM_LE: "LDM.LE", | 6373 arm_LDM_LE: "LDM.LE", |
5017 arm_LDM: "LDM", | 6374 arm_LDM: "LDM", |
5018 arm_LDM_ZZ: "LDM.ZZ", | 6375 arm_LDM_ZZ: "LDM.ZZ", |
5019 arm_LDMDA_EQ: "LDMDA.EQ", | 6376 arm_LDMDA_EQ: "LDMDA.EQ", |
5020 arm_LDMDA_NE: "LDMDA.NE", | 6377 arm_LDMDA_NE: "LDMDA.NE", |
5021 arm_LDMDA_CS: "LDMDA.CS", | 6378 arm_LDMDA_CS: "LDMDA.CS", |
5022 arm_LDMDA_CC: "LDMDA.CC", | 6379 arm_LDMDA_CC: "LDMDA.CC", |
5023 arm_LDMDA_MI: "LDMDA.MI", | 6380 arm_LDMDA_MI: "LDMDA.MI", |
5024 arm_LDMDA_PL: "LDMDA.PL", | 6381 arm_LDMDA_PL: "LDMDA.PL", |
5025 arm_LDMDA_VS: "LDMDA.VS", | 6382 arm_LDMDA_VS: "LDMDA.VS", |
5026 arm_LDMDA_VC: "LDMDA.VC", | 6383 arm_LDMDA_VC: "LDMDA.VC", |
5027 arm_LDMDA_HI: "LDMDA.HI", | 6384 arm_LDMDA_HI: "LDMDA.HI", |
5028 arm_LDMDA_LS: "LDMDA.LS", | 6385 arm_LDMDA_LS: "LDMDA.LS", |
5029 arm_LDMDA_GE: "LDMDA.GE", | 6386 arm_LDMDA_GE: "LDMDA.GE", |
5030 arm_LDMDA_LT: "LDMDA.LT", | 6387 arm_LDMDA_LT: "LDMDA.LT", |
5031 arm_LDMDA_GT: "LDMDA.GT", | 6388 arm_LDMDA_GT: "LDMDA.GT", |
5032 arm_LDMDA_LE: "LDMDA.LE", | 6389 arm_LDMDA_LE: "LDMDA.LE", |
5033 arm_LDMDA: "LDMDA", | 6390 arm_LDMDA: "LDMDA", |
5034 arm_LDMDA_ZZ: "LDMDA.ZZ", | 6391 arm_LDMDA_ZZ: "LDMDA.ZZ", |
5035 arm_LDMDB_EQ: "LDMDB.EQ", | 6392 arm_LDMDB_EQ: "LDMDB.EQ", |
5036 arm_LDMDB_NE: "LDMDB.NE", | 6393 arm_LDMDB_NE: "LDMDB.NE", |
5037 arm_LDMDB_CS: "LDMDB.CS", | 6394 arm_LDMDB_CS: "LDMDB.CS", |
5038 arm_LDMDB_CC: "LDMDB.CC", | 6395 arm_LDMDB_CC: "LDMDB.CC", |
5039 arm_LDMDB_MI: "LDMDB.MI", | 6396 arm_LDMDB_MI: "LDMDB.MI", |
5040 arm_LDMDB_PL: "LDMDB.PL", | 6397 arm_LDMDB_PL: "LDMDB.PL", |
5041 arm_LDMDB_VS: "LDMDB.VS", | 6398 arm_LDMDB_VS: "LDMDB.VS", |
5042 arm_LDMDB_VC: "LDMDB.VC", | 6399 arm_LDMDB_VC: "LDMDB.VC", |
5043 arm_LDMDB_HI: "LDMDB.HI", | 6400 arm_LDMDB_HI: "LDMDB.HI", |
5044 arm_LDMDB_LS: "LDMDB.LS", | 6401 arm_LDMDB_LS: "LDMDB.LS", |
5045 arm_LDMDB_GE: "LDMDB.GE", | 6402 arm_LDMDB_GE: "LDMDB.GE", |
5046 arm_LDMDB_LT: "LDMDB.LT", | 6403 arm_LDMDB_LT: "LDMDB.LT", |
5047 arm_LDMDB_GT: "LDMDB.GT", | 6404 arm_LDMDB_GT: "LDMDB.GT", |
5048 arm_LDMDB_LE: "LDMDB.LE", | 6405 arm_LDMDB_LE: "LDMDB.LE", |
5049 arm_LDMDB: "LDMDB", | 6406 arm_LDMDB: "LDMDB", |
5050 arm_LDMDB_ZZ: "LDMDB.ZZ", | 6407 arm_LDMDB_ZZ: "LDMDB.ZZ", |
5051 arm_LDMIB_EQ: "LDMIB.EQ", | 6408 arm_LDMIB_EQ: "LDMIB.EQ", |
5052 arm_LDMIB_NE: "LDMIB.NE", | 6409 arm_LDMIB_NE: "LDMIB.NE", |
5053 arm_LDMIB_CS: "LDMIB.CS", | 6410 arm_LDMIB_CS: "LDMIB.CS", |
5054 arm_LDMIB_CC: "LDMIB.CC", | 6411 arm_LDMIB_CC: "LDMIB.CC", |
5055 arm_LDMIB_MI: "LDMIB.MI", | 6412 arm_LDMIB_MI: "LDMIB.MI", |
5056 arm_LDMIB_PL: "LDMIB.PL", | 6413 arm_LDMIB_PL: "LDMIB.PL", |
5057 arm_LDMIB_VS: "LDMIB.VS", | 6414 arm_LDMIB_VS: "LDMIB.VS", |
5058 arm_LDMIB_VC: "LDMIB.VC", | 6415 arm_LDMIB_VC: "LDMIB.VC", |
5059 arm_LDMIB_HI: "LDMIB.HI", | 6416 arm_LDMIB_HI: "LDMIB.HI", |
5060 arm_LDMIB_LS: "LDMIB.LS", | 6417 arm_LDMIB_LS: "LDMIB.LS", |
5061 arm_LDMIB_GE: "LDMIB.GE", | 6418 arm_LDMIB_GE: "LDMIB.GE", |
5062 arm_LDMIB_LT: "LDMIB.LT", | 6419 arm_LDMIB_LT: "LDMIB.LT", |
5063 arm_LDMIB_GT: "LDMIB.GT", | 6420 arm_LDMIB_GT: "LDMIB.GT", |
5064 arm_LDMIB_LE: "LDMIB.LE", | 6421 arm_LDMIB_LE: "LDMIB.LE", |
5065 arm_LDMIB: "LDMIB", | 6422 arm_LDMIB: "LDMIB", |
5066 arm_LDMIB_ZZ: "LDMIB.ZZ", | 6423 arm_LDMIB_ZZ: "LDMIB.ZZ", |
5067 arm_LDR_EQ: "LDR.EQ", | 6424 arm_LDR_EQ: "LDR.EQ", |
5068 arm_LDR_NE: "LDR.NE", | 6425 arm_LDR_NE: "LDR.NE", |
5069 arm_LDR_CS: "LDR.CS", | 6426 arm_LDR_CS: "LDR.CS", |
5070 arm_LDR_CC: "LDR.CC", | 6427 arm_LDR_CC: "LDR.CC", |
5071 arm_LDR_MI: "LDR.MI", | 6428 arm_LDR_MI: "LDR.MI", |
5072 arm_LDR_PL: "LDR.PL", | 6429 arm_LDR_PL: "LDR.PL", |
5073 arm_LDR_VS: "LDR.VS", | 6430 arm_LDR_VS: "LDR.VS", |
5074 arm_LDR_VC: "LDR.VC", | 6431 arm_LDR_VC: "LDR.VC", |
5075 arm_LDR_HI: "LDR.HI", | 6432 arm_LDR_HI: "LDR.HI", |
5076 arm_LDR_LS: "LDR.LS", | 6433 arm_LDR_LS: "LDR.LS", |
5077 arm_LDR_GE: "LDR.GE", | 6434 arm_LDR_GE: "LDR.GE", |
5078 arm_LDR_LT: "LDR.LT", | 6435 arm_LDR_LT: "LDR.LT", |
5079 arm_LDR_GT: "LDR.GT", | 6436 arm_LDR_GT: "LDR.GT", |
5080 arm_LDR_LE: "LDR.LE", | 6437 arm_LDR_LE: "LDR.LE", |
5081 arm_LDR: "LDR", | 6438 arm_LDR: "LDR", |
5082 arm_LDR_ZZ: "LDR.ZZ", | 6439 arm_LDR_ZZ: "LDR.ZZ", |
5083 arm_LDRB_EQ: "LDRB.EQ", | 6440 arm_LDRB_EQ: "LDRB.EQ", |
5084 arm_LDRB_NE: "LDRB.NE", | 6441 arm_LDRB_NE: "LDRB.NE", |
5085 arm_LDRB_CS: "LDRB.CS", | 6442 arm_LDRB_CS: "LDRB.CS", |
5086 arm_LDRB_CC: "LDRB.CC", | 6443 arm_LDRB_CC: "LDRB.CC", |
5087 arm_LDRB_MI: "LDRB.MI", | 6444 arm_LDRB_MI: "LDRB.MI", |
5088 arm_LDRB_PL: "LDRB.PL", | 6445 arm_LDRB_PL: "LDRB.PL", |
5089 arm_LDRB_VS: "LDRB.VS", | 6446 arm_LDRB_VS: "LDRB.VS", |
5090 arm_LDRB_VC: "LDRB.VC", | 6447 arm_LDRB_VC: "LDRB.VC", |
5091 arm_LDRB_HI: "LDRB.HI", | 6448 arm_LDRB_HI: "LDRB.HI", |
5092 arm_LDRB_LS: "LDRB.LS", | 6449 arm_LDRB_LS: "LDRB.LS", |
5093 arm_LDRB_GE: "LDRB.GE", | 6450 arm_LDRB_GE: "LDRB.GE", |
5094 arm_LDRB_LT: "LDRB.LT", | 6451 arm_LDRB_LT: "LDRB.LT", |
5095 arm_LDRB_GT: "LDRB.GT", | 6452 arm_LDRB_GT: "LDRB.GT", |
5096 arm_LDRB_LE: "LDRB.LE", | 6453 arm_LDRB_LE: "LDRB.LE", |
5097 arm_LDRB: "LDRB", | 6454 arm_LDRB: "LDRB", |
5098 arm_LDRB_ZZ: "LDRB.ZZ", | 6455 arm_LDRB_ZZ: "LDRB.ZZ", |
5099 arm_LDRBT_EQ: "LDRBT.EQ", | 6456 arm_LDRBT_EQ: "LDRBT.EQ", |
5100 arm_LDRBT_NE: "LDRBT.NE", | 6457 arm_LDRBT_NE: "LDRBT.NE", |
5101 arm_LDRBT_CS: "LDRBT.CS", | 6458 arm_LDRBT_CS: "LDRBT.CS", |
5102 arm_LDRBT_CC: "LDRBT.CC", | 6459 arm_LDRBT_CC: "LDRBT.CC", |
5103 arm_LDRBT_MI: "LDRBT.MI", | 6460 arm_LDRBT_MI: "LDRBT.MI", |
5104 arm_LDRBT_PL: "LDRBT.PL", | 6461 arm_LDRBT_PL: "LDRBT.PL", |
5105 arm_LDRBT_VS: "LDRBT.VS", | 6462 arm_LDRBT_VS: "LDRBT.VS", |
5106 arm_LDRBT_VC: "LDRBT.VC", | 6463 arm_LDRBT_VC: "LDRBT.VC", |
5107 arm_LDRBT_HI: "LDRBT.HI", | 6464 arm_LDRBT_HI: "LDRBT.HI", |
5108 arm_LDRBT_LS: "LDRBT.LS", | 6465 arm_LDRBT_LS: "LDRBT.LS", |
5109 arm_LDRBT_GE: "LDRBT.GE", | 6466 arm_LDRBT_GE: "LDRBT.GE", |
5110 arm_LDRBT_LT: "LDRBT.LT", | 6467 arm_LDRBT_LT: "LDRBT.LT", |
5111 arm_LDRBT_GT: "LDRBT.GT", | 6468 arm_LDRBT_GT: "LDRBT.GT", |
5112 arm_LDRBT_LE: "LDRBT.LE", | 6469 arm_LDRBT_LE: "LDRBT.LE", |
5113 arm_LDRBT: "LDRBT", | 6470 arm_LDRBT: "LDRBT", |
5114 arm_LDRBT_ZZ: "LDRBT.ZZ", | 6471 arm_LDRBT_ZZ: "LDRBT.ZZ", |
5115 arm_LDRD_EQ: "LDRD.EQ", | 6472 arm_LDRD_EQ: "LDRD.EQ", |
5116 arm_LDRD_NE: "LDRD.NE", | 6473 arm_LDRD_NE: "LDRD.NE", |
5117 arm_LDRD_CS: "LDRD.CS", | 6474 arm_LDRD_CS: "LDRD.CS", |
5118 arm_LDRD_CC: "LDRD.CC", | 6475 arm_LDRD_CC: "LDRD.CC", |
5119 arm_LDRD_MI: "LDRD.MI", | 6476 arm_LDRD_MI: "LDRD.MI", |
5120 arm_LDRD_PL: "LDRD.PL", | 6477 arm_LDRD_PL: "LDRD.PL", |
5121 arm_LDRD_VS: "LDRD.VS", | 6478 arm_LDRD_VS: "LDRD.VS", |
5122 arm_LDRD_VC: "LDRD.VC", | 6479 arm_LDRD_VC: "LDRD.VC", |
5123 arm_LDRD_HI: "LDRD.HI", | 6480 arm_LDRD_HI: "LDRD.HI", |
5124 arm_LDRD_LS: "LDRD.LS", | 6481 arm_LDRD_LS: "LDRD.LS", |
5125 arm_LDRD_GE: "LDRD.GE", | 6482 arm_LDRD_GE: "LDRD.GE", |
5126 arm_LDRD_LT: "LDRD.LT", | 6483 arm_LDRD_LT: "LDRD.LT", |
5127 arm_LDRD_GT: "LDRD.GT", | 6484 arm_LDRD_GT: "LDRD.GT", |
5128 arm_LDRD_LE: "LDRD.LE", | 6485 arm_LDRD_LE: "LDRD.LE", |
5129 arm_LDRD: "LDRD", | 6486 arm_LDRD: "LDRD", |
5130 arm_LDRD_ZZ: "LDRD.ZZ", | 6487 arm_LDRD_ZZ: "LDRD.ZZ", |
5131 arm_LDREX_EQ: "LDREX.EQ", | 6488 arm_LDREX_EQ: "LDREX.EQ", |
5132 arm_LDREX_NE: "LDREX.NE", | 6489 arm_LDREX_NE: "LDREX.NE", |
5133 arm_LDREX_CS: "LDREX.CS", | 6490 arm_LDREX_CS: "LDREX.CS", |
5134 arm_LDREX_CC: "LDREX.CC", | 6491 arm_LDREX_CC: "LDREX.CC", |
5135 arm_LDREX_MI: "LDREX.MI", | 6492 arm_LDREX_MI: "LDREX.MI", |
5136 arm_LDREX_PL: "LDREX.PL", | 6493 arm_LDREX_PL: "LDREX.PL", |
5137 arm_LDREX_VS: "LDREX.VS", | 6494 arm_LDREX_VS: "LDREX.VS", |
5138 arm_LDREX_VC: "LDREX.VC", | 6495 arm_LDREX_VC: "LDREX.VC", |
5139 arm_LDREX_HI: "LDREX.HI", | 6496 arm_LDREX_HI: "LDREX.HI", |
5140 arm_LDREX_LS: "LDREX.LS", | 6497 arm_LDREX_LS: "LDREX.LS", |
5141 arm_LDREX_GE: "LDREX.GE", | 6498 arm_LDREX_GE: "LDREX.GE", |
5142 arm_LDREX_LT: "LDREX.LT", | 6499 arm_LDREX_LT: "LDREX.LT", |
5143 arm_LDREX_GT: "LDREX.GT", | 6500 arm_LDREX_GT: "LDREX.GT", |
5144 arm_LDREX_LE: "LDREX.LE", | 6501 arm_LDREX_LE: "LDREX.LE", |
5145 arm_LDREX: "LDREX", | 6502 arm_LDREX: "LDREX", |
5146 arm_LDREX_ZZ: "LDREX.ZZ", | 6503 arm_LDREX_ZZ: "LDREX.ZZ", |
5147 arm_LDREXB_EQ: "LDREXB.EQ", | 6504 arm_LDREXB_EQ: "LDREXB.EQ", |
5148 arm_LDREXB_NE: "LDREXB.NE", | 6505 arm_LDREXB_NE: "LDREXB.NE", |
5149 arm_LDREXB_CS: "LDREXB.CS", | 6506 arm_LDREXB_CS: "LDREXB.CS", |
5150 arm_LDREXB_CC: "LDREXB.CC", | 6507 arm_LDREXB_CC: "LDREXB.CC", |
5151 arm_LDREXB_MI: "LDREXB.MI", | 6508 arm_LDREXB_MI: "LDREXB.MI", |
5152 arm_LDREXB_PL: "LDREXB.PL", | 6509 arm_LDREXB_PL: "LDREXB.PL", |
5153 arm_LDREXB_VS: "LDREXB.VS", | 6510 arm_LDREXB_VS: "LDREXB.VS", |
5154 arm_LDREXB_VC: "LDREXB.VC", | 6511 arm_LDREXB_VC: "LDREXB.VC", |
5155 arm_LDREXB_HI: "LDREXB.HI", | 6512 arm_LDREXB_HI: "LDREXB.HI", |
5156 arm_LDREXB_LS: "LDREXB.LS", | 6513 arm_LDREXB_LS: "LDREXB.LS", |
5157 arm_LDREXB_GE: "LDREXB.GE", | 6514 arm_LDREXB_GE: "LDREXB.GE", |
5158 arm_LDREXB_LT: "LDREXB.LT", | 6515 arm_LDREXB_LT: "LDREXB.LT", |
5159 arm_LDREXB_GT: "LDREXB.GT", | 6516 arm_LDREXB_GT: "LDREXB.GT", |
5160 arm_LDREXB_LE: "LDREXB.LE", | 6517 arm_LDREXB_LE: "LDREXB.LE", |
5161 arm_LDREXB: "LDREXB", | 6518 arm_LDREXB: "LDREXB", |
5162 arm_LDREXB_ZZ: "LDREXB.ZZ", | 6519 arm_LDREXB_ZZ: "LDREXB.ZZ", |
5163 arm_LDREXD_EQ: "LDREXD.EQ", | 6520 arm_LDREXD_EQ: "LDREXD.EQ", |
5164 arm_LDREXD_NE: "LDREXD.NE", | 6521 arm_LDREXD_NE: "LDREXD.NE", |
5165 arm_LDREXD_CS: "LDREXD.CS", | 6522 arm_LDREXD_CS: "LDREXD.CS", |
5166 arm_LDREXD_CC: "LDREXD.CC", | 6523 arm_LDREXD_CC: "LDREXD.CC", |
5167 arm_LDREXD_MI: "LDREXD.MI", | 6524 arm_LDREXD_MI: "LDREXD.MI", |
5168 arm_LDREXD_PL: "LDREXD.PL", | 6525 arm_LDREXD_PL: "LDREXD.PL", |
5169 arm_LDREXD_VS: "LDREXD.VS", | 6526 arm_LDREXD_VS: "LDREXD.VS", |
5170 arm_LDREXD_VC: "LDREXD.VC", | 6527 arm_LDREXD_VC: "LDREXD.VC", |
5171 arm_LDREXD_HI: "LDREXD.HI", | 6528 arm_LDREXD_HI: "LDREXD.HI", |
5172 arm_LDREXD_LS: "LDREXD.LS", | 6529 arm_LDREXD_LS: "LDREXD.LS", |
5173 arm_LDREXD_GE: "LDREXD.GE", | 6530 arm_LDREXD_GE: "LDREXD.GE", |
5174 arm_LDREXD_LT: "LDREXD.LT", | 6531 arm_LDREXD_LT: "LDREXD.LT", |
5175 arm_LDREXD_GT: "LDREXD.GT", | 6532 arm_LDREXD_GT: "LDREXD.GT", |
5176 arm_LDREXD_LE: "LDREXD.LE", | 6533 arm_LDREXD_LE: "LDREXD.LE", |
5177 arm_LDREXD: "LDREXD", | 6534 arm_LDREXD: "LDREXD", |
5178 arm_LDREXD_ZZ: "LDREXD.ZZ", | 6535 arm_LDREXD_ZZ: "LDREXD.ZZ", |
5179 arm_LDREXH_EQ: "LDREXH.EQ", | 6536 arm_LDREXH_EQ: "LDREXH.EQ", |
5180 arm_LDREXH_NE: "LDREXH.NE", | 6537 arm_LDREXH_NE: "LDREXH.NE", |
5181 arm_LDREXH_CS: "LDREXH.CS", | 6538 arm_LDREXH_CS: "LDREXH.CS", |
5182 arm_LDREXH_CC: "LDREXH.CC", | 6539 arm_LDREXH_CC: "LDREXH.CC", |
5183 arm_LDREXH_MI: "LDREXH.MI", | 6540 arm_LDREXH_MI: "LDREXH.MI", |
5184 arm_LDREXH_PL: "LDREXH.PL", | 6541 arm_LDREXH_PL: "LDREXH.PL", |
5185 arm_LDREXH_VS: "LDREXH.VS", | 6542 arm_LDREXH_VS: "LDREXH.VS", |
5186 arm_LDREXH_VC: "LDREXH.VC", | 6543 arm_LDREXH_VC: "LDREXH.VC", |
5187 arm_LDREXH_HI: "LDREXH.HI", | 6544 arm_LDREXH_HI: "LDREXH.HI", |
5188 arm_LDREXH_LS: "LDREXH.LS", | 6545 arm_LDREXH_LS: "LDREXH.LS", |
5189 arm_LDREXH_GE: "LDREXH.GE", | 6546 arm_LDREXH_GE: "LDREXH.GE", |
5190 arm_LDREXH_LT: "LDREXH.LT", | 6547 arm_LDREXH_LT: "LDREXH.LT", |
5191 arm_LDREXH_GT: "LDREXH.GT", | 6548 arm_LDREXH_GT: "LDREXH.GT", |
5192 arm_LDREXH_LE: "LDREXH.LE", | 6549 arm_LDREXH_LE: "LDREXH.LE", |
5193 arm_LDREXH: "LDREXH", | 6550 arm_LDREXH: "LDREXH", |
5194 arm_LDREXH_ZZ: "LDREXH.ZZ", | 6551 arm_LDREXH_ZZ: "LDREXH.ZZ", |
5195 arm_LDRH_EQ: "LDRH.EQ", | 6552 arm_LDRH_EQ: "LDRH.EQ", |
5196 arm_LDRH_NE: "LDRH.NE", | 6553 arm_LDRH_NE: "LDRH.NE", |
5197 arm_LDRH_CS: "LDRH.CS", | 6554 arm_LDRH_CS: "LDRH.CS", |
5198 arm_LDRH_CC: "LDRH.CC", | 6555 arm_LDRH_CC: "LDRH.CC", |
5199 arm_LDRH_MI: "LDRH.MI", | 6556 arm_LDRH_MI: "LDRH.MI", |
5200 arm_LDRH_PL: "LDRH.PL", | 6557 arm_LDRH_PL: "LDRH.PL", |
5201 arm_LDRH_VS: "LDRH.VS", | 6558 arm_LDRH_VS: "LDRH.VS", |
5202 arm_LDRH_VC: "LDRH.VC", | 6559 arm_LDRH_VC: "LDRH.VC", |
5203 arm_LDRH_HI: "LDRH.HI", | 6560 arm_LDRH_HI: "LDRH.HI", |
5204 arm_LDRH_LS: "LDRH.LS", | 6561 arm_LDRH_LS: "LDRH.LS", |
5205 arm_LDRH_GE: "LDRH.GE", | 6562 arm_LDRH_GE: "LDRH.GE", |
5206 arm_LDRH_LT: "LDRH.LT", | 6563 arm_LDRH_LT: "LDRH.LT", |
5207 arm_LDRH_GT: "LDRH.GT", | 6564 arm_LDRH_GT: "LDRH.GT", |
5208 arm_LDRH_LE: "LDRH.LE", | 6565 arm_LDRH_LE: "LDRH.LE", |
5209 arm_LDRH: "LDRH", | 6566 arm_LDRH: "LDRH", |
5210 arm_LDRH_ZZ: "LDRH.ZZ", | 6567 arm_LDRH_ZZ: "LDRH.ZZ", |
5211 arm_LDRHT_EQ: "LDRHT.EQ", | 6568 arm_LDRHT_EQ: "LDRHT.EQ", |
5212 arm_LDRHT_NE: "LDRHT.NE", | 6569 arm_LDRHT_NE: "LDRHT.NE", |
5213 arm_LDRHT_CS: "LDRHT.CS", | 6570 arm_LDRHT_CS: "LDRHT.CS", |
5214 arm_LDRHT_CC: "LDRHT.CC", | 6571 arm_LDRHT_CC: "LDRHT.CC", |
5215 arm_LDRHT_MI: "LDRHT.MI", | 6572 arm_LDRHT_MI: "LDRHT.MI", |
5216 arm_LDRHT_PL: "LDRHT.PL", | 6573 arm_LDRHT_PL: "LDRHT.PL", |
5217 arm_LDRHT_VS: "LDRHT.VS", | 6574 arm_LDRHT_VS: "LDRHT.VS", |
5218 arm_LDRHT_VC: "LDRHT.VC", | 6575 arm_LDRHT_VC: "LDRHT.VC", |
5219 arm_LDRHT_HI: "LDRHT.HI", | 6576 arm_LDRHT_HI: "LDRHT.HI", |
5220 arm_LDRHT_LS: "LDRHT.LS", | 6577 arm_LDRHT_LS: "LDRHT.LS", |
5221 arm_LDRHT_GE: "LDRHT.GE", | 6578 arm_LDRHT_GE: "LDRHT.GE", |
5222 arm_LDRHT_LT: "LDRHT.LT", | 6579 arm_LDRHT_LT: "LDRHT.LT", |
5223 arm_LDRHT_GT: "LDRHT.GT", | 6580 arm_LDRHT_GT: "LDRHT.GT", |
5224 arm_LDRHT_LE: "LDRHT.LE", | 6581 arm_LDRHT_LE: "LDRHT.LE", |
5225 arm_LDRHT: "LDRHT", | 6582 arm_LDRHT: "LDRHT", |
5226 arm_LDRHT_ZZ: "LDRHT.ZZ", | 6583 arm_LDRHT_ZZ: "LDRHT.ZZ", |
5227 arm_LDRSB_EQ: "LDRSB.EQ", | 6584 arm_LDRSB_EQ: "LDRSB.EQ", |
5228 arm_LDRSB_NE: "LDRSB.NE", | 6585 arm_LDRSB_NE: "LDRSB.NE", |
5229 arm_LDRSB_CS: "LDRSB.CS", | 6586 arm_LDRSB_CS: "LDRSB.CS", |
5230 arm_LDRSB_CC: "LDRSB.CC", | 6587 arm_LDRSB_CC: "LDRSB.CC", |
5231 arm_LDRSB_MI: "LDRSB.MI", | 6588 arm_LDRSB_MI: "LDRSB.MI", |
5232 arm_LDRSB_PL: "LDRSB.PL", | 6589 arm_LDRSB_PL: "LDRSB.PL", |
5233 arm_LDRSB_VS: "LDRSB.VS", | 6590 arm_LDRSB_VS: "LDRSB.VS", |
5234 arm_LDRSB_VC: "LDRSB.VC", | 6591 arm_LDRSB_VC: "LDRSB.VC", |
5235 arm_LDRSB_HI: "LDRSB.HI", | 6592 arm_LDRSB_HI: "LDRSB.HI", |
5236 arm_LDRSB_LS: "LDRSB.LS", | 6593 arm_LDRSB_LS: "LDRSB.LS", |
5237 arm_LDRSB_GE: "LDRSB.GE", | 6594 arm_LDRSB_GE: "LDRSB.GE", |
5238 arm_LDRSB_LT: "LDRSB.LT", | 6595 arm_LDRSB_LT: "LDRSB.LT", |
5239 arm_LDRSB_GT: "LDRSB.GT", | 6596 arm_LDRSB_GT: "LDRSB.GT", |
5240 arm_LDRSB_LE: "LDRSB.LE", | 6597 arm_LDRSB_LE: "LDRSB.LE", |
5241 arm_LDRSB: "LDRSB", | 6598 arm_LDRSB: "LDRSB", |
5242 arm_LDRSB_ZZ: "LDRSB.ZZ", | 6599 arm_LDRSB_ZZ: "LDRSB.ZZ", |
5243 arm_LDRSBT_EQ: "LDRSBT.EQ", | 6600 arm_LDRSBT_EQ: "LDRSBT.EQ", |
5244 arm_LDRSBT_NE: "LDRSBT.NE", | 6601 arm_LDRSBT_NE: "LDRSBT.NE", |
5245 arm_LDRSBT_CS: "LDRSBT.CS", | 6602 arm_LDRSBT_CS: "LDRSBT.CS", |
5246 arm_LDRSBT_CC: "LDRSBT.CC", | 6603 arm_LDRSBT_CC: "LDRSBT.CC", |
5247 arm_LDRSBT_MI: "LDRSBT.MI", | 6604 arm_LDRSBT_MI: "LDRSBT.MI", |
5248 arm_LDRSBT_PL: "LDRSBT.PL", | 6605 arm_LDRSBT_PL: "LDRSBT.PL", |
5249 arm_LDRSBT_VS: "LDRSBT.VS", | 6606 arm_LDRSBT_VS: "LDRSBT.VS", |
5250 arm_LDRSBT_VC: "LDRSBT.VC", | 6607 arm_LDRSBT_VC: "LDRSBT.VC", |
5251 arm_LDRSBT_HI: "LDRSBT.HI", | 6608 arm_LDRSBT_HI: "LDRSBT.HI", |
5252 arm_LDRSBT_LS: "LDRSBT.LS", | 6609 arm_LDRSBT_LS: "LDRSBT.LS", |
5253 arm_LDRSBT_GE: "LDRSBT.GE", | 6610 arm_LDRSBT_GE: "LDRSBT.GE", |
5254 arm_LDRSBT_LT: "LDRSBT.LT", | 6611 arm_LDRSBT_LT: "LDRSBT.LT", |
5255 arm_LDRSBT_GT: "LDRSBT.GT", | 6612 arm_LDRSBT_GT: "LDRSBT.GT", |
5256 arm_LDRSBT_LE: "LDRSBT.LE", | 6613 arm_LDRSBT_LE: "LDRSBT.LE", |
5257 arm_LDRSBT: "LDRSBT", | 6614 arm_LDRSBT: "LDRSBT", |
5258 arm_LDRSBT_ZZ: "LDRSBT.ZZ", | 6615 arm_LDRSBT_ZZ: "LDRSBT.ZZ", |
5259 arm_LDRSH_EQ: "LDRSH.EQ", | 6616 arm_LDRSH_EQ: "LDRSH.EQ", |
5260 arm_LDRSH_NE: "LDRSH.NE", | 6617 arm_LDRSH_NE: "LDRSH.NE", |
5261 arm_LDRSH_CS: "LDRSH.CS", | 6618 arm_LDRSH_CS: "LDRSH.CS", |
5262 arm_LDRSH_CC: "LDRSH.CC", | 6619 arm_LDRSH_CC: "LDRSH.CC", |
5263 arm_LDRSH_MI: "LDRSH.MI", | 6620 arm_LDRSH_MI: "LDRSH.MI", |
5264 arm_LDRSH_PL: "LDRSH.PL", | 6621 arm_LDRSH_PL: "LDRSH.PL", |
5265 arm_LDRSH_VS: "LDRSH.VS", | 6622 arm_LDRSH_VS: "LDRSH.VS", |
5266 arm_LDRSH_VC: "LDRSH.VC", | 6623 arm_LDRSH_VC: "LDRSH.VC", |
5267 arm_LDRSH_HI: "LDRSH.HI", | 6624 arm_LDRSH_HI: "LDRSH.HI", |
5268 arm_LDRSH_LS: "LDRSH.LS", | 6625 arm_LDRSH_LS: "LDRSH.LS", |
5269 arm_LDRSH_GE: "LDRSH.GE", | 6626 arm_LDRSH_GE: "LDRSH.GE", |
5270 arm_LDRSH_LT: "LDRSH.LT", | 6627 arm_LDRSH_LT: "LDRSH.LT", |
5271 arm_LDRSH_GT: "LDRSH.GT", | 6628 arm_LDRSH_GT: "LDRSH.GT", |
5272 arm_LDRSH_LE: "LDRSH.LE", | 6629 arm_LDRSH_LE: "LDRSH.LE", |
5273 arm_LDRSH: "LDRSH", | 6630 arm_LDRSH: "LDRSH", |
5274 arm_LDRSH_ZZ: "LDRSH.ZZ", | 6631 arm_LDRSH_ZZ: "LDRSH.ZZ", |
5275 arm_LDRSHT_EQ: "LDRSHT.EQ", | 6632 arm_LDRSHT_EQ: "LDRSHT.EQ", |
5276 arm_LDRSHT_NE: "LDRSHT.NE", | 6633 arm_LDRSHT_NE: "LDRSHT.NE", |
5277 arm_LDRSHT_CS: "LDRSHT.CS", | 6634 arm_LDRSHT_CS: "LDRSHT.CS", |
5278 arm_LDRSHT_CC: "LDRSHT.CC", | 6635 arm_LDRSHT_CC: "LDRSHT.CC", |
5279 arm_LDRSHT_MI: "LDRSHT.MI", | 6636 arm_LDRSHT_MI: "LDRSHT.MI", |
5280 arm_LDRSHT_PL: "LDRSHT.PL", | 6637 arm_LDRSHT_PL: "LDRSHT.PL", |
5281 arm_LDRSHT_VS: "LDRSHT.VS", | 6638 arm_LDRSHT_VS: "LDRSHT.VS", |
5282 arm_LDRSHT_VC: "LDRSHT.VC", | 6639 arm_LDRSHT_VC: "LDRSHT.VC", |
5283 arm_LDRSHT_HI: "LDRSHT.HI", | 6640 arm_LDRSHT_HI: "LDRSHT.HI", |
5284 arm_LDRSHT_LS: "LDRSHT.LS", | 6641 arm_LDRSHT_LS: "LDRSHT.LS", |
5285 arm_LDRSHT_GE: "LDRSHT.GE", | 6642 arm_LDRSHT_GE: "LDRSHT.GE", |
5286 arm_LDRSHT_LT: "LDRSHT.LT", | 6643 arm_LDRSHT_LT: "LDRSHT.LT", |
5287 arm_LDRSHT_GT: "LDRSHT.GT", | 6644 arm_LDRSHT_GT: "LDRSHT.GT", |
5288 arm_LDRSHT_LE: "LDRSHT.LE", | 6645 arm_LDRSHT_LE: "LDRSHT.LE", |
5289 arm_LDRSHT: "LDRSHT", | 6646 arm_LDRSHT: "LDRSHT", |
5290 arm_LDRSHT_ZZ: "LDRSHT.ZZ", | 6647 arm_LDRSHT_ZZ: "LDRSHT.ZZ", |
5291 arm_LDRT_EQ: "LDRT.EQ", | 6648 arm_LDRT_EQ: "LDRT.EQ", |
5292 arm_LDRT_NE: "LDRT.NE", | 6649 arm_LDRT_NE: "LDRT.NE", |
5293 arm_LDRT_CS: "LDRT.CS", | 6650 arm_LDRT_CS: "LDRT.CS", |
5294 arm_LDRT_CC: "LDRT.CC", | 6651 arm_LDRT_CC: "LDRT.CC", |
5295 arm_LDRT_MI: "LDRT.MI", | 6652 arm_LDRT_MI: "LDRT.MI", |
5296 arm_LDRT_PL: "LDRT.PL", | 6653 arm_LDRT_PL: "LDRT.PL", |
5297 arm_LDRT_VS: "LDRT.VS", | 6654 arm_LDRT_VS: "LDRT.VS", |
5298 arm_LDRT_VC: "LDRT.VC", | 6655 arm_LDRT_VC: "LDRT.VC", |
5299 arm_LDRT_HI: "LDRT.HI", | 6656 arm_LDRT_HI: "LDRT.HI", |
5300 arm_LDRT_LS: "LDRT.LS", | 6657 arm_LDRT_LS: "LDRT.LS", |
5301 arm_LDRT_GE: "LDRT.GE", | 6658 arm_LDRT_GE: "LDRT.GE", |
5302 arm_LDRT_LT: "LDRT.LT", | 6659 arm_LDRT_LT: "LDRT.LT", |
5303 arm_LDRT_GT: "LDRT.GT", | 6660 arm_LDRT_GT: "LDRT.GT", |
5304 arm_LDRT_LE: "LDRT.LE", | 6661 arm_LDRT_LE: "LDRT.LE", |
5305 arm_LDRT: "LDRT", | 6662 arm_LDRT: "LDRT", |
5306 arm_LDRT_ZZ: "LDRT.ZZ", | 6663 arm_LDRT_ZZ: "LDRT.ZZ", |
5307 arm_LSL_EQ: "LSL.EQ", | 6664 arm_LSL_EQ: "LSL.EQ", |
5308 arm_LSL_NE: "LSL.NE", | 6665 arm_LSL_NE: "LSL.NE", |
5309 arm_LSL_CS: "LSL.CS", | 6666 arm_LSL_CS: "LSL.CS", |
5310 arm_LSL_CC: "LSL.CC", | 6667 arm_LSL_CC: "LSL.CC", |
5311 arm_LSL_MI: "LSL.MI", | 6668 arm_LSL_MI: "LSL.MI", |
5312 arm_LSL_PL: "LSL.PL", | 6669 arm_LSL_PL: "LSL.PL", |
5313 arm_LSL_VS: "LSL.VS", | 6670 arm_LSL_VS: "LSL.VS", |
5314 arm_LSL_VC: "LSL.VC", | 6671 arm_LSL_VC: "LSL.VC", |
5315 arm_LSL_HI: "LSL.HI", | 6672 arm_LSL_HI: "LSL.HI", |
5316 arm_LSL_LS: "LSL.LS", | 6673 arm_LSL_LS: "LSL.LS", |
5317 arm_LSL_GE: "LSL.GE", | 6674 arm_LSL_GE: "LSL.GE", |
5318 arm_LSL_LT: "LSL.LT", | 6675 arm_LSL_LT: "LSL.LT", |
5319 arm_LSL_GT: "LSL.GT", | 6676 arm_LSL_GT: "LSL.GT", |
5320 arm_LSL_LE: "LSL.LE", | 6677 arm_LSL_LE: "LSL.LE", |
5321 arm_LSL: "LSL", | 6678 arm_LSL: "LSL", |
5322 arm_LSL_ZZ: "LSL.ZZ", | 6679 arm_LSL_ZZ: "LSL.ZZ", |
5323 arm_LSL_S_EQ: "LSL.S.EQ", | 6680 arm_LSL_S_EQ: "LSL.S.EQ", |
5324 arm_LSL_S_NE: "LSL.S.NE", | 6681 arm_LSL_S_NE: "LSL.S.NE", |
5325 arm_LSL_S_CS: "LSL.S.CS", | 6682 arm_LSL_S_CS: "LSL.S.CS", |
5326 arm_LSL_S_CC: "LSL.S.CC", | 6683 arm_LSL_S_CC: "LSL.S.CC", |
5327 arm_LSL_S_MI: "LSL.S.MI", | 6684 arm_LSL_S_MI: "LSL.S.MI", |
5328 arm_LSL_S_PL: "LSL.S.PL", | 6685 arm_LSL_S_PL: "LSL.S.PL", |
5329 arm_LSL_S_VS: "LSL.S.VS", | 6686 arm_LSL_S_VS: "LSL.S.VS", |
5330 arm_LSL_S_VC: "LSL.S.VC", | 6687 arm_LSL_S_VC: "LSL.S.VC", |
5331 arm_LSL_S_HI: "LSL.S.HI", | 6688 arm_LSL_S_HI: "LSL.S.HI", |
5332 arm_LSL_S_LS: "LSL.S.LS", | 6689 arm_LSL_S_LS: "LSL.S.LS", |
5333 arm_LSL_S_GE: "LSL.S.GE", | 6690 arm_LSL_S_GE: "LSL.S.GE", |
5334 arm_LSL_S_LT: "LSL.S.LT", | 6691 arm_LSL_S_LT: "LSL.S.LT", |
5335 arm_LSL_S_GT: "LSL.S.GT", | 6692 arm_LSL_S_GT: "LSL.S.GT", |
5336 arm_LSL_S_LE: "LSL.S.LE", | 6693 arm_LSL_S_LE: "LSL.S.LE", |
5337 arm_LSL_S: "LSL.S", | 6694 arm_LSL_S: "LSL.S", |
5338 arm_LSL_S_ZZ: "LSL.S.ZZ", | 6695 arm_LSL_S_ZZ: "LSL.S.ZZ", |
5339 arm_LSR_EQ: "LSR.EQ", | 6696 arm_LSR_EQ: "LSR.EQ", |
5340 arm_LSR_NE: "LSR.NE", | 6697 arm_LSR_NE: "LSR.NE", |
5341 arm_LSR_CS: "LSR.CS", | 6698 arm_LSR_CS: "LSR.CS", |
5342 arm_LSR_CC: "LSR.CC", | 6699 arm_LSR_CC: "LSR.CC", |
5343 arm_LSR_MI: "LSR.MI", | 6700 arm_LSR_MI: "LSR.MI", |
5344 arm_LSR_PL: "LSR.PL", | 6701 arm_LSR_PL: "LSR.PL", |
5345 arm_LSR_VS: "LSR.VS", | 6702 arm_LSR_VS: "LSR.VS", |
5346 arm_LSR_VC: "LSR.VC", | 6703 arm_LSR_VC: "LSR.VC", |
5347 arm_LSR_HI: "LSR.HI", | 6704 arm_LSR_HI: "LSR.HI", |
5348 arm_LSR_LS: "LSR.LS", | 6705 arm_LSR_LS: "LSR.LS", |
5349 arm_LSR_GE: "LSR.GE", | 6706 arm_LSR_GE: "LSR.GE", |
5350 arm_LSR_LT: "LSR.LT", | 6707 arm_LSR_LT: "LSR.LT", |
5351 arm_LSR_GT: "LSR.GT", | 6708 arm_LSR_GT: "LSR.GT", |
5352 arm_LSR_LE: "LSR.LE", | 6709 arm_LSR_LE: "LSR.LE", |
5353 arm_LSR: "LSR", | 6710 arm_LSR: "LSR", |
5354 arm_LSR_ZZ: "LSR.ZZ", | 6711 arm_LSR_ZZ: "LSR.ZZ", |
5355 arm_LSR_S_EQ: "LSR.S.EQ", | 6712 arm_LSR_S_EQ: "LSR.S.EQ", |
5356 arm_LSR_S_NE: "LSR.S.NE", | 6713 arm_LSR_S_NE: "LSR.S.NE", |
5357 arm_LSR_S_CS: "LSR.S.CS", | 6714 arm_LSR_S_CS: "LSR.S.CS", |
5358 arm_LSR_S_CC: "LSR.S.CC", | 6715 arm_LSR_S_CC: "LSR.S.CC", |
5359 arm_LSR_S_MI: "LSR.S.MI", | 6716 arm_LSR_S_MI: "LSR.S.MI", |
5360 arm_LSR_S_PL: "LSR.S.PL", | 6717 arm_LSR_S_PL: "LSR.S.PL", |
5361 arm_LSR_S_VS: "LSR.S.VS", | 6718 arm_LSR_S_VS: "LSR.S.VS", |
5362 arm_LSR_S_VC: "LSR.S.VC", | 6719 arm_LSR_S_VC: "LSR.S.VC", |
5363 arm_LSR_S_HI: "LSR.S.HI", | 6720 arm_LSR_S_HI: "LSR.S.HI", |
5364 arm_LSR_S_LS: "LSR.S.LS", | 6721 arm_LSR_S_LS: "LSR.S.LS", |
5365 arm_LSR_S_GE: "LSR.S.GE", | 6722 arm_LSR_S_GE: "LSR.S.GE", |
5366 arm_LSR_S_LT: "LSR.S.LT", | 6723 arm_LSR_S_LT: "LSR.S.LT", |
5367 arm_LSR_S_GT: "LSR.S.GT", | 6724 arm_LSR_S_GT: "LSR.S.GT", |
5368 arm_LSR_S_LE: "LSR.S.LE", | 6725 arm_LSR_S_LE: "LSR.S.LE", |
5369 arm_LSR_S: "LSR.S", | 6726 arm_LSR_S: "LSR.S", |
5370 arm_LSR_S_ZZ: "LSR.S.ZZ", | 6727 arm_LSR_S_ZZ: "LSR.S.ZZ", |
5371 arm_MLA_EQ: "MLA.EQ", | 6728 arm_MLA_EQ: "MLA.EQ", |
5372 arm_MLA_NE: "MLA.NE", | 6729 arm_MLA_NE: "MLA.NE", |
5373 arm_MLA_CS: "MLA.CS", | 6730 arm_MLA_CS: "MLA.CS", |
5374 arm_MLA_CC: "MLA.CC", | 6731 arm_MLA_CC: "MLA.CC", |
5375 arm_MLA_MI: "MLA.MI", | 6732 arm_MLA_MI: "MLA.MI", |
5376 arm_MLA_PL: "MLA.PL", | 6733 arm_MLA_PL: "MLA.PL", |
5377 arm_MLA_VS: "MLA.VS", | 6734 arm_MLA_VS: "MLA.VS", |
5378 arm_MLA_VC: "MLA.VC", | 6735 arm_MLA_VC: "MLA.VC", |
5379 arm_MLA_HI: "MLA.HI", | 6736 arm_MLA_HI: "MLA.HI", |
5380 arm_MLA_LS: "MLA.LS", | 6737 arm_MLA_LS: "MLA.LS", |
5381 arm_MLA_GE: "MLA.GE", | 6738 arm_MLA_GE: "MLA.GE", |
5382 arm_MLA_LT: "MLA.LT", | 6739 arm_MLA_LT: "MLA.LT", |
5383 arm_MLA_GT: "MLA.GT", | 6740 arm_MLA_GT: "MLA.GT", |
5384 arm_MLA_LE: "MLA.LE", | 6741 arm_MLA_LE: "MLA.LE", |
5385 arm_MLA: "MLA", | 6742 arm_MLA: "MLA", |
5386 arm_MLA_ZZ: "MLA.ZZ", | 6743 arm_MLA_ZZ: "MLA.ZZ", |
5387 arm_MLA_S_EQ: "MLA.S.EQ", | 6744 arm_MLA_S_EQ: "MLA.S.EQ", |
5388 arm_MLA_S_NE: "MLA.S.NE", | 6745 arm_MLA_S_NE: "MLA.S.NE", |
5389 arm_MLA_S_CS: "MLA.S.CS", | 6746 arm_MLA_S_CS: "MLA.S.CS", |
5390 arm_MLA_S_CC: "MLA.S.CC", | 6747 arm_MLA_S_CC: "MLA.S.CC", |
5391 arm_MLA_S_MI: "MLA.S.MI", | 6748 arm_MLA_S_MI: "MLA.S.MI", |
5392 arm_MLA_S_PL: "MLA.S.PL", | 6749 arm_MLA_S_PL: "MLA.S.PL", |
5393 arm_MLA_S_VS: "MLA.S.VS", | 6750 arm_MLA_S_VS: "MLA.S.VS", |
5394 arm_MLA_S_VC: "MLA.S.VC", | 6751 arm_MLA_S_VC: "MLA.S.VC", |
5395 arm_MLA_S_HI: "MLA.S.HI", | 6752 arm_MLA_S_HI: "MLA.S.HI", |
5396 arm_MLA_S_LS: "MLA.S.LS", | 6753 arm_MLA_S_LS: "MLA.S.LS", |
5397 arm_MLA_S_GE: "MLA.S.GE", | 6754 arm_MLA_S_GE: "MLA.S.GE", |
5398 arm_MLA_S_LT: "MLA.S.LT", | 6755 arm_MLA_S_LT: "MLA.S.LT", |
5399 arm_MLA_S_GT: "MLA.S.GT", | 6756 arm_MLA_S_GT: "MLA.S.GT", |
5400 arm_MLA_S_LE: "MLA.S.LE", | 6757 arm_MLA_S_LE: "MLA.S.LE", |
5401 arm_MLA_S: "MLA.S", | 6758 arm_MLA_S: "MLA.S", |
5402 arm_MLA_S_ZZ: "MLA.S.ZZ", | 6759 arm_MLA_S_ZZ: "MLA.S.ZZ", |
5403 arm_MLS_EQ: "MLS.EQ", | 6760 arm_MLS_EQ: "MLS.EQ", |
5404 arm_MLS_NE: "MLS.NE", | 6761 arm_MLS_NE: "MLS.NE", |
5405 arm_MLS_CS: "MLS.CS", | 6762 arm_MLS_CS: "MLS.CS", |
5406 arm_MLS_CC: "MLS.CC", | 6763 arm_MLS_CC: "MLS.CC", |
5407 arm_MLS_MI: "MLS.MI", | 6764 arm_MLS_MI: "MLS.MI", |
5408 arm_MLS_PL: "MLS.PL", | 6765 arm_MLS_PL: "MLS.PL", |
5409 arm_MLS_VS: "MLS.VS", | 6766 arm_MLS_VS: "MLS.VS", |
5410 arm_MLS_VC: "MLS.VC", | 6767 arm_MLS_VC: "MLS.VC", |
5411 arm_MLS_HI: "MLS.HI", | 6768 arm_MLS_HI: "MLS.HI", |
5412 arm_MLS_LS: "MLS.LS", | 6769 arm_MLS_LS: "MLS.LS", |
5413 arm_MLS_GE: "MLS.GE", | 6770 arm_MLS_GE: "MLS.GE", |
5414 arm_MLS_LT: "MLS.LT", | 6771 arm_MLS_LT: "MLS.LT", |
5415 arm_MLS_GT: "MLS.GT", | 6772 arm_MLS_GT: "MLS.GT", |
5416 arm_MLS_LE: "MLS.LE", | 6773 arm_MLS_LE: "MLS.LE", |
5417 arm_MLS: "MLS", | 6774 arm_MLS: "MLS", |
5418 arm_MLS_ZZ: "MLS.ZZ", | 6775 arm_MLS_ZZ: "MLS.ZZ", |
5419 arm_MOV_EQ: "MOV.EQ", | 6776 arm_MOV_EQ: "MOV.EQ", |
5420 arm_MOV_NE: "MOV.NE", | 6777 arm_MOV_NE: "MOV.NE", |
5421 arm_MOV_CS: "MOV.CS", | 6778 arm_MOV_CS: "MOV.CS", |
5422 arm_MOV_CC: "MOV.CC", | 6779 arm_MOV_CC: "MOV.CC", |
5423 arm_MOV_MI: "MOV.MI", | 6780 arm_MOV_MI: "MOV.MI", |
5424 arm_MOV_PL: "MOV.PL", | 6781 arm_MOV_PL: "MOV.PL", |
5425 arm_MOV_VS: "MOV.VS", | 6782 arm_MOV_VS: "MOV.VS", |
5426 arm_MOV_VC: "MOV.VC", | 6783 arm_MOV_VC: "MOV.VC", |
5427 arm_MOV_HI: "MOV.HI", | 6784 arm_MOV_HI: "MOV.HI", |
5428 arm_MOV_LS: "MOV.LS", | 6785 arm_MOV_LS: "MOV.LS", |
5429 arm_MOV_GE: "MOV.GE", | 6786 arm_MOV_GE: "MOV.GE", |
5430 arm_MOV_LT: "MOV.LT", | 6787 arm_MOV_LT: "MOV.LT", |
5431 arm_MOV_GT: "MOV.GT", | 6788 arm_MOV_GT: "MOV.GT", |
5432 arm_MOV_LE: "MOV.LE", | 6789 arm_MOV_LE: "MOV.LE", |
5433 arm_MOV: "MOV", | 6790 arm_MOV: "MOV", |
5434 arm_MOV_ZZ: "MOV.ZZ", | 6791 arm_MOV_ZZ: "MOV.ZZ", |
5435 arm_MOV_S_EQ: "MOV.S.EQ", | 6792 arm_MOV_S_EQ: "MOV.S.EQ", |
5436 arm_MOV_S_NE: "MOV.S.NE", | 6793 arm_MOV_S_NE: "MOV.S.NE", |
5437 arm_MOV_S_CS: "MOV.S.CS", | 6794 arm_MOV_S_CS: "MOV.S.CS", |
5438 arm_MOV_S_CC: "MOV.S.CC", | 6795 arm_MOV_S_CC: "MOV.S.CC", |
5439 arm_MOV_S_MI: "MOV.S.MI", | 6796 arm_MOV_S_MI: "MOV.S.MI", |
5440 arm_MOV_S_PL: "MOV.S.PL", | 6797 arm_MOV_S_PL: "MOV.S.PL", |
5441 arm_MOV_S_VS: "MOV.S.VS", | 6798 arm_MOV_S_VS: "MOV.S.VS", |
5442 arm_MOV_S_VC: "MOV.S.VC", | 6799 arm_MOV_S_VC: "MOV.S.VC", |
5443 arm_MOV_S_HI: "MOV.S.HI", | 6800 arm_MOV_S_HI: "MOV.S.HI", |
5444 arm_MOV_S_LS: "MOV.S.LS", | 6801 arm_MOV_S_LS: "MOV.S.LS", |
5445 arm_MOV_S_GE: "MOV.S.GE", | 6802 arm_MOV_S_GE: "MOV.S.GE", |
5446 arm_MOV_S_LT: "MOV.S.LT", | 6803 arm_MOV_S_LT: "MOV.S.LT", |
5447 arm_MOV_S_GT: "MOV.S.GT", | 6804 arm_MOV_S_GT: "MOV.S.GT", |
5448 arm_MOV_S_LE: "MOV.S.LE", | 6805 arm_MOV_S_LE: "MOV.S.LE", |
5449 arm_MOV_S: "MOV.S", | 6806 arm_MOV_S: "MOV.S", |
5450 arm_MOV_S_ZZ: "MOV.S.ZZ", | 6807 arm_MOV_S_ZZ: "MOV.S.ZZ", |
5451 arm_MOVT_EQ: "MOVT.EQ", | 6808 arm_MOVT_EQ: "MOVT.EQ", |
5452 arm_MOVT_NE: "MOVT.NE", | 6809 arm_MOVT_NE: "MOVT.NE", |
5453 arm_MOVT_CS: "MOVT.CS", | 6810 arm_MOVT_CS: "MOVT.CS", |
5454 arm_MOVT_CC: "MOVT.CC", | 6811 arm_MOVT_CC: "MOVT.CC", |
5455 arm_MOVT_MI: "MOVT.MI", | 6812 arm_MOVT_MI: "MOVT.MI", |
5456 arm_MOVT_PL: "MOVT.PL", | 6813 arm_MOVT_PL: "MOVT.PL", |
5457 arm_MOVT_VS: "MOVT.VS", | 6814 arm_MOVT_VS: "MOVT.VS", |
5458 arm_MOVT_VC: "MOVT.VC", | 6815 arm_MOVT_VC: "MOVT.VC", |
5459 arm_MOVT_HI: "MOVT.HI", | 6816 arm_MOVT_HI: "MOVT.HI", |
5460 arm_MOVT_LS: "MOVT.LS", | 6817 arm_MOVT_LS: "MOVT.LS", |
5461 arm_MOVT_GE: "MOVT.GE", | 6818 arm_MOVT_GE: "MOVT.GE", |
5462 arm_MOVT_LT: "MOVT.LT", | 6819 arm_MOVT_LT: "MOVT.LT", |
5463 arm_MOVT_GT: "MOVT.GT", | 6820 arm_MOVT_GT: "MOVT.GT", |
5464 arm_MOVT_LE: "MOVT.LE", | 6821 arm_MOVT_LE: "MOVT.LE", |
5465 arm_MOVT: "MOVT", | 6822 arm_MOVT: "MOVT", |
5466 arm_MOVT_ZZ: "MOVT.ZZ", | 6823 arm_MOVT_ZZ: "MOVT.ZZ", |
5467 arm_MOVW_EQ: "MOVW.EQ", | 6824 arm_MOVW_EQ: "MOVW.EQ", |
5468 arm_MOVW_NE: "MOVW.NE", | 6825 arm_MOVW_NE: "MOVW.NE", |
5469 arm_MOVW_CS: "MOVW.CS", | 6826 arm_MOVW_CS: "MOVW.CS", |
5470 arm_MOVW_CC: "MOVW.CC", | 6827 arm_MOVW_CC: "MOVW.CC", |
5471 arm_MOVW_MI: "MOVW.MI", | 6828 arm_MOVW_MI: "MOVW.MI", |
5472 arm_MOVW_PL: "MOVW.PL", | 6829 arm_MOVW_PL: "MOVW.PL", |
5473 arm_MOVW_VS: "MOVW.VS", | 6830 arm_MOVW_VS: "MOVW.VS", |
5474 arm_MOVW_VC: "MOVW.VC", | 6831 arm_MOVW_VC: "MOVW.VC", |
5475 arm_MOVW_HI: "MOVW.HI", | 6832 arm_MOVW_HI: "MOVW.HI", |
5476 arm_MOVW_LS: "MOVW.LS", | 6833 arm_MOVW_LS: "MOVW.LS", |
5477 arm_MOVW_GE: "MOVW.GE", | 6834 arm_MOVW_GE: "MOVW.GE", |
5478 arm_MOVW_LT: "MOVW.LT", | 6835 arm_MOVW_LT: "MOVW.LT", |
5479 arm_MOVW_GT: "MOVW.GT", | 6836 arm_MOVW_GT: "MOVW.GT", |
5480 arm_MOVW_LE: "MOVW.LE", | 6837 arm_MOVW_LE: "MOVW.LE", |
5481 arm_MOVW: "MOVW", | 6838 arm_MOVW: "MOVW", |
5482 arm_MOVW_ZZ: "MOVW.ZZ", | 6839 arm_MOVW_ZZ: "MOVW.ZZ", |
5483 arm_MRS_EQ: "MRS.EQ", | 6840 arm_MRS_EQ: "MRS.EQ", |
5484 arm_MRS_NE: "MRS.NE", | 6841 arm_MRS_NE: "MRS.NE", |
5485 arm_MRS_CS: "MRS.CS", | 6842 arm_MRS_CS: "MRS.CS", |
5486 arm_MRS_CC: "MRS.CC", | 6843 arm_MRS_CC: "MRS.CC", |
5487 arm_MRS_MI: "MRS.MI", | 6844 arm_MRS_MI: "MRS.MI", |
5488 arm_MRS_PL: "MRS.PL", | 6845 arm_MRS_PL: "MRS.PL", |
5489 arm_MRS_VS: "MRS.VS", | 6846 arm_MRS_VS: "MRS.VS", |
5490 arm_MRS_VC: "MRS.VC", | 6847 arm_MRS_VC: "MRS.VC", |
5491 arm_MRS_HI: "MRS.HI", | 6848 arm_MRS_HI: "MRS.HI", |
5492 arm_MRS_LS: "MRS.LS", | 6849 arm_MRS_LS: "MRS.LS", |
5493 arm_MRS_GE: "MRS.GE", | 6850 arm_MRS_GE: "MRS.GE", |
5494 arm_MRS_LT: "MRS.LT", | 6851 arm_MRS_LT: "MRS.LT", |
5495 arm_MRS_GT: "MRS.GT", | 6852 arm_MRS_GT: "MRS.GT", |
5496 arm_MRS_LE: "MRS.LE", | 6853 arm_MRS_LE: "MRS.LE", |
5497 arm_MRS: "MRS", | 6854 arm_MRS: "MRS", |
5498 arm_MRS_ZZ: "MRS.ZZ", | 6855 arm_MRS_ZZ: "MRS.ZZ", |
5499 arm_MUL_EQ: "MUL.EQ", | 6856 arm_MUL_EQ: "MUL.EQ", |
5500 arm_MUL_NE: "MUL.NE", | 6857 arm_MUL_NE: "MUL.NE", |
5501 arm_MUL_CS: "MUL.CS", | 6858 arm_MUL_CS: "MUL.CS", |
5502 arm_MUL_CC: "MUL.CC", | 6859 arm_MUL_CC: "MUL.CC", |
5503 arm_MUL_MI: "MUL.MI", | 6860 arm_MUL_MI: "MUL.MI", |
5504 arm_MUL_PL: "MUL.PL", | 6861 arm_MUL_PL: "MUL.PL", |
5505 arm_MUL_VS: "MUL.VS", | 6862 arm_MUL_VS: "MUL.VS", |
5506 arm_MUL_VC: "MUL.VC", | 6863 arm_MUL_VC: "MUL.VC", |
5507 arm_MUL_HI: "MUL.HI", | 6864 arm_MUL_HI: "MUL.HI", |
5508 arm_MUL_LS: "MUL.LS", | 6865 arm_MUL_LS: "MUL.LS", |
5509 arm_MUL_GE: "MUL.GE", | 6866 arm_MUL_GE: "MUL.GE", |
5510 arm_MUL_LT: "MUL.LT", | 6867 arm_MUL_LT: "MUL.LT", |
5511 arm_MUL_GT: "MUL.GT", | 6868 arm_MUL_GT: "MUL.GT", |
5512 arm_MUL_LE: "MUL.LE", | 6869 arm_MUL_LE: "MUL.LE", |
5513 arm_MUL: "MUL", | 6870 arm_MUL: "MUL", |
5514 arm_MUL_ZZ: "MUL.ZZ", | 6871 arm_MUL_ZZ: "MUL.ZZ", |
5515 arm_MUL_S_EQ: "MUL.S.EQ", | 6872 arm_MUL_S_EQ: "MUL.S.EQ", |
5516 arm_MUL_S_NE: "MUL.S.NE", | 6873 arm_MUL_S_NE: "MUL.S.NE", |
5517 arm_MUL_S_CS: "MUL.S.CS", | 6874 arm_MUL_S_CS: "MUL.S.CS", |
5518 arm_MUL_S_CC: "MUL.S.CC", | 6875 arm_MUL_S_CC: "MUL.S.CC", |
5519 arm_MUL_S_MI: "MUL.S.MI", | 6876 arm_MUL_S_MI: "MUL.S.MI", |
5520 arm_MUL_S_PL: "MUL.S.PL", | 6877 arm_MUL_S_PL: "MUL.S.PL", |
5521 arm_MUL_S_VS: "MUL.S.VS", | 6878 arm_MUL_S_VS: "MUL.S.VS", |
5522 arm_MUL_S_VC: "MUL.S.VC", | 6879 arm_MUL_S_VC: "MUL.S.VC", |
5523 arm_MUL_S_HI: "MUL.S.HI", | 6880 arm_MUL_S_HI: "MUL.S.HI", |
5524 arm_MUL_S_LS: "MUL.S.LS", | 6881 arm_MUL_S_LS: "MUL.S.LS", |
5525 arm_MUL_S_GE: "MUL.S.GE", | 6882 arm_MUL_S_GE: "MUL.S.GE", |
5526 arm_MUL_S_LT: "MUL.S.LT", | 6883 arm_MUL_S_LT: "MUL.S.LT", |
5527 arm_MUL_S_GT: "MUL.S.GT", | 6884 arm_MUL_S_GT: "MUL.S.GT", |
5528 arm_MUL_S_LE: "MUL.S.LE", | 6885 arm_MUL_S_LE: "MUL.S.LE", |
5529 arm_MUL_S: "MUL.S", | 6886 arm_MUL_S: "MUL.S", |
5530 arm_MUL_S_ZZ: "MUL.S.ZZ", | 6887 arm_MUL_S_ZZ: "MUL.S.ZZ", |
5531 arm_MVN_EQ: "MVN.EQ", | 6888 arm_MVN_EQ: "MVN.EQ", |
5532 arm_MVN_NE: "MVN.NE", | 6889 arm_MVN_NE: "MVN.NE", |
5533 arm_MVN_CS: "MVN.CS", | 6890 arm_MVN_CS: "MVN.CS", |
5534 arm_MVN_CC: "MVN.CC", | 6891 arm_MVN_CC: "MVN.CC", |
5535 arm_MVN_MI: "MVN.MI", | 6892 arm_MVN_MI: "MVN.MI", |
5536 arm_MVN_PL: "MVN.PL", | 6893 arm_MVN_PL: "MVN.PL", |
5537 arm_MVN_VS: "MVN.VS", | 6894 arm_MVN_VS: "MVN.VS", |
5538 arm_MVN_VC: "MVN.VC", | 6895 arm_MVN_VC: "MVN.VC", |
5539 arm_MVN_HI: "MVN.HI", | 6896 arm_MVN_HI: "MVN.HI", |
5540 arm_MVN_LS: "MVN.LS", | 6897 arm_MVN_LS: "MVN.LS", |
5541 arm_MVN_GE: "MVN.GE", | 6898 arm_MVN_GE: "MVN.GE", |
5542 arm_MVN_LT: "MVN.LT", | 6899 arm_MVN_LT: "MVN.LT", |
5543 arm_MVN_GT: "MVN.GT", | 6900 arm_MVN_GT: "MVN.GT", |
5544 arm_MVN_LE: "MVN.LE", | 6901 arm_MVN_LE: "MVN.LE", |
5545 arm_MVN: "MVN", | 6902 arm_MVN: "MVN", |
5546 arm_MVN_ZZ: "MVN.ZZ", | 6903 arm_MVN_ZZ: "MVN.ZZ", |
5547 arm_MVN_S_EQ: "MVN.S.EQ", | 6904 arm_MVN_S_EQ: "MVN.S.EQ", |
5548 arm_MVN_S_NE: "MVN.S.NE", | 6905 arm_MVN_S_NE: "MVN.S.NE", |
5549 arm_MVN_S_CS: "MVN.S.CS", | 6906 arm_MVN_S_CS: "MVN.S.CS", |
5550 arm_MVN_S_CC: "MVN.S.CC", | 6907 arm_MVN_S_CC: "MVN.S.CC", |
5551 arm_MVN_S_MI: "MVN.S.MI", | 6908 arm_MVN_S_MI: "MVN.S.MI", |
5552 arm_MVN_S_PL: "MVN.S.PL", | 6909 arm_MVN_S_PL: "MVN.S.PL", |
5553 arm_MVN_S_VS: "MVN.S.VS", | 6910 arm_MVN_S_VS: "MVN.S.VS", |
5554 arm_MVN_S_VC: "MVN.S.VC", | 6911 arm_MVN_S_VC: "MVN.S.VC", |
5555 arm_MVN_S_HI: "MVN.S.HI", | 6912 arm_MVN_S_HI: "MVN.S.HI", |
5556 arm_MVN_S_LS: "MVN.S.LS", | 6913 arm_MVN_S_LS: "MVN.S.LS", |
5557 arm_MVN_S_GE: "MVN.S.GE", | 6914 arm_MVN_S_GE: "MVN.S.GE", |
5558 arm_MVN_S_LT: "MVN.S.LT", | 6915 arm_MVN_S_LT: "MVN.S.LT", |
5559 arm_MVN_S_GT: "MVN.S.GT", | 6916 arm_MVN_S_GT: "MVN.S.GT", |
5560 arm_MVN_S_LE: "MVN.S.LE", | 6917 arm_MVN_S_LE: "MVN.S.LE", |
5561 arm_MVN_S: "MVN.S", | 6918 arm_MVN_S: "MVN.S", |
5562 arm_MVN_S_ZZ: "MVN.S.ZZ", | 6919 arm_MVN_S_ZZ: "MVN.S.ZZ", |
5563 arm_NOP_EQ: "NOP.EQ", | 6920 arm_NOP_EQ: "NOP.EQ", |
5564 arm_NOP_NE: "NOP.NE", | 6921 arm_NOP_NE: "NOP.NE", |
5565 arm_NOP_CS: "NOP.CS", | 6922 arm_NOP_CS: "NOP.CS", |
5566 arm_NOP_CC: "NOP.CC", | 6923 arm_NOP_CC: "NOP.CC", |
5567 arm_NOP_MI: "NOP.MI", | 6924 arm_NOP_MI: "NOP.MI", |
5568 arm_NOP_PL: "NOP.PL", | 6925 arm_NOP_PL: "NOP.PL", |
5569 arm_NOP_VS: "NOP.VS", | 6926 arm_NOP_VS: "NOP.VS", |
5570 arm_NOP_VC: "NOP.VC", | 6927 arm_NOP_VC: "NOP.VC", |
5571 arm_NOP_HI: "NOP.HI", | 6928 arm_NOP_HI: "NOP.HI", |
5572 arm_NOP_LS: "NOP.LS", | 6929 arm_NOP_LS: "NOP.LS", |
5573 arm_NOP_GE: "NOP.GE", | 6930 arm_NOP_GE: "NOP.GE", |
5574 arm_NOP_LT: "NOP.LT", | 6931 arm_NOP_LT: "NOP.LT", |
5575 arm_NOP_GT: "NOP.GT", | 6932 arm_NOP_GT: "NOP.GT", |
5576 arm_NOP_LE: "NOP.LE", | 6933 arm_NOP_LE: "NOP.LE", |
5577 arm_NOP: "NOP", | 6934 arm_NOP: "NOP", |
5578 arm_NOP_ZZ: "NOP.ZZ", | 6935 arm_NOP_ZZ: "NOP.ZZ", |
5579 arm_ORR_EQ: "ORR.EQ", | 6936 arm_ORR_EQ: "ORR.EQ", |
5580 arm_ORR_NE: "ORR.NE", | 6937 arm_ORR_NE: "ORR.NE", |
5581 arm_ORR_CS: "ORR.CS", | 6938 arm_ORR_CS: "ORR.CS", |
5582 arm_ORR_CC: "ORR.CC", | 6939 arm_ORR_CC: "ORR.CC", |
5583 arm_ORR_MI: "ORR.MI", | 6940 arm_ORR_MI: "ORR.MI", |
5584 arm_ORR_PL: "ORR.PL", | 6941 arm_ORR_PL: "ORR.PL", |
5585 arm_ORR_VS: "ORR.VS", | 6942 arm_ORR_VS: "ORR.VS", |
5586 arm_ORR_VC: "ORR.VC", | 6943 arm_ORR_VC: "ORR.VC", |
5587 arm_ORR_HI: "ORR.HI", | 6944 arm_ORR_HI: "ORR.HI", |
5588 arm_ORR_LS: "ORR.LS", | 6945 arm_ORR_LS: "ORR.LS", |
5589 arm_ORR_GE: "ORR.GE", | 6946 arm_ORR_GE: "ORR.GE", |
5590 arm_ORR_LT: "ORR.LT", | 6947 arm_ORR_LT: "ORR.LT", |
5591 arm_ORR_GT: "ORR.GT", | 6948 arm_ORR_GT: "ORR.GT", |
5592 arm_ORR_LE: "ORR.LE", | 6949 arm_ORR_LE: "ORR.LE", |
5593 arm_ORR: "ORR", | 6950 arm_ORR: "ORR", |
5594 arm_ORR_ZZ: "ORR.ZZ", | 6951 arm_ORR_ZZ: "ORR.ZZ", |
5595 arm_ORR_S_EQ: "ORR.S.EQ", | 6952 arm_ORR_S_EQ: "ORR.S.EQ", |
5596 arm_ORR_S_NE: "ORR.S.NE", | 6953 arm_ORR_S_NE: "ORR.S.NE", |
5597 arm_ORR_S_CS: "ORR.S.CS", | 6954 arm_ORR_S_CS: "ORR.S.CS", |
5598 arm_ORR_S_CC: "ORR.S.CC", | 6955 arm_ORR_S_CC: "ORR.S.CC", |
5599 arm_ORR_S_MI: "ORR.S.MI", | 6956 arm_ORR_S_MI: "ORR.S.MI", |
5600 arm_ORR_S_PL: "ORR.S.PL", | 6957 arm_ORR_S_PL: "ORR.S.PL", |
5601 arm_ORR_S_VS: "ORR.S.VS", | 6958 arm_ORR_S_VS: "ORR.S.VS", |
5602 arm_ORR_S_VC: "ORR.S.VC", | 6959 arm_ORR_S_VC: "ORR.S.VC", |
5603 arm_ORR_S_HI: "ORR.S.HI", | 6960 arm_ORR_S_HI: "ORR.S.HI", |
5604 arm_ORR_S_LS: "ORR.S.LS", | 6961 arm_ORR_S_LS: "ORR.S.LS", |
5605 arm_ORR_S_GE: "ORR.S.GE", | 6962 arm_ORR_S_GE: "ORR.S.GE", |
5606 arm_ORR_S_LT: "ORR.S.LT", | 6963 arm_ORR_S_LT: "ORR.S.LT", |
5607 arm_ORR_S_GT: "ORR.S.GT", | 6964 arm_ORR_S_GT: "ORR.S.GT", |
5608 arm_ORR_S_LE: "ORR.S.LE", | 6965 arm_ORR_S_LE: "ORR.S.LE", |
5609 arm_ORR_S: "ORR.S", | 6966 arm_ORR_S: "ORR.S", |
5610 arm_ORR_S_ZZ: "ORR.S.ZZ", | 6967 arm_ORR_S_ZZ: "ORR.S.ZZ", |
5611 arm_PKHBT_EQ: "PKHBT.EQ", | 6968 arm_PKHBT_EQ: "PKHBT.EQ", |
5612 arm_PKHBT_NE: "PKHBT.NE", | 6969 arm_PKHBT_NE: "PKHBT.NE", |
5613 arm_PKHBT_CS: "PKHBT.CS", | 6970 arm_PKHBT_CS: "PKHBT.CS", |
5614 arm_PKHBT_CC: "PKHBT.CC", | 6971 arm_PKHBT_CC: "PKHBT.CC", |
5615 arm_PKHBT_MI: "PKHBT.MI", | 6972 arm_PKHBT_MI: "PKHBT.MI", |
5616 arm_PKHBT_PL: "PKHBT.PL", | 6973 arm_PKHBT_PL: "PKHBT.PL", |
5617 arm_PKHBT_VS: "PKHBT.VS", | 6974 arm_PKHBT_VS: "PKHBT.VS", |
5618 arm_PKHBT_VC: "PKHBT.VC", | 6975 arm_PKHBT_VC: "PKHBT.VC", |
5619 arm_PKHBT_HI: "PKHBT.HI", | 6976 arm_PKHBT_HI: "PKHBT.HI", |
5620 arm_PKHBT_LS: "PKHBT.LS", | 6977 arm_PKHBT_LS: "PKHBT.LS", |
5621 arm_PKHBT_GE: "PKHBT.GE", | 6978 arm_PKHBT_GE: "PKHBT.GE", |
5622 arm_PKHBT_LT: "PKHBT.LT", | 6979 arm_PKHBT_LT: "PKHBT.LT", |
5623 arm_PKHBT_GT: "PKHBT.GT", | 6980 arm_PKHBT_GT: "PKHBT.GT", |
5624 arm_PKHBT_LE: "PKHBT.LE", | 6981 arm_PKHBT_LE: "PKHBT.LE", |
5625 arm_PKHBT: "PKHBT", | 6982 arm_PKHBT: "PKHBT", |
5626 arm_PKHBT_ZZ: "PKHBT.ZZ", | 6983 arm_PKHBT_ZZ: "PKHBT.ZZ", |
5627 arm_PKHTB_EQ: "PKHTB.EQ", | 6984 arm_PKHTB_EQ: "PKHTB.EQ", |
5628 arm_PKHTB_NE: "PKHTB.NE", | 6985 arm_PKHTB_NE: "PKHTB.NE", |
5629 arm_PKHTB_CS: "PKHTB.CS", | 6986 arm_PKHTB_CS: "PKHTB.CS", |
5630 arm_PKHTB_CC: "PKHTB.CC", | 6987 arm_PKHTB_CC: "PKHTB.CC", |
5631 arm_PKHTB_MI: "PKHTB.MI", | 6988 arm_PKHTB_MI: "PKHTB.MI", |
5632 arm_PKHTB_PL: "PKHTB.PL", | 6989 arm_PKHTB_PL: "PKHTB.PL", |
5633 arm_PKHTB_VS: "PKHTB.VS", | 6990 arm_PKHTB_VS: "PKHTB.VS", |
5634 arm_PKHTB_VC: "PKHTB.VC", | 6991 arm_PKHTB_VC: "PKHTB.VC", |
5635 arm_PKHTB_HI: "PKHTB.HI", | 6992 arm_PKHTB_HI: "PKHTB.HI", |
5636 arm_PKHTB_LS: "PKHTB.LS", | 6993 arm_PKHTB_LS: "PKHTB.LS", |
5637 arm_PKHTB_GE: "PKHTB.GE", | 6994 arm_PKHTB_GE: "PKHTB.GE", |
5638 arm_PKHTB_LT: "PKHTB.LT", | 6995 arm_PKHTB_LT: "PKHTB.LT", |
5639 arm_PKHTB_GT: "PKHTB.GT", | 6996 arm_PKHTB_GT: "PKHTB.GT", |
5640 arm_PKHTB_LE: "PKHTB.LE", | 6997 arm_PKHTB_LE: "PKHTB.LE", |
5641 arm_PKHTB: "PKHTB", | 6998 arm_PKHTB: "PKHTB", |
5642 arm_PKHTB_ZZ: "PKHTB.ZZ", | 6999 arm_PKHTB_ZZ: "PKHTB.ZZ", |
5643 arm_PLD_W: "PLD.W", | 7000 arm_PLD_W: "PLD.W", |
5644 arm_PLD: "PLD", | 7001 arm_PLD: "PLD", |
5645 arm_PLI: "PLI", | 7002 arm_PLI: "PLI", |
5646 arm_POP_EQ: "POP.EQ", | 7003 arm_POP_EQ: "POP.EQ", |
5647 arm_POP_NE: "POP.NE", | 7004 arm_POP_NE: "POP.NE", |
5648 arm_POP_CS: "POP.CS", | 7005 arm_POP_CS: "POP.CS", |
5649 arm_POP_CC: "POP.CC", | 7006 arm_POP_CC: "POP.CC", |
5650 arm_POP_MI: "POP.MI", | 7007 arm_POP_MI: "POP.MI", |
5651 arm_POP_PL: "POP.PL", | 7008 arm_POP_PL: "POP.PL", |
5652 arm_POP_VS: "POP.VS", | 7009 arm_POP_VS: "POP.VS", |
5653 arm_POP_VC: "POP.VC", | 7010 arm_POP_VC: "POP.VC", |
5654 arm_POP_HI: "POP.HI", | 7011 arm_POP_HI: "POP.HI", |
5655 arm_POP_LS: "POP.LS", | 7012 arm_POP_LS: "POP.LS", |
5656 arm_POP_GE: "POP.GE", | 7013 arm_POP_GE: "POP.GE", |
5657 arm_POP_LT: "POP.LT", | 7014 arm_POP_LT: "POP.LT", |
5658 arm_POP_GT: "POP.GT", | 7015 arm_POP_GT: "POP.GT", |
5659 arm_POP_LE: "POP.LE", | 7016 arm_POP_LE: "POP.LE", |
5660 arm_POP: "POP", | 7017 arm_POP: "POP", |
5661 arm_POP_ZZ: "POP.ZZ", | 7018 arm_POP_ZZ: "POP.ZZ", |
5662 arm_PUSH_EQ: "PUSH.EQ", | 7019 arm_PUSH_EQ: "PUSH.EQ", |
5663 arm_PUSH_NE: "PUSH.NE", | 7020 arm_PUSH_NE: "PUSH.NE", |
5664 arm_PUSH_CS: "PUSH.CS", | 7021 arm_PUSH_CS: "PUSH.CS", |
5665 arm_PUSH_CC: "PUSH.CC", | 7022 arm_PUSH_CC: "PUSH.CC", |
5666 arm_PUSH_MI: "PUSH.MI", | 7023 arm_PUSH_MI: "PUSH.MI", |
5667 arm_PUSH_PL: "PUSH.PL", | 7024 arm_PUSH_PL: "PUSH.PL", |
5668 arm_PUSH_VS: "PUSH.VS", | 7025 arm_PUSH_VS: "PUSH.VS", |
5669 arm_PUSH_VC: "PUSH.VC", | 7026 arm_PUSH_VC: "PUSH.VC", |
5670 arm_PUSH_HI: "PUSH.HI", | 7027 arm_PUSH_HI: "PUSH.HI", |
5671 arm_PUSH_LS: "PUSH.LS", | 7028 arm_PUSH_LS: "PUSH.LS", |
5672 arm_PUSH_GE: "PUSH.GE", | 7029 arm_PUSH_GE: "PUSH.GE", |
5673 arm_PUSH_LT: "PUSH.LT", | 7030 arm_PUSH_LT: "PUSH.LT", |
5674 arm_PUSH_GT: "PUSH.GT", | 7031 arm_PUSH_GT: "PUSH.GT", |
5675 arm_PUSH_LE: "PUSH.LE", | 7032 arm_PUSH_LE: "PUSH.LE", |
5676 arm_PUSH: "PUSH", | 7033 arm_PUSH: "PUSH", |
5677 arm_PUSH_ZZ: "PUSH.ZZ", | 7034 arm_PUSH_ZZ: "PUSH.ZZ", |
5678 arm_QADD_EQ: "QADD.EQ", | 7035 arm_QADD_EQ: "QADD.EQ", |
5679 arm_QADD_NE: "QADD.NE", | 7036 arm_QADD_NE: "QADD.NE", |
5680 arm_QADD_CS: "QADD.CS", | 7037 arm_QADD_CS: "QADD.CS", |
5681 arm_QADD_CC: "QADD.CC", | 7038 arm_QADD_CC: "QADD.CC", |
5682 arm_QADD_MI: "QADD.MI", | 7039 arm_QADD_MI: "QADD.MI", |
5683 arm_QADD_PL: "QADD.PL", | 7040 arm_QADD_PL: "QADD.PL", |
5684 arm_QADD_VS: "QADD.VS", | 7041 arm_QADD_VS: "QADD.VS", |
5685 arm_QADD_VC: "QADD.VC", | 7042 arm_QADD_VC: "QADD.VC", |
5686 arm_QADD_HI: "QADD.HI", | 7043 arm_QADD_HI: "QADD.HI", |
5687 arm_QADD_LS: "QADD.LS", | 7044 arm_QADD_LS: "QADD.LS", |
5688 arm_QADD_GE: "QADD.GE", | 7045 arm_QADD_GE: "QADD.GE", |
5689 arm_QADD_LT: "QADD.LT", | 7046 arm_QADD_LT: "QADD.LT", |
5690 arm_QADD_GT: "QADD.GT", | 7047 arm_QADD_GT: "QADD.GT", |
5691 arm_QADD_LE: "QADD.LE", | 7048 arm_QADD_LE: "QADD.LE", |
5692 arm_QADD: "QADD", | 7049 arm_QADD: "QADD", |
5693 arm_QADD_ZZ: "QADD.ZZ", | 7050 arm_QADD_ZZ: "QADD.ZZ", |
5694 arm_QADD16_EQ: "QADD16.EQ", | 7051 arm_QADD16_EQ: "QADD16.EQ", |
5695 arm_QADD16_NE: "QADD16.NE", | 7052 arm_QADD16_NE: "QADD16.NE", |
5696 arm_QADD16_CS: "QADD16.CS", | 7053 arm_QADD16_CS: "QADD16.CS", |
5697 arm_QADD16_CC: "QADD16.CC", | 7054 arm_QADD16_CC: "QADD16.CC", |
5698 arm_QADD16_MI: "QADD16.MI", | 7055 arm_QADD16_MI: "QADD16.MI", |
5699 arm_QADD16_PL: "QADD16.PL", | 7056 arm_QADD16_PL: "QADD16.PL", |
5700 arm_QADD16_VS: "QADD16.VS", | 7057 arm_QADD16_VS: "QADD16.VS", |
5701 arm_QADD16_VC: "QADD16.VC", | 7058 arm_QADD16_VC: "QADD16.VC", |
5702 arm_QADD16_HI: "QADD16.HI", | 7059 arm_QADD16_HI: "QADD16.HI", |
5703 arm_QADD16_LS: "QADD16.LS", | 7060 arm_QADD16_LS: "QADD16.LS", |
5704 arm_QADD16_GE: "QADD16.GE", | 7061 arm_QADD16_GE: "QADD16.GE", |
5705 arm_QADD16_LT: "QADD16.LT", | 7062 arm_QADD16_LT: "QADD16.LT", |
5706 arm_QADD16_GT: "QADD16.GT", | 7063 arm_QADD16_GT: "QADD16.GT", |
5707 arm_QADD16_LE: "QADD16.LE", | 7064 arm_QADD16_LE: "QADD16.LE", |
5708 arm_QADD16: "QADD16", | 7065 arm_QADD16: "QADD16", |
5709 arm_QADD16_ZZ: "QADD16.ZZ", | 7066 arm_QADD16_ZZ: "QADD16.ZZ", |
5710 arm_QADD8_EQ: "QADD8.EQ", | 7067 arm_QADD8_EQ: "QADD8.EQ", |
5711 arm_QADD8_NE: "QADD8.NE", | 7068 arm_QADD8_NE: "QADD8.NE", |
5712 arm_QADD8_CS: "QADD8.CS", | 7069 arm_QADD8_CS: "QADD8.CS", |
5713 arm_QADD8_CC: "QADD8.CC", | 7070 arm_QADD8_CC: "QADD8.CC", |
5714 arm_QADD8_MI: "QADD8.MI", | 7071 arm_QADD8_MI: "QADD8.MI", |
5715 arm_QADD8_PL: "QADD8.PL", | 7072 arm_QADD8_PL: "QADD8.PL", |
5716 arm_QADD8_VS: "QADD8.VS", | 7073 arm_QADD8_VS: "QADD8.VS", |
5717 arm_QADD8_VC: "QADD8.VC", | 7074 arm_QADD8_VC: "QADD8.VC", |
5718 arm_QADD8_HI: "QADD8.HI", | 7075 arm_QADD8_HI: "QADD8.HI", |
5719 arm_QADD8_LS: "QADD8.LS", | 7076 arm_QADD8_LS: "QADD8.LS", |
5720 arm_QADD8_GE: "QADD8.GE", | 7077 arm_QADD8_GE: "QADD8.GE", |
5721 arm_QADD8_LT: "QADD8.LT", | 7078 arm_QADD8_LT: "QADD8.LT", |
5722 arm_QADD8_GT: "QADD8.GT", | 7079 arm_QADD8_GT: "QADD8.GT", |
5723 arm_QADD8_LE: "QADD8.LE", | 7080 arm_QADD8_LE: "QADD8.LE", |
5724 arm_QADD8: "QADD8", | 7081 arm_QADD8: "QADD8", |
5725 arm_QADD8_ZZ: "QADD8.ZZ", | 7082 arm_QADD8_ZZ: "QADD8.ZZ", |
5726 arm_QASX_EQ: "QASX.EQ", | 7083 arm_QASX_EQ: "QASX.EQ", |
5727 arm_QASX_NE: "QASX.NE", | 7084 arm_QASX_NE: "QASX.NE", |
5728 arm_QASX_CS: "QASX.CS", | 7085 arm_QASX_CS: "QASX.CS", |
5729 arm_QASX_CC: "QASX.CC", | 7086 arm_QASX_CC: "QASX.CC", |
5730 arm_QASX_MI: "QASX.MI", | 7087 arm_QASX_MI: "QASX.MI", |
5731 arm_QASX_PL: "QASX.PL", | 7088 arm_QASX_PL: "QASX.PL", |
5732 arm_QASX_VS: "QASX.VS", | 7089 arm_QASX_VS: "QASX.VS", |
5733 arm_QASX_VC: "QASX.VC", | 7090 arm_QASX_VC: "QASX.VC", |
5734 arm_QASX_HI: "QASX.HI", | 7091 arm_QASX_HI: "QASX.HI", |
5735 arm_QASX_LS: "QASX.LS", | 7092 arm_QASX_LS: "QASX.LS", |
5736 arm_QASX_GE: "QASX.GE", | 7093 arm_QASX_GE: "QASX.GE", |
5737 arm_QASX_LT: "QASX.LT", | 7094 arm_QASX_LT: "QASX.LT", |
5738 arm_QASX_GT: "QASX.GT", | 7095 arm_QASX_GT: "QASX.GT", |
5739 arm_QASX_LE: "QASX.LE", | 7096 arm_QASX_LE: "QASX.LE", |
5740 arm_QASX: "QASX", | 7097 arm_QASX: "QASX", |
5741 arm_QASX_ZZ: "QASX.ZZ", | 7098 arm_QASX_ZZ: "QASX.ZZ", |
5742 arm_QDADD_EQ: "QDADD.EQ", | 7099 arm_QDADD_EQ: "QDADD.EQ", |
5743 arm_QDADD_NE: "QDADD.NE", | 7100 arm_QDADD_NE: "QDADD.NE", |
5744 arm_QDADD_CS: "QDADD.CS", | 7101 arm_QDADD_CS: "QDADD.CS", |
5745 arm_QDADD_CC: "QDADD.CC", | 7102 arm_QDADD_CC: "QDADD.CC", |
5746 arm_QDADD_MI: "QDADD.MI", | 7103 arm_QDADD_MI: "QDADD.MI", |
5747 arm_QDADD_PL: "QDADD.PL", | 7104 arm_QDADD_PL: "QDADD.PL", |
5748 arm_QDADD_VS: "QDADD.VS", | 7105 arm_QDADD_VS: "QDADD.VS", |
5749 arm_QDADD_VC: "QDADD.VC", | 7106 arm_QDADD_VC: "QDADD.VC", |
5750 arm_QDADD_HI: "QDADD.HI", | 7107 arm_QDADD_HI: "QDADD.HI", |
5751 arm_QDADD_LS: "QDADD.LS", | 7108 arm_QDADD_LS: "QDADD.LS", |
5752 arm_QDADD_GE: "QDADD.GE", | 7109 arm_QDADD_GE: "QDADD.GE", |
5753 arm_QDADD_LT: "QDADD.LT", | 7110 arm_QDADD_LT: "QDADD.LT", |
5754 arm_QDADD_GT: "QDADD.GT", | 7111 arm_QDADD_GT: "QDADD.GT", |
5755 arm_QDADD_LE: "QDADD.LE", | 7112 arm_QDADD_LE: "QDADD.LE", |
5756 arm_QDADD: "QDADD", | 7113 arm_QDADD: "QDADD", |
5757 arm_QDADD_ZZ: "QDADD.ZZ", | 7114 arm_QDADD_ZZ: "QDADD.ZZ", |
5758 arm_QDSUB_EQ: "QDSUB.EQ", | 7115 arm_QDSUB_EQ: "QDSUB.EQ", |
5759 arm_QDSUB_NE: "QDSUB.NE", | 7116 arm_QDSUB_NE: "QDSUB.NE", |
5760 arm_QDSUB_CS: "QDSUB.CS", | 7117 arm_QDSUB_CS: "QDSUB.CS", |
5761 arm_QDSUB_CC: "QDSUB.CC", | 7118 arm_QDSUB_CC: "QDSUB.CC", |
5762 arm_QDSUB_MI: "QDSUB.MI", | 7119 arm_QDSUB_MI: "QDSUB.MI", |
5763 arm_QDSUB_PL: "QDSUB.PL", | 7120 arm_QDSUB_PL: "QDSUB.PL", |
5764 arm_QDSUB_VS: "QDSUB.VS", | 7121 arm_QDSUB_VS: "QDSUB.VS", |
5765 arm_QDSUB_VC: "QDSUB.VC", | 7122 arm_QDSUB_VC: "QDSUB.VC", |
5766 arm_QDSUB_HI: "QDSUB.HI", | 7123 arm_QDSUB_HI: "QDSUB.HI", |
5767 arm_QDSUB_LS: "QDSUB.LS", | 7124 arm_QDSUB_LS: "QDSUB.LS", |
5768 arm_QDSUB_GE: "QDSUB.GE", | 7125 arm_QDSUB_GE: "QDSUB.GE", |
5769 arm_QDSUB_LT: "QDSUB.LT", | 7126 arm_QDSUB_LT: "QDSUB.LT", |
5770 arm_QDSUB_GT: "QDSUB.GT", | 7127 arm_QDSUB_GT: "QDSUB.GT", |
5771 arm_QDSUB_LE: "QDSUB.LE", | 7128 arm_QDSUB_LE: "QDSUB.LE", |
5772 arm_QDSUB: "QDSUB", | 7129 arm_QDSUB: "QDSUB", |
5773 arm_QDSUB_ZZ: "QDSUB.ZZ", | 7130 arm_QDSUB_ZZ: "QDSUB.ZZ", |
5774 arm_QSAX_EQ: "QSAX.EQ", | 7131 arm_QSAX_EQ: "QSAX.EQ", |
5775 arm_QSAX_NE: "QSAX.NE", | 7132 arm_QSAX_NE: "QSAX.NE", |
5776 arm_QSAX_CS: "QSAX.CS", | 7133 arm_QSAX_CS: "QSAX.CS", |
5777 arm_QSAX_CC: "QSAX.CC", | 7134 arm_QSAX_CC: "QSAX.CC", |
5778 arm_QSAX_MI: "QSAX.MI", | 7135 arm_QSAX_MI: "QSAX.MI", |
5779 arm_QSAX_PL: "QSAX.PL", | 7136 arm_QSAX_PL: "QSAX.PL", |
5780 arm_QSAX_VS: "QSAX.VS", | 7137 arm_QSAX_VS: "QSAX.VS", |
5781 arm_QSAX_VC: "QSAX.VC", | 7138 arm_QSAX_VC: "QSAX.VC", |
5782 arm_QSAX_HI: "QSAX.HI", | 7139 arm_QSAX_HI: "QSAX.HI", |
5783 arm_QSAX_LS: "QSAX.LS", | 7140 arm_QSAX_LS: "QSAX.LS", |
5784 arm_QSAX_GE: "QSAX.GE", | 7141 arm_QSAX_GE: "QSAX.GE", |
5785 arm_QSAX_LT: "QSAX.LT", | 7142 arm_QSAX_LT: "QSAX.LT", |
5786 arm_QSAX_GT: "QSAX.GT", | 7143 arm_QSAX_GT: "QSAX.GT", |
5787 arm_QSAX_LE: "QSAX.LE", | 7144 arm_QSAX_LE: "QSAX.LE", |
5788 arm_QSAX: "QSAX", | 7145 arm_QSAX: "QSAX", |
5789 arm_QSAX_ZZ: "QSAX.ZZ", | 7146 arm_QSAX_ZZ: "QSAX.ZZ", |
5790 arm_QSUB_EQ: "QSUB.EQ", | 7147 arm_QSUB_EQ: "QSUB.EQ", |
5791 arm_QSUB_NE: "QSUB.NE", | 7148 arm_QSUB_NE: "QSUB.NE", |
5792 arm_QSUB_CS: "QSUB.CS", | 7149 arm_QSUB_CS: "QSUB.CS", |
5793 arm_QSUB_CC: "QSUB.CC", | 7150 arm_QSUB_CC: "QSUB.CC", |
5794 arm_QSUB_MI: "QSUB.MI", | 7151 arm_QSUB_MI: "QSUB.MI", |
5795 arm_QSUB_PL: "QSUB.PL", | 7152 arm_QSUB_PL: "QSUB.PL", |
5796 arm_QSUB_VS: "QSUB.VS", | 7153 arm_QSUB_VS: "QSUB.VS", |
5797 arm_QSUB_VC: "QSUB.VC", | 7154 arm_QSUB_VC: "QSUB.VC", |
5798 arm_QSUB_HI: "QSUB.HI", | 7155 arm_QSUB_HI: "QSUB.HI", |
5799 arm_QSUB_LS: "QSUB.LS", | 7156 arm_QSUB_LS: "QSUB.LS", |
5800 arm_QSUB_GE: "QSUB.GE", | 7157 arm_QSUB_GE: "QSUB.GE", |
5801 arm_QSUB_LT: "QSUB.LT", | 7158 arm_QSUB_LT: "QSUB.LT", |
5802 arm_QSUB_GT: "QSUB.GT", | 7159 arm_QSUB_GT: "QSUB.GT", |
5803 arm_QSUB_LE: "QSUB.LE", | 7160 arm_QSUB_LE: "QSUB.LE", |
5804 arm_QSUB: "QSUB", | 7161 arm_QSUB: "QSUB", |
5805 arm_QSUB_ZZ: "QSUB.ZZ", | 7162 arm_QSUB_ZZ: "QSUB.ZZ", |
5806 arm_QSUB16_EQ: "QSUB16.EQ", | 7163 arm_QSUB16_EQ: "QSUB16.EQ", |
5807 arm_QSUB16_NE: "QSUB16.NE", | 7164 arm_QSUB16_NE: "QSUB16.NE", |
5808 arm_QSUB16_CS: "QSUB16.CS", | 7165 arm_QSUB16_CS: "QSUB16.CS", |
5809 arm_QSUB16_CC: "QSUB16.CC", | 7166 arm_QSUB16_CC: "QSUB16.CC", |
5810 arm_QSUB16_MI: "QSUB16.MI", | 7167 arm_QSUB16_MI: "QSUB16.MI", |
5811 arm_QSUB16_PL: "QSUB16.PL", | 7168 arm_QSUB16_PL: "QSUB16.PL", |
5812 arm_QSUB16_VS: "QSUB16.VS", | 7169 arm_QSUB16_VS: "QSUB16.VS", |
5813 arm_QSUB16_VC: "QSUB16.VC", | 7170 arm_QSUB16_VC: "QSUB16.VC", |
5814 arm_QSUB16_HI: "QSUB16.HI", | 7171 arm_QSUB16_HI: "QSUB16.HI", |
5815 arm_QSUB16_LS: "QSUB16.LS", | 7172 arm_QSUB16_LS: "QSUB16.LS", |
5816 arm_QSUB16_GE: "QSUB16.GE", | 7173 arm_QSUB16_GE: "QSUB16.GE", |
5817 arm_QSUB16_LT: "QSUB16.LT", | 7174 arm_QSUB16_LT: "QSUB16.LT", |
5818 arm_QSUB16_GT: "QSUB16.GT", | 7175 arm_QSUB16_GT: "QSUB16.GT", |
5819 arm_QSUB16_LE: "QSUB16.LE", | 7176 arm_QSUB16_LE: "QSUB16.LE", |
5820 arm_QSUB16: "QSUB16", | 7177 arm_QSUB16: "QSUB16", |
5821 arm_QSUB16_ZZ: "QSUB16.ZZ", | 7178 arm_QSUB16_ZZ: "QSUB16.ZZ", |
5822 arm_QSUB8_EQ: "QSUB8.EQ", | 7179 arm_QSUB8_EQ: "QSUB8.EQ", |
5823 arm_QSUB8_NE: "QSUB8.NE", | 7180 arm_QSUB8_NE: "QSUB8.NE", |
5824 arm_QSUB8_CS: "QSUB8.CS", | 7181 arm_QSUB8_CS: "QSUB8.CS", |
5825 arm_QSUB8_CC: "QSUB8.CC", | 7182 arm_QSUB8_CC: "QSUB8.CC", |
5826 arm_QSUB8_MI: "QSUB8.MI", | 7183 arm_QSUB8_MI: "QSUB8.MI", |
5827 arm_QSUB8_PL: "QSUB8.PL", | 7184 arm_QSUB8_PL: "QSUB8.PL", |
5828 arm_QSUB8_VS: "QSUB8.VS", | 7185 arm_QSUB8_VS: "QSUB8.VS", |
5829 arm_QSUB8_VC: "QSUB8.VC", | 7186 arm_QSUB8_VC: "QSUB8.VC", |
5830 arm_QSUB8_HI: "QSUB8.HI", | 7187 arm_QSUB8_HI: "QSUB8.HI", |
5831 arm_QSUB8_LS: "QSUB8.LS", | 7188 arm_QSUB8_LS: "QSUB8.LS", |
5832 arm_QSUB8_GE: "QSUB8.GE", | 7189 arm_QSUB8_GE: "QSUB8.GE", |
5833 arm_QSUB8_LT: "QSUB8.LT", | 7190 arm_QSUB8_LT: "QSUB8.LT", |
5834 arm_QSUB8_GT: "QSUB8.GT", | 7191 arm_QSUB8_GT: "QSUB8.GT", |
5835 arm_QSUB8_LE: "QSUB8.LE", | 7192 arm_QSUB8_LE: "QSUB8.LE", |
5836 arm_QSUB8: "QSUB8", | 7193 arm_QSUB8: "QSUB8", |
5837 arm_QSUB8_ZZ: "QSUB8.ZZ", | 7194 arm_QSUB8_ZZ: "QSUB8.ZZ", |
5838 arm_RBIT_EQ: "RBIT.EQ", | 7195 arm_RBIT_EQ: "RBIT.EQ", |
5839 arm_RBIT_NE: "RBIT.NE", | 7196 arm_RBIT_NE: "RBIT.NE", |
5840 arm_RBIT_CS: "RBIT.CS", | 7197 arm_RBIT_CS: "RBIT.CS", |
5841 arm_RBIT_CC: "RBIT.CC", | 7198 arm_RBIT_CC: "RBIT.CC", |
5842 arm_RBIT_MI: "RBIT.MI", | 7199 arm_RBIT_MI: "RBIT.MI", |
5843 arm_RBIT_PL: "RBIT.PL", | 7200 arm_RBIT_PL: "RBIT.PL", |
5844 arm_RBIT_VS: "RBIT.VS", | 7201 arm_RBIT_VS: "RBIT.VS", |
5845 arm_RBIT_VC: "RBIT.VC", | 7202 arm_RBIT_VC: "RBIT.VC", |
5846 arm_RBIT_HI: "RBIT.HI", | 7203 arm_RBIT_HI: "RBIT.HI", |
5847 arm_RBIT_LS: "RBIT.LS", | 7204 arm_RBIT_LS: "RBIT.LS", |
5848 arm_RBIT_GE: "RBIT.GE", | 7205 arm_RBIT_GE: "RBIT.GE", |
5849 arm_RBIT_LT: "RBIT.LT", | 7206 arm_RBIT_LT: "RBIT.LT", |
5850 arm_RBIT_GT: "RBIT.GT", | 7207 arm_RBIT_GT: "RBIT.GT", |
5851 arm_RBIT_LE: "RBIT.LE", | 7208 arm_RBIT_LE: "RBIT.LE", |
5852 arm_RBIT: "RBIT", | 7209 arm_RBIT: "RBIT", |
5853 arm_RBIT_ZZ: "RBIT.ZZ", | 7210 arm_RBIT_ZZ: "RBIT.ZZ", |
5854 arm_REV_EQ: "REV.EQ", | 7211 arm_REV_EQ: "REV.EQ", |
5855 arm_REV_NE: "REV.NE", | 7212 arm_REV_NE: "REV.NE", |
5856 arm_REV_CS: "REV.CS", | 7213 arm_REV_CS: "REV.CS", |
5857 arm_REV_CC: "REV.CC", | 7214 arm_REV_CC: "REV.CC", |
5858 arm_REV_MI: "REV.MI", | 7215 arm_REV_MI: "REV.MI", |
5859 arm_REV_PL: "REV.PL", | 7216 arm_REV_PL: "REV.PL", |
5860 arm_REV_VS: "REV.VS", | 7217 arm_REV_VS: "REV.VS", |
5861 arm_REV_VC: "REV.VC", | 7218 arm_REV_VC: "REV.VC", |
5862 arm_REV_HI: "REV.HI", | 7219 arm_REV_HI: "REV.HI", |
5863 arm_REV_LS: "REV.LS", | 7220 arm_REV_LS: "REV.LS", |
5864 arm_REV_GE: "REV.GE", | 7221 arm_REV_GE: "REV.GE", |
5865 arm_REV_LT: "REV.LT", | 7222 arm_REV_LT: "REV.LT", |
5866 arm_REV_GT: "REV.GT", | 7223 arm_REV_GT: "REV.GT", |
5867 arm_REV_LE: "REV.LE", | 7224 arm_REV_LE: "REV.LE", |
5868 arm_REV: "REV", | 7225 arm_REV: "REV", |
5869 arm_REV_ZZ: "REV.ZZ", | 7226 arm_REV_ZZ: "REV.ZZ", |
5870 arm_REV16_EQ: "REV16.EQ", | 7227 arm_REV16_EQ: "REV16.EQ", |
5871 arm_REV16_NE: "REV16.NE", | 7228 arm_REV16_NE: "REV16.NE", |
5872 arm_REV16_CS: "REV16.CS", | 7229 arm_REV16_CS: "REV16.CS", |
5873 arm_REV16_CC: "REV16.CC", | 7230 arm_REV16_CC: "REV16.CC", |
5874 arm_REV16_MI: "REV16.MI", | 7231 arm_REV16_MI: "REV16.MI", |
5875 arm_REV16_PL: "REV16.PL", | 7232 arm_REV16_PL: "REV16.PL", |
5876 arm_REV16_VS: "REV16.VS", | 7233 arm_REV16_VS: "REV16.VS", |
5877 arm_REV16_VC: "REV16.VC", | 7234 arm_REV16_VC: "REV16.VC", |
5878 arm_REV16_HI: "REV16.HI", | 7235 arm_REV16_HI: "REV16.HI", |
5879 arm_REV16_LS: "REV16.LS", | 7236 arm_REV16_LS: "REV16.LS", |
5880 arm_REV16_GE: "REV16.GE", | 7237 arm_REV16_GE: "REV16.GE", |
5881 arm_REV16_LT: "REV16.LT", | 7238 arm_REV16_LT: "REV16.LT", |
5882 arm_REV16_GT: "REV16.GT", | 7239 arm_REV16_GT: "REV16.GT", |
5883 arm_REV16_LE: "REV16.LE", | 7240 arm_REV16_LE: "REV16.LE", |
5884 arm_REV16: "REV16", | 7241 arm_REV16: "REV16", |
5885 arm_REV16_ZZ: "REV16.ZZ", | 7242 arm_REV16_ZZ: "REV16.ZZ", |
5886 arm_REVSH_EQ: "REVSH.EQ", | 7243 arm_REVSH_EQ: "REVSH.EQ", |
5887 arm_REVSH_NE: "REVSH.NE", | 7244 arm_REVSH_NE: "REVSH.NE", |
5888 arm_REVSH_CS: "REVSH.CS", | 7245 arm_REVSH_CS: "REVSH.CS", |
5889 arm_REVSH_CC: "REVSH.CC", | 7246 arm_REVSH_CC: "REVSH.CC", |
5890 arm_REVSH_MI: "REVSH.MI", | 7247 arm_REVSH_MI: "REVSH.MI", |
5891 arm_REVSH_PL: "REVSH.PL", | 7248 arm_REVSH_PL: "REVSH.PL", |
5892 arm_REVSH_VS: "REVSH.VS", | 7249 arm_REVSH_VS: "REVSH.VS", |
5893 arm_REVSH_VC: "REVSH.VC", | 7250 arm_REVSH_VC: "REVSH.VC", |
5894 arm_REVSH_HI: "REVSH.HI", | 7251 arm_REVSH_HI: "REVSH.HI", |
5895 arm_REVSH_LS: "REVSH.LS", | 7252 arm_REVSH_LS: "REVSH.LS", |
5896 arm_REVSH_GE: "REVSH.GE", | 7253 arm_REVSH_GE: "REVSH.GE", |
5897 arm_REVSH_LT: "REVSH.LT", | 7254 arm_REVSH_LT: "REVSH.LT", |
5898 arm_REVSH_GT: "REVSH.GT", | 7255 arm_REVSH_GT: "REVSH.GT", |
5899 arm_REVSH_LE: "REVSH.LE", | 7256 arm_REVSH_LE: "REVSH.LE", |
5900 arm_REVSH: "REVSH", | 7257 arm_REVSH: "REVSH", |
5901 arm_REVSH_ZZ: "REVSH.ZZ", | 7258 arm_REVSH_ZZ: "REVSH.ZZ", |
5902 arm_ROR_EQ: "ROR.EQ", | 7259 arm_ROR_EQ: "ROR.EQ", |
5903 arm_ROR_NE: "ROR.NE", | 7260 arm_ROR_NE: "ROR.NE", |
5904 arm_ROR_CS: "ROR.CS", | 7261 arm_ROR_CS: "ROR.CS", |
5905 arm_ROR_CC: "ROR.CC", | 7262 arm_ROR_CC: "ROR.CC", |
5906 arm_ROR_MI: "ROR.MI", | 7263 arm_ROR_MI: "ROR.MI", |
5907 arm_ROR_PL: "ROR.PL", | 7264 arm_ROR_PL: "ROR.PL", |
5908 arm_ROR_VS: "ROR.VS", | 7265 arm_ROR_VS: "ROR.VS", |
5909 arm_ROR_VC: "ROR.VC", | 7266 arm_ROR_VC: "ROR.VC", |
5910 arm_ROR_HI: "ROR.HI", | 7267 arm_ROR_HI: "ROR.HI", |
5911 arm_ROR_LS: "ROR.LS", | 7268 arm_ROR_LS: "ROR.LS", |
5912 arm_ROR_GE: "ROR.GE", | 7269 arm_ROR_GE: "ROR.GE", |
5913 arm_ROR_LT: "ROR.LT", | 7270 arm_ROR_LT: "ROR.LT", |
5914 arm_ROR_GT: "ROR.GT", | 7271 arm_ROR_GT: "ROR.GT", |
5915 arm_ROR_LE: "ROR.LE", | 7272 arm_ROR_LE: "ROR.LE", |
5916 arm_ROR: "ROR", | 7273 arm_ROR: "ROR", |
5917 arm_ROR_ZZ: "ROR.ZZ", | 7274 arm_ROR_ZZ: "ROR.ZZ", |
5918 arm_ROR_S_EQ: "ROR.S.EQ", | 7275 arm_ROR_S_EQ: "ROR.S.EQ", |
5919 arm_ROR_S_NE: "ROR.S.NE", | 7276 arm_ROR_S_NE: "ROR.S.NE", |
5920 arm_ROR_S_CS: "ROR.S.CS", | 7277 arm_ROR_S_CS: "ROR.S.CS", |
5921 arm_ROR_S_CC: "ROR.S.CC", | 7278 arm_ROR_S_CC: "ROR.S.CC", |
5922 arm_ROR_S_MI: "ROR.S.MI", | 7279 arm_ROR_S_MI: "ROR.S.MI", |
5923 arm_ROR_S_PL: "ROR.S.PL", | 7280 arm_ROR_S_PL: "ROR.S.PL", |
5924 arm_ROR_S_VS: "ROR.S.VS", | 7281 arm_ROR_S_VS: "ROR.S.VS", |
5925 arm_ROR_S_VC: "ROR.S.VC", | 7282 arm_ROR_S_VC: "ROR.S.VC", |
5926 arm_ROR_S_HI: "ROR.S.HI", | 7283 arm_ROR_S_HI: "ROR.S.HI", |
5927 arm_ROR_S_LS: "ROR.S.LS", | 7284 arm_ROR_S_LS: "ROR.S.LS", |
5928 arm_ROR_S_GE: "ROR.S.GE", | 7285 arm_ROR_S_GE: "ROR.S.GE", |
5929 arm_ROR_S_LT: "ROR.S.LT", | 7286 arm_ROR_S_LT: "ROR.S.LT", |
5930 arm_ROR_S_GT: "ROR.S.GT", | 7287 arm_ROR_S_GT: "ROR.S.GT", |
5931 arm_ROR_S_LE: "ROR.S.LE", | 7288 arm_ROR_S_LE: "ROR.S.LE", |
5932 arm_ROR_S: "ROR.S", | 7289 arm_ROR_S: "ROR.S", |
5933 arm_ROR_S_ZZ: "ROR.S.ZZ", | 7290 arm_ROR_S_ZZ: "ROR.S.ZZ", |
5934 arm_RRX_EQ: "RRX.EQ", | 7291 arm_RRX_EQ: "RRX.EQ", |
5935 arm_RRX_NE: "RRX.NE", | 7292 arm_RRX_NE: "RRX.NE", |
5936 arm_RRX_CS: "RRX.CS", | 7293 arm_RRX_CS: "RRX.CS", |
5937 arm_RRX_CC: "RRX.CC", | 7294 arm_RRX_CC: "RRX.CC", |
5938 arm_RRX_MI: "RRX.MI", | 7295 arm_RRX_MI: "RRX.MI", |
5939 arm_RRX_PL: "RRX.PL", | 7296 arm_RRX_PL: "RRX.PL", |
5940 arm_RRX_VS: "RRX.VS", | 7297 arm_RRX_VS: "RRX.VS", |
5941 arm_RRX_VC: "RRX.VC", | 7298 arm_RRX_VC: "RRX.VC", |
5942 arm_RRX_HI: "RRX.HI", | 7299 arm_RRX_HI: "RRX.HI", |
5943 arm_RRX_LS: "RRX.LS", | 7300 arm_RRX_LS: "RRX.LS", |
5944 arm_RRX_GE: "RRX.GE", | 7301 arm_RRX_GE: "RRX.GE", |
5945 arm_RRX_LT: "RRX.LT", | 7302 arm_RRX_LT: "RRX.LT", |
5946 arm_RRX_GT: "RRX.GT", | 7303 arm_RRX_GT: "RRX.GT", |
5947 arm_RRX_LE: "RRX.LE", | 7304 arm_RRX_LE: "RRX.LE", |
5948 arm_RRX: "RRX", | 7305 arm_RRX: "RRX", |
5949 arm_RRX_ZZ: "RRX.ZZ", | 7306 arm_RRX_ZZ: "RRX.ZZ", |
5950 arm_RRX_S_EQ: "RRX.S.EQ", | 7307 arm_RRX_S_EQ: "RRX.S.EQ", |
5951 arm_RRX_S_NE: "RRX.S.NE", | 7308 arm_RRX_S_NE: "RRX.S.NE", |
5952 arm_RRX_S_CS: "RRX.S.CS", | 7309 arm_RRX_S_CS: "RRX.S.CS", |
5953 arm_RRX_S_CC: "RRX.S.CC", | 7310 arm_RRX_S_CC: "RRX.S.CC", |
5954 arm_RRX_S_MI: "RRX.S.MI", | 7311 arm_RRX_S_MI: "RRX.S.MI", |
5955 arm_RRX_S_PL: "RRX.S.PL", | 7312 arm_RRX_S_PL: "RRX.S.PL", |
5956 arm_RRX_S_VS: "RRX.S.VS", | 7313 arm_RRX_S_VS: "RRX.S.VS", |
5957 arm_RRX_S_VC: "RRX.S.VC", | 7314 arm_RRX_S_VC: "RRX.S.VC", |
5958 arm_RRX_S_HI: "RRX.S.HI", | 7315 arm_RRX_S_HI: "RRX.S.HI", |
5959 arm_RRX_S_LS: "RRX.S.LS", | 7316 arm_RRX_S_LS: "RRX.S.LS", |
5960 arm_RRX_S_GE: "RRX.S.GE", | 7317 arm_RRX_S_GE: "RRX.S.GE", |
5961 arm_RRX_S_LT: "RRX.S.LT", | 7318 arm_RRX_S_LT: "RRX.S.LT", |
5962 arm_RRX_S_GT: "RRX.S.GT", | 7319 arm_RRX_S_GT: "RRX.S.GT", |
5963 arm_RRX_S_LE: "RRX.S.LE", | 7320 arm_RRX_S_LE: "RRX.S.LE", |
5964 arm_RRX_S: "RRX.S", | 7321 arm_RRX_S: "RRX.S", |
5965 arm_RRX_S_ZZ: "RRX.S.ZZ", | 7322 arm_RRX_S_ZZ: "RRX.S.ZZ", |
5966 arm_RSB_EQ: "RSB.EQ", | 7323 arm_RSB_EQ: "RSB.EQ", |
5967 arm_RSB_NE: "RSB.NE", | 7324 arm_RSB_NE: "RSB.NE", |
5968 arm_RSB_CS: "RSB.CS", | 7325 arm_RSB_CS: "RSB.CS", |
5969 arm_RSB_CC: "RSB.CC", | 7326 arm_RSB_CC: "RSB.CC", |
5970 arm_RSB_MI: "RSB.MI", | 7327 arm_RSB_MI: "RSB.MI", |
5971 arm_RSB_PL: "RSB.PL", | 7328 arm_RSB_PL: "RSB.PL", |
5972 arm_RSB_VS: "RSB.VS", | 7329 arm_RSB_VS: "RSB.VS", |
5973 arm_RSB_VC: "RSB.VC", | 7330 arm_RSB_VC: "RSB.VC", |
5974 arm_RSB_HI: "RSB.HI", | 7331 arm_RSB_HI: "RSB.HI", |
5975 arm_RSB_LS: "RSB.LS", | 7332 arm_RSB_LS: "RSB.LS", |
5976 arm_RSB_GE: "RSB.GE", | 7333 arm_RSB_GE: "RSB.GE", |
5977 arm_RSB_LT: "RSB.LT", | 7334 arm_RSB_LT: "RSB.LT", |
5978 arm_RSB_GT: "RSB.GT", | 7335 arm_RSB_GT: "RSB.GT", |
5979 arm_RSB_LE: "RSB.LE", | 7336 arm_RSB_LE: "RSB.LE", |
5980 arm_RSB: "RSB", | 7337 arm_RSB: "RSB", |
5981 arm_RSB_ZZ: "RSB.ZZ", | 7338 arm_RSB_ZZ: "RSB.ZZ", |
5982 arm_RSB_S_EQ: "RSB.S.EQ", | 7339 arm_RSB_S_EQ: "RSB.S.EQ", |
5983 arm_RSB_S_NE: "RSB.S.NE", | 7340 arm_RSB_S_NE: "RSB.S.NE", |
5984 arm_RSB_S_CS: "RSB.S.CS", | 7341 arm_RSB_S_CS: "RSB.S.CS", |
5985 arm_RSB_S_CC: "RSB.S.CC", | 7342 arm_RSB_S_CC: "RSB.S.CC", |
5986 arm_RSB_S_MI: "RSB.S.MI", | 7343 arm_RSB_S_MI: "RSB.S.MI", |
5987 arm_RSB_S_PL: "RSB.S.PL", | 7344 arm_RSB_S_PL: "RSB.S.PL", |
5988 arm_RSB_S_VS: "RSB.S.VS", | 7345 arm_RSB_S_VS: "RSB.S.VS", |
5989 arm_RSB_S_VC: "RSB.S.VC", | 7346 arm_RSB_S_VC: "RSB.S.VC", |
5990 arm_RSB_S_HI: "RSB.S.HI", | 7347 arm_RSB_S_HI: "RSB.S.HI", |
5991 arm_RSB_S_LS: "RSB.S.LS", | 7348 arm_RSB_S_LS: "RSB.S.LS", |
5992 arm_RSB_S_GE: "RSB.S.GE", | 7349 arm_RSB_S_GE: "RSB.S.GE", |
5993 arm_RSB_S_LT: "RSB.S.LT", | 7350 arm_RSB_S_LT: "RSB.S.LT", |
5994 arm_RSB_S_GT: "RSB.S.GT", | 7351 arm_RSB_S_GT: "RSB.S.GT", |
5995 arm_RSB_S_LE: "RSB.S.LE", | 7352 arm_RSB_S_LE: "RSB.S.LE", |
5996 arm_RSB_S: "RSB.S", | 7353 arm_RSB_S: "RSB.S", |
5997 arm_RSB_S_ZZ: "RSB.S.ZZ", | 7354 arm_RSB_S_ZZ: "RSB.S.ZZ", |
5998 arm_RSC_EQ: "RSC.EQ", | 7355 arm_RSC_EQ: "RSC.EQ", |
5999 arm_RSC_NE: "RSC.NE", | 7356 arm_RSC_NE: "RSC.NE", |
6000 arm_RSC_CS: "RSC.CS", | 7357 arm_RSC_CS: "RSC.CS", |
6001 arm_RSC_CC: "RSC.CC", | 7358 arm_RSC_CC: "RSC.CC", |
6002 arm_RSC_MI: "RSC.MI", | 7359 arm_RSC_MI: "RSC.MI", |
6003 arm_RSC_PL: "RSC.PL", | 7360 arm_RSC_PL: "RSC.PL", |
6004 arm_RSC_VS: "RSC.VS", | 7361 arm_RSC_VS: "RSC.VS", |
6005 arm_RSC_VC: "RSC.VC", | 7362 arm_RSC_VC: "RSC.VC", |
6006 arm_RSC_HI: "RSC.HI", | 7363 arm_RSC_HI: "RSC.HI", |
6007 arm_RSC_LS: "RSC.LS", | 7364 arm_RSC_LS: "RSC.LS", |
6008 arm_RSC_GE: "RSC.GE", | 7365 arm_RSC_GE: "RSC.GE", |
6009 arm_RSC_LT: "RSC.LT", | 7366 arm_RSC_LT: "RSC.LT", |
6010 arm_RSC_GT: "RSC.GT", | 7367 arm_RSC_GT: "RSC.GT", |
6011 arm_RSC_LE: "RSC.LE", | 7368 arm_RSC_LE: "RSC.LE", |
6012 arm_RSC: "RSC", | 7369 arm_RSC: "RSC", |
6013 arm_RSC_ZZ: "RSC.ZZ", | 7370 arm_RSC_ZZ: "RSC.ZZ", |
6014 arm_RSC_S_EQ: "RSC.S.EQ", | 7371 arm_RSC_S_EQ: "RSC.S.EQ", |
6015 arm_RSC_S_NE: "RSC.S.NE", | 7372 arm_RSC_S_NE: "RSC.S.NE", |
6016 arm_RSC_S_CS: "RSC.S.CS", | 7373 arm_RSC_S_CS: "RSC.S.CS", |
6017 arm_RSC_S_CC: "RSC.S.CC", | 7374 arm_RSC_S_CC: "RSC.S.CC", |
6018 arm_RSC_S_MI: "RSC.S.MI", | 7375 arm_RSC_S_MI: "RSC.S.MI", |
6019 arm_RSC_S_PL: "RSC.S.PL", | 7376 arm_RSC_S_PL: "RSC.S.PL", |
6020 arm_RSC_S_VS: "RSC.S.VS", | 7377 arm_RSC_S_VS: "RSC.S.VS", |
6021 arm_RSC_S_VC: "RSC.S.VC", | 7378 arm_RSC_S_VC: "RSC.S.VC", |
6022 arm_RSC_S_HI: "RSC.S.HI", | 7379 arm_RSC_S_HI: "RSC.S.HI", |
6023 arm_RSC_S_LS: "RSC.S.LS", | 7380 arm_RSC_S_LS: "RSC.S.LS", |
6024 arm_RSC_S_GE: "RSC.S.GE", | 7381 arm_RSC_S_GE: "RSC.S.GE", |
6025 arm_RSC_S_LT: "RSC.S.LT", | 7382 arm_RSC_S_LT: "RSC.S.LT", |
6026 arm_RSC_S_GT: "RSC.S.GT", | 7383 arm_RSC_S_GT: "RSC.S.GT", |
6027 arm_RSC_S_LE: "RSC.S.LE", | 7384 arm_RSC_S_LE: "RSC.S.LE", |
6028 arm_RSC_S: "RSC.S", | 7385 arm_RSC_S: "RSC.S", |
6029 arm_RSC_S_ZZ: "RSC.S.ZZ", | 7386 arm_RSC_S_ZZ: "RSC.S.ZZ", |
6030 arm_SADD16_EQ: "SADD16.EQ", | 7387 arm_SADD16_EQ: "SADD16.EQ", |
6031 arm_SADD16_NE: "SADD16.NE", | 7388 arm_SADD16_NE: "SADD16.NE", |
6032 arm_SADD16_CS: "SADD16.CS", | 7389 arm_SADD16_CS: "SADD16.CS", |
6033 arm_SADD16_CC: "SADD16.CC", | 7390 arm_SADD16_CC: "SADD16.CC", |
6034 arm_SADD16_MI: "SADD16.MI", | 7391 arm_SADD16_MI: "SADD16.MI", |
6035 arm_SADD16_PL: "SADD16.PL", | 7392 arm_SADD16_PL: "SADD16.PL", |
6036 arm_SADD16_VS: "SADD16.VS", | 7393 arm_SADD16_VS: "SADD16.VS", |
6037 arm_SADD16_VC: "SADD16.VC", | 7394 arm_SADD16_VC: "SADD16.VC", |
6038 arm_SADD16_HI: "SADD16.HI", | 7395 arm_SADD16_HI: "SADD16.HI", |
6039 arm_SADD16_LS: "SADD16.LS", | 7396 arm_SADD16_LS: "SADD16.LS", |
6040 arm_SADD16_GE: "SADD16.GE", | 7397 arm_SADD16_GE: "SADD16.GE", |
6041 arm_SADD16_LT: "SADD16.LT", | 7398 arm_SADD16_LT: "SADD16.LT", |
6042 arm_SADD16_GT: "SADD16.GT", | 7399 arm_SADD16_GT: "SADD16.GT", |
6043 arm_SADD16_LE: "SADD16.LE", | 7400 arm_SADD16_LE: "SADD16.LE", |
6044 arm_SADD16: "SADD16", | 7401 arm_SADD16: "SADD16", |
6045 arm_SADD16_ZZ: "SADD16.ZZ", | 7402 arm_SADD16_ZZ: "SADD16.ZZ", |
6046 arm_SADD8_EQ: "SADD8.EQ", | 7403 arm_SADD8_EQ: "SADD8.EQ", |
6047 arm_SADD8_NE: "SADD8.NE", | 7404 arm_SADD8_NE: "SADD8.NE", |
6048 arm_SADD8_CS: "SADD8.CS", | 7405 arm_SADD8_CS: "SADD8.CS", |
6049 arm_SADD8_CC: "SADD8.CC", | 7406 arm_SADD8_CC: "SADD8.CC", |
6050 arm_SADD8_MI: "SADD8.MI", | 7407 arm_SADD8_MI: "SADD8.MI", |
6051 arm_SADD8_PL: "SADD8.PL", | 7408 arm_SADD8_PL: "SADD8.PL", |
6052 arm_SADD8_VS: "SADD8.VS", | 7409 arm_SADD8_VS: "SADD8.VS", |
6053 arm_SADD8_VC: "SADD8.VC", | 7410 arm_SADD8_VC: "SADD8.VC", |
6054 arm_SADD8_HI: "SADD8.HI", | 7411 arm_SADD8_HI: "SADD8.HI", |
6055 arm_SADD8_LS: "SADD8.LS", | 7412 arm_SADD8_LS: "SADD8.LS", |
6056 arm_SADD8_GE: "SADD8.GE", | 7413 arm_SADD8_GE: "SADD8.GE", |
6057 arm_SADD8_LT: "SADD8.LT", | 7414 arm_SADD8_LT: "SADD8.LT", |
6058 arm_SADD8_GT: "SADD8.GT", | 7415 arm_SADD8_GT: "SADD8.GT", |
6059 arm_SADD8_LE: "SADD8.LE", | 7416 arm_SADD8_LE: "SADD8.LE", |
6060 arm_SADD8: "SADD8", | 7417 arm_SADD8: "SADD8", |
6061 arm_SADD8_ZZ: "SADD8.ZZ", | 7418 arm_SADD8_ZZ: "SADD8.ZZ", |
6062 arm_SASX_EQ: "SASX.EQ", | 7419 arm_SASX_EQ: "SASX.EQ", |
6063 arm_SASX_NE: "SASX.NE", | 7420 arm_SASX_NE: "SASX.NE", |
6064 arm_SASX_CS: "SASX.CS", | 7421 arm_SASX_CS: "SASX.CS", |
6065 arm_SASX_CC: "SASX.CC", | 7422 arm_SASX_CC: "SASX.CC", |
6066 arm_SASX_MI: "SASX.MI", | 7423 arm_SASX_MI: "SASX.MI", |
6067 arm_SASX_PL: "SASX.PL", | 7424 arm_SASX_PL: "SASX.PL", |
6068 arm_SASX_VS: "SASX.VS", | 7425 arm_SASX_VS: "SASX.VS", |
6069 arm_SASX_VC: "SASX.VC", | 7426 arm_SASX_VC: "SASX.VC", |
6070 arm_SASX_HI: "SASX.HI", | 7427 arm_SASX_HI: "SASX.HI", |
6071 arm_SASX_LS: "SASX.LS", | 7428 arm_SASX_LS: "SASX.LS", |
6072 arm_SASX_GE: "SASX.GE", | 7429 arm_SASX_GE: "SASX.GE", |
6073 arm_SASX_LT: "SASX.LT", | 7430 arm_SASX_LT: "SASX.LT", |
6074 arm_SASX_GT: "SASX.GT", | 7431 arm_SASX_GT: "SASX.GT", |
6075 arm_SASX_LE: "SASX.LE", | 7432 arm_SASX_LE: "SASX.LE", |
6076 arm_SASX: "SASX", | 7433 arm_SASX: "SASX", |
6077 arm_SASX_ZZ: "SASX.ZZ", | 7434 arm_SASX_ZZ: "SASX.ZZ", |
6078 arm_SBC_EQ: "SBC.EQ", | 7435 arm_SBC_EQ: "SBC.EQ", |
6079 arm_SBC_NE: "SBC.NE", | 7436 arm_SBC_NE: "SBC.NE", |
6080 arm_SBC_CS: "SBC.CS", | 7437 arm_SBC_CS: "SBC.CS", |
6081 arm_SBC_CC: "SBC.CC", | 7438 arm_SBC_CC: "SBC.CC", |
6082 arm_SBC_MI: "SBC.MI", | 7439 arm_SBC_MI: "SBC.MI", |
6083 arm_SBC_PL: "SBC.PL", | 7440 arm_SBC_PL: "SBC.PL", |
6084 arm_SBC_VS: "SBC.VS", | 7441 arm_SBC_VS: "SBC.VS", |
6085 arm_SBC_VC: "SBC.VC", | 7442 arm_SBC_VC: "SBC.VC", |
6086 arm_SBC_HI: "SBC.HI", | 7443 arm_SBC_HI: "SBC.HI", |
6087 arm_SBC_LS: "SBC.LS", | 7444 arm_SBC_LS: "SBC.LS", |
6088 arm_SBC_GE: "SBC.GE", | 7445 arm_SBC_GE: "SBC.GE", |
6089 arm_SBC_LT: "SBC.LT", | 7446 arm_SBC_LT: "SBC.LT", |
6090 arm_SBC_GT: "SBC.GT", | 7447 arm_SBC_GT: "SBC.GT", |
6091 arm_SBC_LE: "SBC.LE", | 7448 arm_SBC_LE: "SBC.LE", |
6092 arm_SBC: "SBC", | 7449 arm_SBC: "SBC", |
6093 arm_SBC_ZZ: "SBC.ZZ", | 7450 arm_SBC_ZZ: "SBC.ZZ", |
6094 arm_SBC_S_EQ: "SBC.S.EQ", | 7451 arm_SBC_S_EQ: "SBC.S.EQ", |
6095 arm_SBC_S_NE: "SBC.S.NE", | 7452 arm_SBC_S_NE: "SBC.S.NE", |
6096 arm_SBC_S_CS: "SBC.S.CS", | 7453 arm_SBC_S_CS: "SBC.S.CS", |
6097 arm_SBC_S_CC: "SBC.S.CC", | 7454 arm_SBC_S_CC: "SBC.S.CC", |
6098 arm_SBC_S_MI: "SBC.S.MI", | 7455 arm_SBC_S_MI: "SBC.S.MI", |
6099 arm_SBC_S_PL: "SBC.S.PL", | 7456 arm_SBC_S_PL: "SBC.S.PL", |
6100 arm_SBC_S_VS: "SBC.S.VS", | 7457 arm_SBC_S_VS: "SBC.S.VS", |
6101 arm_SBC_S_VC: "SBC.S.VC", | 7458 arm_SBC_S_VC: "SBC.S.VC", |
6102 arm_SBC_S_HI: "SBC.S.HI", | 7459 arm_SBC_S_HI: "SBC.S.HI", |
6103 arm_SBC_S_LS: "SBC.S.LS", | 7460 arm_SBC_S_LS: "SBC.S.LS", |
6104 arm_SBC_S_GE: "SBC.S.GE", | 7461 arm_SBC_S_GE: "SBC.S.GE", |
6105 arm_SBC_S_LT: "SBC.S.LT", | 7462 arm_SBC_S_LT: "SBC.S.LT", |
6106 arm_SBC_S_GT: "SBC.S.GT", | 7463 arm_SBC_S_GT: "SBC.S.GT", |
6107 arm_SBC_S_LE: "SBC.S.LE", | 7464 arm_SBC_S_LE: "SBC.S.LE", |
6108 arm_SBC_S: "SBC.S", | 7465 arm_SBC_S: "SBC.S", |
6109 arm_SBC_S_ZZ: "SBC.S.ZZ", | 7466 arm_SBC_S_ZZ: "SBC.S.ZZ", |
6110 arm_SBFX_EQ: "SBFX.EQ", | 7467 arm_SBFX_EQ: "SBFX.EQ", |
6111 arm_SBFX_NE: "SBFX.NE", | 7468 arm_SBFX_NE: "SBFX.NE", |
6112 arm_SBFX_CS: "SBFX.CS", | 7469 arm_SBFX_CS: "SBFX.CS", |
6113 arm_SBFX_CC: "SBFX.CC", | 7470 arm_SBFX_CC: "SBFX.CC", |
6114 arm_SBFX_MI: "SBFX.MI", | 7471 arm_SBFX_MI: "SBFX.MI", |
6115 arm_SBFX_PL: "SBFX.PL", | 7472 arm_SBFX_PL: "SBFX.PL", |
6116 arm_SBFX_VS: "SBFX.VS", | 7473 arm_SBFX_VS: "SBFX.VS", |
6117 arm_SBFX_VC: "SBFX.VC", | 7474 arm_SBFX_VC: "SBFX.VC", |
6118 arm_SBFX_HI: "SBFX.HI", | 7475 arm_SBFX_HI: "SBFX.HI", |
6119 arm_SBFX_LS: "SBFX.LS", | 7476 arm_SBFX_LS: "SBFX.LS", |
6120 arm_SBFX_GE: "SBFX.GE", | 7477 arm_SBFX_GE: "SBFX.GE", |
6121 arm_SBFX_LT: "SBFX.LT", | 7478 arm_SBFX_LT: "SBFX.LT", |
6122 arm_SBFX_GT: "SBFX.GT", | 7479 arm_SBFX_GT: "SBFX.GT", |
6123 arm_SBFX_LE: "SBFX.LE", | 7480 arm_SBFX_LE: "SBFX.LE", |
6124 arm_SBFX: "SBFX", | 7481 arm_SBFX: "SBFX", |
6125 arm_SBFX_ZZ: "SBFX.ZZ", | 7482 arm_SBFX_ZZ: "SBFX.ZZ", |
6126 arm_SEL_EQ: "SEL.EQ", | 7483 arm_SEL_EQ: "SEL.EQ", |
6127 arm_SEL_NE: "SEL.NE", | 7484 arm_SEL_NE: "SEL.NE", |
6128 arm_SEL_CS: "SEL.CS", | 7485 arm_SEL_CS: "SEL.CS", |
6129 arm_SEL_CC: "SEL.CC", | 7486 arm_SEL_CC: "SEL.CC", |
6130 arm_SEL_MI: "SEL.MI", | 7487 arm_SEL_MI: "SEL.MI", |
6131 arm_SEL_PL: "SEL.PL", | 7488 arm_SEL_PL: "SEL.PL", |
6132 arm_SEL_VS: "SEL.VS", | 7489 arm_SEL_VS: "SEL.VS", |
6133 arm_SEL_VC: "SEL.VC", | 7490 arm_SEL_VC: "SEL.VC", |
6134 arm_SEL_HI: "SEL.HI", | 7491 arm_SEL_HI: "SEL.HI", |
6135 arm_SEL_LS: "SEL.LS", | 7492 arm_SEL_LS: "SEL.LS", |
6136 arm_SEL_GE: "SEL.GE", | 7493 arm_SEL_GE: "SEL.GE", |
6137 arm_SEL_LT: "SEL.LT", | 7494 arm_SEL_LT: "SEL.LT", |
6138 arm_SEL_GT: "SEL.GT", | 7495 arm_SEL_GT: "SEL.GT", |
6139 arm_SEL_LE: "SEL.LE", | 7496 arm_SEL_LE: "SEL.LE", |
6140 arm_SEL: "SEL", | 7497 arm_SEL: "SEL", |
6141 arm_SEL_ZZ: "SEL.ZZ", | 7498 arm_SEL_ZZ: "SEL.ZZ", |
6142 arm_SETEND: "SETEND", | 7499 arm_SETEND: "SETEND", |
6143 arm_SEV_EQ: "SEV.EQ", | 7500 arm_SEV_EQ: "SEV.EQ", |
6144 arm_SEV_NE: "SEV.NE", | 7501 arm_SEV_NE: "SEV.NE", |
6145 arm_SEV_CS: "SEV.CS", | 7502 arm_SEV_CS: "SEV.CS", |
6146 arm_SEV_CC: "SEV.CC", | 7503 arm_SEV_CC: "SEV.CC", |
6147 arm_SEV_MI: "SEV.MI", | 7504 arm_SEV_MI: "SEV.MI", |
6148 arm_SEV_PL: "SEV.PL", | 7505 arm_SEV_PL: "SEV.PL", |
6149 arm_SEV_VS: "SEV.VS", | 7506 arm_SEV_VS: "SEV.VS", |
6150 arm_SEV_VC: "SEV.VC", | 7507 arm_SEV_VC: "SEV.VC", |
6151 arm_SEV_HI: "SEV.HI", | 7508 arm_SEV_HI: "SEV.HI", |
6152 arm_SEV_LS: "SEV.LS", | 7509 arm_SEV_LS: "SEV.LS", |
6153 arm_SEV_GE: "SEV.GE", | 7510 arm_SEV_GE: "SEV.GE", |
6154 arm_SEV_LT: "SEV.LT", | 7511 arm_SEV_LT: "SEV.LT", |
6155 arm_SEV_GT: "SEV.GT", | 7512 arm_SEV_GT: "SEV.GT", |
6156 arm_SEV_LE: "SEV.LE", | 7513 arm_SEV_LE: "SEV.LE", |
6157 arm_SEV: "SEV", | 7514 arm_SEV: "SEV", |
6158 arm_SEV_ZZ: "SEV.ZZ", | 7515 arm_SEV_ZZ: "SEV.ZZ", |
6159 arm_SHADD16_EQ: "SHADD16.EQ", | 7516 arm_SHADD16_EQ: "SHADD16.EQ", |
6160 arm_SHADD16_NE: "SHADD16.NE", | 7517 arm_SHADD16_NE: "SHADD16.NE", |
6161 arm_SHADD16_CS: "SHADD16.CS", | 7518 arm_SHADD16_CS: "SHADD16.CS", |
6162 arm_SHADD16_CC: "SHADD16.CC", | 7519 arm_SHADD16_CC: "SHADD16.CC", |
6163 arm_SHADD16_MI: "SHADD16.MI", | 7520 arm_SHADD16_MI: "SHADD16.MI", |
6164 arm_SHADD16_PL: "SHADD16.PL", | 7521 arm_SHADD16_PL: "SHADD16.PL", |
6165 arm_SHADD16_VS: "SHADD16.VS", | 7522 arm_SHADD16_VS: "SHADD16.VS", |
6166 arm_SHADD16_VC: "SHADD16.VC", | 7523 arm_SHADD16_VC: "SHADD16.VC", |
6167 arm_SHADD16_HI: "SHADD16.HI", | 7524 arm_SHADD16_HI: "SHADD16.HI", |
6168 arm_SHADD16_LS: "SHADD16.LS", | 7525 arm_SHADD16_LS: "SHADD16.LS", |
6169 arm_SHADD16_GE: "SHADD16.GE", | 7526 arm_SHADD16_GE: "SHADD16.GE", |
6170 arm_SHADD16_LT: "SHADD16.LT", | 7527 arm_SHADD16_LT: "SHADD16.LT", |
6171 arm_SHADD16_GT: "SHADD16.GT", | 7528 arm_SHADD16_GT: "SHADD16.GT", |
6172 arm_SHADD16_LE: "SHADD16.LE", | 7529 arm_SHADD16_LE: "SHADD16.LE", |
6173 arm_SHADD16: "SHADD16", | 7530 arm_SHADD16: "SHADD16", |
6174 arm_SHADD16_ZZ: "SHADD16.ZZ", | 7531 arm_SHADD16_ZZ: "SHADD16.ZZ", |
6175 arm_SHADD8_EQ: "SHADD8.EQ", | 7532 arm_SHADD8_EQ: "SHADD8.EQ", |
6176 arm_SHADD8_NE: "SHADD8.NE", | 7533 arm_SHADD8_NE: "SHADD8.NE", |
6177 arm_SHADD8_CS: "SHADD8.CS", | 7534 arm_SHADD8_CS: "SHADD8.CS", |
6178 arm_SHADD8_CC: "SHADD8.CC", | 7535 arm_SHADD8_CC: "SHADD8.CC", |
6179 arm_SHADD8_MI: "SHADD8.MI", | 7536 arm_SHADD8_MI: "SHADD8.MI", |
6180 arm_SHADD8_PL: "SHADD8.PL", | 7537 arm_SHADD8_PL: "SHADD8.PL", |
6181 arm_SHADD8_VS: "SHADD8.VS", | 7538 arm_SHADD8_VS: "SHADD8.VS", |
6182 arm_SHADD8_VC: "SHADD8.VC", | 7539 arm_SHADD8_VC: "SHADD8.VC", |
6183 arm_SHADD8_HI: "SHADD8.HI", | 7540 arm_SHADD8_HI: "SHADD8.HI", |
6184 arm_SHADD8_LS: "SHADD8.LS", | 7541 arm_SHADD8_LS: "SHADD8.LS", |
6185 arm_SHADD8_GE: "SHADD8.GE", | 7542 arm_SHADD8_GE: "SHADD8.GE", |
6186 arm_SHADD8_LT: "SHADD8.LT", | 7543 arm_SHADD8_LT: "SHADD8.LT", |
6187 arm_SHADD8_GT: "SHADD8.GT", | 7544 arm_SHADD8_GT: "SHADD8.GT", |
6188 arm_SHADD8_LE: "SHADD8.LE", | 7545 arm_SHADD8_LE: "SHADD8.LE", |
6189 arm_SHADD8: "SHADD8", | 7546 arm_SHADD8: "SHADD8", |
6190 arm_SHADD8_ZZ: "SHADD8.ZZ", | 7547 arm_SHADD8_ZZ: "SHADD8.ZZ", |
6191 arm_SHASX_EQ: "SHASX.EQ", | 7548 arm_SHASX_EQ: "SHASX.EQ", |
6192 arm_SHASX_NE: "SHASX.NE", | 7549 arm_SHASX_NE: "SHASX.NE", |
6193 arm_SHASX_CS: "SHASX.CS", | 7550 arm_SHASX_CS: "SHASX.CS", |
6194 arm_SHASX_CC: "SHASX.CC", | 7551 arm_SHASX_CC: "SHASX.CC", |
6195 arm_SHASX_MI: "SHASX.MI", | 7552 arm_SHASX_MI: "SHASX.MI", |
6196 arm_SHASX_PL: "SHASX.PL", | 7553 arm_SHASX_PL: "SHASX.PL", |
6197 arm_SHASX_VS: "SHASX.VS", | 7554 arm_SHASX_VS: "SHASX.VS", |
6198 arm_SHASX_VC: "SHASX.VC", | 7555 arm_SHASX_VC: "SHASX.VC", |
6199 arm_SHASX_HI: "SHASX.HI", | 7556 arm_SHASX_HI: "SHASX.HI", |
6200 arm_SHASX_LS: "SHASX.LS", | 7557 arm_SHASX_LS: "SHASX.LS", |
6201 arm_SHASX_GE: "SHASX.GE", | 7558 arm_SHASX_GE: "SHASX.GE", |
6202 arm_SHASX_LT: "SHASX.LT", | 7559 arm_SHASX_LT: "SHASX.LT", |
6203 arm_SHASX_GT: "SHASX.GT", | 7560 arm_SHASX_GT: "SHASX.GT", |
6204 arm_SHASX_LE: "SHASX.LE", | 7561 arm_SHASX_LE: "SHASX.LE", |
6205 arm_SHASX: "SHASX", | 7562 arm_SHASX: "SHASX", |
6206 arm_SHASX_ZZ: "SHASX.ZZ", | 7563 arm_SHASX_ZZ: "SHASX.ZZ", |
6207 arm_SHSAX_EQ: "SHSAX.EQ", | 7564 arm_SHSAX_EQ: "SHSAX.EQ", |
6208 arm_SHSAX_NE: "SHSAX.NE", | 7565 arm_SHSAX_NE: "SHSAX.NE", |
6209 arm_SHSAX_CS: "SHSAX.CS", | 7566 arm_SHSAX_CS: "SHSAX.CS", |
6210 arm_SHSAX_CC: "SHSAX.CC", | 7567 arm_SHSAX_CC: "SHSAX.CC", |
6211 arm_SHSAX_MI: "SHSAX.MI", | 7568 arm_SHSAX_MI: "SHSAX.MI", |
6212 arm_SHSAX_PL: "SHSAX.PL", | 7569 arm_SHSAX_PL: "SHSAX.PL", |
6213 arm_SHSAX_VS: "SHSAX.VS", | 7570 arm_SHSAX_VS: "SHSAX.VS", |
6214 arm_SHSAX_VC: "SHSAX.VC", | 7571 arm_SHSAX_VC: "SHSAX.VC", |
6215 arm_SHSAX_HI: "SHSAX.HI", | 7572 arm_SHSAX_HI: "SHSAX.HI", |
6216 arm_SHSAX_LS: "SHSAX.LS", | 7573 arm_SHSAX_LS: "SHSAX.LS", |
6217 arm_SHSAX_GE: "SHSAX.GE", | 7574 arm_SHSAX_GE: "SHSAX.GE", |
6218 arm_SHSAX_LT: "SHSAX.LT", | 7575 arm_SHSAX_LT: "SHSAX.LT", |
6219 arm_SHSAX_GT: "SHSAX.GT", | 7576 arm_SHSAX_GT: "SHSAX.GT", |
6220 arm_SHSAX_LE: "SHSAX.LE", | 7577 arm_SHSAX_LE: "SHSAX.LE", |
6221 arm_SHSAX: "SHSAX", | 7578 arm_SHSAX: "SHSAX", |
6222 arm_SHSAX_ZZ: "SHSAX.ZZ", | 7579 arm_SHSAX_ZZ: "SHSAX.ZZ", |
6223 arm_SHSUB16_EQ: "SHSUB16.EQ", | 7580 arm_SHSUB16_EQ: "SHSUB16.EQ", |
6224 arm_SHSUB16_NE: "SHSUB16.NE", | 7581 arm_SHSUB16_NE: "SHSUB16.NE", |
6225 arm_SHSUB16_CS: "SHSUB16.CS", | 7582 arm_SHSUB16_CS: "SHSUB16.CS", |
6226 arm_SHSUB16_CC: "SHSUB16.CC", | 7583 arm_SHSUB16_CC: "SHSUB16.CC", |
6227 arm_SHSUB16_MI: "SHSUB16.MI", | 7584 arm_SHSUB16_MI: "SHSUB16.MI", |
6228 arm_SHSUB16_PL: "SHSUB16.PL", | 7585 arm_SHSUB16_PL: "SHSUB16.PL", |
6229 arm_SHSUB16_VS: "SHSUB16.VS", | 7586 arm_SHSUB16_VS: "SHSUB16.VS", |
6230 arm_SHSUB16_VC: "SHSUB16.VC", | 7587 arm_SHSUB16_VC: "SHSUB16.VC", |
6231 arm_SHSUB16_HI: "SHSUB16.HI", | 7588 arm_SHSUB16_HI: "SHSUB16.HI", |
6232 arm_SHSUB16_LS: "SHSUB16.LS", | 7589 arm_SHSUB16_LS: "SHSUB16.LS", |
6233 arm_SHSUB16_GE: "SHSUB16.GE", | 7590 arm_SHSUB16_GE: "SHSUB16.GE", |
6234 arm_SHSUB16_LT: "SHSUB16.LT", | 7591 arm_SHSUB16_LT: "SHSUB16.LT", |
6235 arm_SHSUB16_GT: "SHSUB16.GT", | 7592 arm_SHSUB16_GT: "SHSUB16.GT", |
6236 arm_SHSUB16_LE: "SHSUB16.LE", | 7593 arm_SHSUB16_LE: "SHSUB16.LE", |
6237 arm_SHSUB16: "SHSUB16", | 7594 arm_SHSUB16: "SHSUB16", |
6238 arm_SHSUB16_ZZ: "SHSUB16.ZZ", | 7595 arm_SHSUB16_ZZ: "SHSUB16.ZZ", |
6239 arm_SHSUB8_EQ: "SHSUB8.EQ", | 7596 arm_SHSUB8_EQ: "SHSUB8.EQ", |
6240 arm_SHSUB8_NE: "SHSUB8.NE", | 7597 arm_SHSUB8_NE: "SHSUB8.NE", |
6241 arm_SHSUB8_CS: "SHSUB8.CS", | 7598 arm_SHSUB8_CS: "SHSUB8.CS", |
6242 arm_SHSUB8_CC: "SHSUB8.CC", | 7599 arm_SHSUB8_CC: "SHSUB8.CC", |
6243 arm_SHSUB8_MI: "SHSUB8.MI", | 7600 arm_SHSUB8_MI: "SHSUB8.MI", |
6244 arm_SHSUB8_PL: "SHSUB8.PL", | 7601 arm_SHSUB8_PL: "SHSUB8.PL", |
6245 arm_SHSUB8_VS: "SHSUB8.VS", | 7602 arm_SHSUB8_VS: "SHSUB8.VS", |
6246 arm_SHSUB8_VC: "SHSUB8.VC", | 7603 arm_SHSUB8_VC: "SHSUB8.VC", |
6247 arm_SHSUB8_HI: "SHSUB8.HI", | 7604 arm_SHSUB8_HI: "SHSUB8.HI", |
6248 arm_SHSUB8_LS: "SHSUB8.LS", | 7605 arm_SHSUB8_LS: "SHSUB8.LS", |
6249 arm_SHSUB8_GE: "SHSUB8.GE", | 7606 arm_SHSUB8_GE: "SHSUB8.GE", |
6250 arm_SHSUB8_LT: "SHSUB8.LT", | 7607 arm_SHSUB8_LT: "SHSUB8.LT", |
6251 arm_SHSUB8_GT: "SHSUB8.GT", | 7608 arm_SHSUB8_GT: "SHSUB8.GT", |
6252 arm_SHSUB8_LE: "SHSUB8.LE", | 7609 arm_SHSUB8_LE: "SHSUB8.LE", |
6253 arm_SHSUB8: "SHSUB8", | 7610 arm_SHSUB8: "SHSUB8", |
6254 arm_SHSUB8_ZZ: "SHSUB8.ZZ", | 7611 arm_SHSUB8_ZZ: "SHSUB8.ZZ", |
6255 arm_SMLABB_EQ: "SMLABB.EQ", | 7612 arm_SMLABB_EQ: "SMLABB.EQ", |
6256 arm_SMLABB_NE: "SMLABB.NE", | 7613 arm_SMLABB_NE: "SMLABB.NE", |
6257 arm_SMLABB_CS: "SMLABB.CS", | 7614 arm_SMLABB_CS: "SMLABB.CS", |
6258 arm_SMLABB_CC: "SMLABB.CC", | 7615 arm_SMLABB_CC: "SMLABB.CC", |
6259 arm_SMLABB_MI: "SMLABB.MI", | 7616 arm_SMLABB_MI: "SMLABB.MI", |
6260 arm_SMLABB_PL: "SMLABB.PL", | 7617 arm_SMLABB_PL: "SMLABB.PL", |
6261 arm_SMLABB_VS: "SMLABB.VS", | 7618 arm_SMLABB_VS: "SMLABB.VS", |
6262 arm_SMLABB_VC: "SMLABB.VC", | 7619 arm_SMLABB_VC: "SMLABB.VC", |
6263 arm_SMLABB_HI: "SMLABB.HI", | 7620 arm_SMLABB_HI: "SMLABB.HI", |
6264 arm_SMLABB_LS: "SMLABB.LS", | 7621 arm_SMLABB_LS: "SMLABB.LS", |
6265 arm_SMLABB_GE: "SMLABB.GE", | 7622 arm_SMLABB_GE: "SMLABB.GE", |
6266 arm_SMLABB_LT: "SMLABB.LT", | 7623 arm_SMLABB_LT: "SMLABB.LT", |
6267 arm_SMLABB_GT: "SMLABB.GT", | 7624 arm_SMLABB_GT: "SMLABB.GT", |
6268 arm_SMLABB_LE: "SMLABB.LE", | 7625 arm_SMLABB_LE: "SMLABB.LE", |
6269 arm_SMLABB: "SMLABB", | 7626 arm_SMLABB: "SMLABB", |
6270 arm_SMLABB_ZZ: "SMLABB.ZZ", | 7627 arm_SMLABB_ZZ: "SMLABB.ZZ", |
6271 arm_SMLABT_EQ: "SMLABT.EQ", | 7628 arm_SMLABT_EQ: "SMLABT.EQ", |
6272 arm_SMLABT_NE: "SMLABT.NE", | 7629 arm_SMLABT_NE: "SMLABT.NE", |
6273 arm_SMLABT_CS: "SMLABT.CS", | 7630 arm_SMLABT_CS: "SMLABT.CS", |
6274 arm_SMLABT_CC: "SMLABT.CC", | 7631 arm_SMLABT_CC: "SMLABT.CC", |
6275 arm_SMLABT_MI: "SMLABT.MI", | 7632 arm_SMLABT_MI: "SMLABT.MI", |
6276 arm_SMLABT_PL: "SMLABT.PL", | 7633 arm_SMLABT_PL: "SMLABT.PL", |
6277 arm_SMLABT_VS: "SMLABT.VS", | 7634 arm_SMLABT_VS: "SMLABT.VS", |
6278 arm_SMLABT_VC: "SMLABT.VC", | 7635 arm_SMLABT_VC: "SMLABT.VC", |
6279 arm_SMLABT_HI: "SMLABT.HI", | 7636 arm_SMLABT_HI: "SMLABT.HI", |
6280 arm_SMLABT_LS: "SMLABT.LS", | 7637 arm_SMLABT_LS: "SMLABT.LS", |
6281 arm_SMLABT_GE: "SMLABT.GE", | 7638 arm_SMLABT_GE: "SMLABT.GE", |
6282 arm_SMLABT_LT: "SMLABT.LT", | 7639 arm_SMLABT_LT: "SMLABT.LT", |
6283 arm_SMLABT_GT: "SMLABT.GT", | 7640 arm_SMLABT_GT: "SMLABT.GT", |
6284 arm_SMLABT_LE: "SMLABT.LE", | 7641 arm_SMLABT_LE: "SMLABT.LE", |
6285 arm_SMLABT: "SMLABT", | 7642 arm_SMLABT: "SMLABT", |
6286 arm_SMLABT_ZZ: "SMLABT.ZZ", | 7643 arm_SMLABT_ZZ: "SMLABT.ZZ", |
6287 arm_SMLATB_EQ: "SMLATB.EQ", | 7644 arm_SMLATB_EQ: "SMLATB.EQ", |
6288 arm_SMLATB_NE: "SMLATB.NE", | 7645 arm_SMLATB_NE: "SMLATB.NE", |
6289 arm_SMLATB_CS: "SMLATB.CS", | 7646 arm_SMLATB_CS: "SMLATB.CS", |
6290 arm_SMLATB_CC: "SMLATB.CC", | 7647 arm_SMLATB_CC: "SMLATB.CC", |
6291 arm_SMLATB_MI: "SMLATB.MI", | 7648 arm_SMLATB_MI: "SMLATB.MI", |
6292 arm_SMLATB_PL: "SMLATB.PL", | 7649 arm_SMLATB_PL: "SMLATB.PL", |
6293 arm_SMLATB_VS: "SMLATB.VS", | 7650 arm_SMLATB_VS: "SMLATB.VS", |
6294 arm_SMLATB_VC: "SMLATB.VC", | 7651 arm_SMLATB_VC: "SMLATB.VC", |
6295 arm_SMLATB_HI: "SMLATB.HI", | 7652 arm_SMLATB_HI: "SMLATB.HI", |
6296 arm_SMLATB_LS: "SMLATB.LS", | 7653 arm_SMLATB_LS: "SMLATB.LS", |
6297 arm_SMLATB_GE: "SMLATB.GE", | 7654 arm_SMLATB_GE: "SMLATB.GE", |
6298 arm_SMLATB_LT: "SMLATB.LT", | 7655 arm_SMLATB_LT: "SMLATB.LT", |
6299 arm_SMLATB_GT: "SMLATB.GT", | 7656 arm_SMLATB_GT: "SMLATB.GT", |
6300 arm_SMLATB_LE: "SMLATB.LE", | 7657 arm_SMLATB_LE: "SMLATB.LE", |
6301 arm_SMLATB: "SMLATB", | 7658 arm_SMLATB: "SMLATB", |
6302 arm_SMLATB_ZZ: "SMLATB.ZZ", | 7659 arm_SMLATB_ZZ: "SMLATB.ZZ", |
6303 arm_SMLATT_EQ: "SMLATT.EQ", | 7660 arm_SMLATT_EQ: "SMLATT.EQ", |
6304 arm_SMLATT_NE: "SMLATT.NE", | 7661 arm_SMLATT_NE: "SMLATT.NE", |
6305 arm_SMLATT_CS: "SMLATT.CS", | 7662 arm_SMLATT_CS: "SMLATT.CS", |
6306 arm_SMLATT_CC: "SMLATT.CC", | 7663 arm_SMLATT_CC: "SMLATT.CC", |
6307 arm_SMLATT_MI: "SMLATT.MI", | 7664 arm_SMLATT_MI: "SMLATT.MI", |
6308 arm_SMLATT_PL: "SMLATT.PL", | 7665 arm_SMLATT_PL: "SMLATT.PL", |
6309 arm_SMLATT_VS: "SMLATT.VS", | 7666 arm_SMLATT_VS: "SMLATT.VS", |
6310 arm_SMLATT_VC: "SMLATT.VC", | 7667 arm_SMLATT_VC: "SMLATT.VC", |
6311 arm_SMLATT_HI: "SMLATT.HI", | 7668 arm_SMLATT_HI: "SMLATT.HI", |
6312 arm_SMLATT_LS: "SMLATT.LS", | 7669 arm_SMLATT_LS: "SMLATT.LS", |
6313 arm_SMLATT_GE: "SMLATT.GE", | 7670 arm_SMLATT_GE: "SMLATT.GE", |
6314 arm_SMLATT_LT: "SMLATT.LT", | 7671 arm_SMLATT_LT: "SMLATT.LT", |
6315 arm_SMLATT_GT: "SMLATT.GT", | 7672 arm_SMLATT_GT: "SMLATT.GT", |
6316 arm_SMLATT_LE: "SMLATT.LE", | 7673 arm_SMLATT_LE: "SMLATT.LE", |
6317 arm_SMLATT: "SMLATT", | 7674 arm_SMLATT: "SMLATT", |
6318 arm_SMLATT_ZZ: "SMLATT.ZZ", | 7675 arm_SMLATT_ZZ: "SMLATT.ZZ", |
6319 arm_SMLAD_EQ: "SMLAD.EQ", | 7676 arm_SMLAD_EQ: "SMLAD.EQ", |
6320 arm_SMLAD_NE: "SMLAD.NE", | 7677 arm_SMLAD_NE: "SMLAD.NE", |
6321 arm_SMLAD_CS: "SMLAD.CS", | 7678 arm_SMLAD_CS: "SMLAD.CS", |
6322 arm_SMLAD_CC: "SMLAD.CC", | 7679 arm_SMLAD_CC: "SMLAD.CC", |
6323 arm_SMLAD_MI: "SMLAD.MI", | 7680 arm_SMLAD_MI: "SMLAD.MI", |
6324 arm_SMLAD_PL: "SMLAD.PL", | 7681 arm_SMLAD_PL: "SMLAD.PL", |
6325 arm_SMLAD_VS: "SMLAD.VS", | 7682 arm_SMLAD_VS: "SMLAD.VS", |
6326 arm_SMLAD_VC: "SMLAD.VC", | 7683 arm_SMLAD_VC: "SMLAD.VC", |
6327 arm_SMLAD_HI: "SMLAD.HI", | 7684 arm_SMLAD_HI: "SMLAD.HI", |
6328 arm_SMLAD_LS: "SMLAD.LS", | 7685 arm_SMLAD_LS: "SMLAD.LS", |
6329 arm_SMLAD_GE: "SMLAD.GE", | 7686 arm_SMLAD_GE: "SMLAD.GE", |
6330 arm_SMLAD_LT: "SMLAD.LT", | 7687 arm_SMLAD_LT: "SMLAD.LT", |
6331 arm_SMLAD_GT: "SMLAD.GT", | 7688 arm_SMLAD_GT: "SMLAD.GT", |
6332 arm_SMLAD_LE: "SMLAD.LE", | 7689 arm_SMLAD_LE: "SMLAD.LE", |
6333 arm_SMLAD: "SMLAD", | 7690 arm_SMLAD: "SMLAD", |
6334 arm_SMLAD_ZZ: "SMLAD.ZZ", | 7691 arm_SMLAD_ZZ: "SMLAD.ZZ", |
6335 arm_SMLAD_X_EQ: "SMLAD.X.EQ", | 7692 arm_SMLAD_X_EQ: "SMLAD.X.EQ", |
6336 arm_SMLAD_X_NE: "SMLAD.X.NE", | 7693 arm_SMLAD_X_NE: "SMLAD.X.NE", |
6337 arm_SMLAD_X_CS: "SMLAD.X.CS", | 7694 arm_SMLAD_X_CS: "SMLAD.X.CS", |
6338 arm_SMLAD_X_CC: "SMLAD.X.CC", | 7695 arm_SMLAD_X_CC: "SMLAD.X.CC", |
6339 arm_SMLAD_X_MI: "SMLAD.X.MI", | 7696 arm_SMLAD_X_MI: "SMLAD.X.MI", |
6340 arm_SMLAD_X_PL: "SMLAD.X.PL", | 7697 arm_SMLAD_X_PL: "SMLAD.X.PL", |
6341 arm_SMLAD_X_VS: "SMLAD.X.VS", | 7698 arm_SMLAD_X_VS: "SMLAD.X.VS", |
6342 arm_SMLAD_X_VC: "SMLAD.X.VC", | 7699 arm_SMLAD_X_VC: "SMLAD.X.VC", |
6343 arm_SMLAD_X_HI: "SMLAD.X.HI", | 7700 arm_SMLAD_X_HI: "SMLAD.X.HI", |
6344 arm_SMLAD_X_LS: "SMLAD.X.LS", | 7701 arm_SMLAD_X_LS: "SMLAD.X.LS", |
6345 arm_SMLAD_X_GE: "SMLAD.X.GE", | 7702 arm_SMLAD_X_GE: "SMLAD.X.GE", |
6346 arm_SMLAD_X_LT: "SMLAD.X.LT", | 7703 arm_SMLAD_X_LT: "SMLAD.X.LT", |
6347 arm_SMLAD_X_GT: "SMLAD.X.GT", | 7704 arm_SMLAD_X_GT: "SMLAD.X.GT", |
6348 arm_SMLAD_X_LE: "SMLAD.X.LE", | 7705 arm_SMLAD_X_LE: "SMLAD.X.LE", |
6349 arm_SMLAD_X: "SMLAD.X", | 7706 arm_SMLAD_X: "SMLAD.X", |
6350 arm_SMLAD_X_ZZ: "SMLAD.X.ZZ", | 7707 arm_SMLAD_X_ZZ: "SMLAD.X.ZZ", |
6351 arm_SMLAL_EQ: "SMLAL.EQ", | 7708 arm_SMLAL_EQ: "SMLAL.EQ", |
6352 arm_SMLAL_NE: "SMLAL.NE", | 7709 arm_SMLAL_NE: "SMLAL.NE", |
6353 arm_SMLAL_CS: "SMLAL.CS", | 7710 arm_SMLAL_CS: "SMLAL.CS", |
6354 arm_SMLAL_CC: "SMLAL.CC", | 7711 arm_SMLAL_CC: "SMLAL.CC", |
6355 arm_SMLAL_MI: "SMLAL.MI", | 7712 arm_SMLAL_MI: "SMLAL.MI", |
6356 arm_SMLAL_PL: "SMLAL.PL", | 7713 arm_SMLAL_PL: "SMLAL.PL", |
6357 arm_SMLAL_VS: "SMLAL.VS", | 7714 arm_SMLAL_VS: "SMLAL.VS", |
6358 arm_SMLAL_VC: "SMLAL.VC", | 7715 arm_SMLAL_VC: "SMLAL.VC", |
6359 arm_SMLAL_HI: "SMLAL.HI", | 7716 arm_SMLAL_HI: "SMLAL.HI", |
6360 arm_SMLAL_LS: "SMLAL.LS", | 7717 arm_SMLAL_LS: "SMLAL.LS", |
6361 arm_SMLAL_GE: "SMLAL.GE", | 7718 arm_SMLAL_GE: "SMLAL.GE", |
6362 arm_SMLAL_LT: "SMLAL.LT", | 7719 arm_SMLAL_LT: "SMLAL.LT", |
6363 arm_SMLAL_GT: "SMLAL.GT", | 7720 arm_SMLAL_GT: "SMLAL.GT", |
6364 arm_SMLAL_LE: "SMLAL.LE", | 7721 arm_SMLAL_LE: "SMLAL.LE", |
6365 arm_SMLAL: "SMLAL", | 7722 arm_SMLAL: "SMLAL", |
6366 arm_SMLAL_ZZ: "SMLAL.ZZ", | 7723 arm_SMLAL_ZZ: "SMLAL.ZZ", |
6367 arm_SMLAL_S_EQ: "SMLAL.S.EQ", | 7724 arm_SMLAL_S_EQ: "SMLAL.S.EQ", |
6368 arm_SMLAL_S_NE: "SMLAL.S.NE", | 7725 arm_SMLAL_S_NE: "SMLAL.S.NE", |
6369 arm_SMLAL_S_CS: "SMLAL.S.CS", | 7726 arm_SMLAL_S_CS: "SMLAL.S.CS", |
6370 arm_SMLAL_S_CC: "SMLAL.S.CC", | 7727 arm_SMLAL_S_CC: "SMLAL.S.CC", |
6371 arm_SMLAL_S_MI: "SMLAL.S.MI", | 7728 arm_SMLAL_S_MI: "SMLAL.S.MI", |
6372 arm_SMLAL_S_PL: "SMLAL.S.PL", | 7729 arm_SMLAL_S_PL: "SMLAL.S.PL", |
6373 arm_SMLAL_S_VS: "SMLAL.S.VS", | 7730 arm_SMLAL_S_VS: "SMLAL.S.VS", |
6374 arm_SMLAL_S_VC: "SMLAL.S.VC", | 7731 arm_SMLAL_S_VC: "SMLAL.S.VC", |
6375 arm_SMLAL_S_HI: "SMLAL.S.HI", | 7732 arm_SMLAL_S_HI: "SMLAL.S.HI", |
6376 arm_SMLAL_S_LS: "SMLAL.S.LS", | 7733 arm_SMLAL_S_LS: "SMLAL.S.LS", |
6377 arm_SMLAL_S_GE: "SMLAL.S.GE", | 7734 arm_SMLAL_S_GE: "SMLAL.S.GE", |
6378 arm_SMLAL_S_LT: "SMLAL.S.LT", | 7735 arm_SMLAL_S_LT: "SMLAL.S.LT", |
6379 arm_SMLAL_S_GT: "SMLAL.S.GT", | 7736 arm_SMLAL_S_GT: "SMLAL.S.GT", |
6380 arm_SMLAL_S_LE: "SMLAL.S.LE", | 7737 arm_SMLAL_S_LE: "SMLAL.S.LE", |
6381 arm_SMLAL_S: "SMLAL.S", | 7738 arm_SMLAL_S: "SMLAL.S", |
6382 arm_SMLAL_S_ZZ: "SMLAL.S.ZZ", | 7739 arm_SMLAL_S_ZZ: "SMLAL.S.ZZ", |
6383 arm_SMLALBB_EQ: "SMLALBB.EQ", | 7740 arm_SMLALBB_EQ: "SMLALBB.EQ", |
6384 arm_SMLALBB_NE: "SMLALBB.NE", | 7741 arm_SMLALBB_NE: "SMLALBB.NE", |
6385 arm_SMLALBB_CS: "SMLALBB.CS", | 7742 arm_SMLALBB_CS: "SMLALBB.CS", |
6386 arm_SMLALBB_CC: "SMLALBB.CC", | 7743 arm_SMLALBB_CC: "SMLALBB.CC", |
6387 arm_SMLALBB_MI: "SMLALBB.MI", | 7744 arm_SMLALBB_MI: "SMLALBB.MI", |
6388 arm_SMLALBB_PL: "SMLALBB.PL", | 7745 arm_SMLALBB_PL: "SMLALBB.PL", |
6389 arm_SMLALBB_VS: "SMLALBB.VS", | 7746 arm_SMLALBB_VS: "SMLALBB.VS", |
6390 arm_SMLALBB_VC: "SMLALBB.VC", | 7747 arm_SMLALBB_VC: "SMLALBB.VC", |
6391 arm_SMLALBB_HI: "SMLALBB.HI", | 7748 arm_SMLALBB_HI: "SMLALBB.HI", |
6392 arm_SMLALBB_LS: "SMLALBB.LS", | 7749 arm_SMLALBB_LS: "SMLALBB.LS", |
6393 arm_SMLALBB_GE: "SMLALBB.GE", | 7750 arm_SMLALBB_GE: "SMLALBB.GE", |
6394 arm_SMLALBB_LT: "SMLALBB.LT", | 7751 arm_SMLALBB_LT: "SMLALBB.LT", |
6395 arm_SMLALBB_GT: "SMLALBB.GT", | 7752 arm_SMLALBB_GT: "SMLALBB.GT", |
6396 arm_SMLALBB_LE: "SMLALBB.LE", | 7753 arm_SMLALBB_LE: "SMLALBB.LE", |
6397 arm_SMLALBB: "SMLALBB", | 7754 arm_SMLALBB: "SMLALBB", |
6398 arm_SMLALBB_ZZ: "SMLALBB.ZZ", | 7755 arm_SMLALBB_ZZ: "SMLALBB.ZZ", |
6399 arm_SMLALBT_EQ: "SMLALBT.EQ", | 7756 arm_SMLALBT_EQ: "SMLALBT.EQ", |
6400 arm_SMLALBT_NE: "SMLALBT.NE", | 7757 arm_SMLALBT_NE: "SMLALBT.NE", |
6401 arm_SMLALBT_CS: "SMLALBT.CS", | 7758 arm_SMLALBT_CS: "SMLALBT.CS", |
6402 arm_SMLALBT_CC: "SMLALBT.CC", | 7759 arm_SMLALBT_CC: "SMLALBT.CC", |
6403 arm_SMLALBT_MI: "SMLALBT.MI", | 7760 arm_SMLALBT_MI: "SMLALBT.MI", |
6404 arm_SMLALBT_PL: "SMLALBT.PL", | 7761 arm_SMLALBT_PL: "SMLALBT.PL", |
6405 arm_SMLALBT_VS: "SMLALBT.VS", | 7762 arm_SMLALBT_VS: "SMLALBT.VS", |
6406 arm_SMLALBT_VC: "SMLALBT.VC", | 7763 arm_SMLALBT_VC: "SMLALBT.VC", |
6407 arm_SMLALBT_HI: "SMLALBT.HI", | 7764 arm_SMLALBT_HI: "SMLALBT.HI", |
6408 arm_SMLALBT_LS: "SMLALBT.LS", | 7765 arm_SMLALBT_LS: "SMLALBT.LS", |
6409 arm_SMLALBT_GE: "SMLALBT.GE", | 7766 arm_SMLALBT_GE: "SMLALBT.GE", |
6410 arm_SMLALBT_LT: "SMLALBT.LT", | 7767 arm_SMLALBT_LT: "SMLALBT.LT", |
6411 arm_SMLALBT_GT: "SMLALBT.GT", | 7768 arm_SMLALBT_GT: "SMLALBT.GT", |
6412 arm_SMLALBT_LE: "SMLALBT.LE", | 7769 arm_SMLALBT_LE: "SMLALBT.LE", |
6413 arm_SMLALBT: "SMLALBT", | 7770 arm_SMLALBT: "SMLALBT", |
6414 arm_SMLALBT_ZZ: "SMLALBT.ZZ", | 7771 arm_SMLALBT_ZZ: "SMLALBT.ZZ", |
6415 arm_SMLALTB_EQ: "SMLALTB.EQ", | 7772 arm_SMLALTB_EQ: "SMLALTB.EQ", |
6416 arm_SMLALTB_NE: "SMLALTB.NE", | 7773 arm_SMLALTB_NE: "SMLALTB.NE", |
6417 arm_SMLALTB_CS: "SMLALTB.CS", | 7774 arm_SMLALTB_CS: "SMLALTB.CS", |
6418 arm_SMLALTB_CC: "SMLALTB.CC", | 7775 arm_SMLALTB_CC: "SMLALTB.CC", |
6419 arm_SMLALTB_MI: "SMLALTB.MI", | 7776 arm_SMLALTB_MI: "SMLALTB.MI", |
6420 arm_SMLALTB_PL: "SMLALTB.PL", | 7777 arm_SMLALTB_PL: "SMLALTB.PL", |
6421 arm_SMLALTB_VS: "SMLALTB.VS", | 7778 arm_SMLALTB_VS: "SMLALTB.VS", |
6422 arm_SMLALTB_VC: "SMLALTB.VC", | 7779 arm_SMLALTB_VC: "SMLALTB.VC", |
6423 arm_SMLALTB_HI: "SMLALTB.HI", | 7780 arm_SMLALTB_HI: "SMLALTB.HI", |
6424 arm_SMLALTB_LS: "SMLALTB.LS", | 7781 arm_SMLALTB_LS: "SMLALTB.LS", |
6425 arm_SMLALTB_GE: "SMLALTB.GE", | 7782 arm_SMLALTB_GE: "SMLALTB.GE", |
6426 arm_SMLALTB_LT: "SMLALTB.LT", | 7783 arm_SMLALTB_LT: "SMLALTB.LT", |
6427 arm_SMLALTB_GT: "SMLALTB.GT", | 7784 arm_SMLALTB_GT: "SMLALTB.GT", |
6428 arm_SMLALTB_LE: "SMLALTB.LE", | 7785 arm_SMLALTB_LE: "SMLALTB.LE", |
6429 arm_SMLALTB: "SMLALTB", | 7786 arm_SMLALTB: "SMLALTB", |
6430 arm_SMLALTB_ZZ: "SMLALTB.ZZ", | 7787 arm_SMLALTB_ZZ: "SMLALTB.ZZ", |
6431 arm_SMLALTT_EQ: "SMLALTT.EQ", | 7788 arm_SMLALTT_EQ: "SMLALTT.EQ", |
6432 arm_SMLALTT_NE: "SMLALTT.NE", | 7789 arm_SMLALTT_NE: "SMLALTT.NE", |
6433 arm_SMLALTT_CS: "SMLALTT.CS", | 7790 arm_SMLALTT_CS: "SMLALTT.CS", |
6434 arm_SMLALTT_CC: "SMLALTT.CC", | 7791 arm_SMLALTT_CC: "SMLALTT.CC", |
6435 arm_SMLALTT_MI: "SMLALTT.MI", | 7792 arm_SMLALTT_MI: "SMLALTT.MI", |
6436 arm_SMLALTT_PL: "SMLALTT.PL", | 7793 arm_SMLALTT_PL: "SMLALTT.PL", |
6437 arm_SMLALTT_VS: "SMLALTT.VS", | 7794 arm_SMLALTT_VS: "SMLALTT.VS", |
6438 arm_SMLALTT_VC: "SMLALTT.VC", | 7795 arm_SMLALTT_VC: "SMLALTT.VC", |
6439 arm_SMLALTT_HI: "SMLALTT.HI", | 7796 arm_SMLALTT_HI: "SMLALTT.HI", |
6440 arm_SMLALTT_LS: "SMLALTT.LS", | 7797 arm_SMLALTT_LS: "SMLALTT.LS", |
6441 arm_SMLALTT_GE: "SMLALTT.GE", | 7798 arm_SMLALTT_GE: "SMLALTT.GE", |
6442 arm_SMLALTT_LT: "SMLALTT.LT", | 7799 arm_SMLALTT_LT: "SMLALTT.LT", |
6443 arm_SMLALTT_GT: "SMLALTT.GT", | 7800 arm_SMLALTT_GT: "SMLALTT.GT", |
6444 arm_SMLALTT_LE: "SMLALTT.LE", | 7801 arm_SMLALTT_LE: "SMLALTT.LE", |
6445 arm_SMLALTT: "SMLALTT", | 7802 arm_SMLALTT: "SMLALTT", |
6446 arm_SMLALTT_ZZ: "SMLALTT.ZZ", | 7803 arm_SMLALTT_ZZ: "SMLALTT.ZZ", |
6447 arm_SMLALD_EQ: "SMLALD.EQ", | 7804 arm_SMLALD_EQ: "SMLALD.EQ", |
6448 arm_SMLALD_NE: "SMLALD.NE", | 7805 arm_SMLALD_NE: "SMLALD.NE", |
6449 arm_SMLALD_CS: "SMLALD.CS", | 7806 arm_SMLALD_CS: "SMLALD.CS", |
6450 arm_SMLALD_CC: "SMLALD.CC", | 7807 arm_SMLALD_CC: "SMLALD.CC", |
6451 arm_SMLALD_MI: "SMLALD.MI", | 7808 arm_SMLALD_MI: "SMLALD.MI", |
6452 arm_SMLALD_PL: "SMLALD.PL", | 7809 arm_SMLALD_PL: "SMLALD.PL", |
6453 arm_SMLALD_VS: "SMLALD.VS", | 7810 arm_SMLALD_VS: "SMLALD.VS", |
6454 arm_SMLALD_VC: "SMLALD.VC", | 7811 arm_SMLALD_VC: "SMLALD.VC", |
6455 arm_SMLALD_HI: "SMLALD.HI", | 7812 arm_SMLALD_HI: "SMLALD.HI", |
6456 arm_SMLALD_LS: "SMLALD.LS", | 7813 arm_SMLALD_LS: "SMLALD.LS", |
6457 arm_SMLALD_GE: "SMLALD.GE", | 7814 arm_SMLALD_GE: "SMLALD.GE", |
6458 arm_SMLALD_LT: "SMLALD.LT", | 7815 arm_SMLALD_LT: "SMLALD.LT", |
6459 arm_SMLALD_GT: "SMLALD.GT", | 7816 arm_SMLALD_GT: "SMLALD.GT", |
6460 arm_SMLALD_LE: "SMLALD.LE", | 7817 arm_SMLALD_LE: "SMLALD.LE", |
6461 arm_SMLALD: "SMLALD", | 7818 arm_SMLALD: "SMLALD", |
6462 arm_SMLALD_ZZ: "SMLALD.ZZ", | 7819 arm_SMLALD_ZZ: "SMLALD.ZZ", |
6463 arm_SMLALD_X_EQ: "SMLALD.X.EQ", | 7820 arm_SMLALD_X_EQ: "SMLALD.X.EQ", |
6464 arm_SMLALD_X_NE: "SMLALD.X.NE", | 7821 arm_SMLALD_X_NE: "SMLALD.X.NE", |
6465 arm_SMLALD_X_CS: "SMLALD.X.CS", | 7822 arm_SMLALD_X_CS: "SMLALD.X.CS", |
6466 arm_SMLALD_X_CC: "SMLALD.X.CC", | 7823 arm_SMLALD_X_CC: "SMLALD.X.CC", |
6467 arm_SMLALD_X_MI: "SMLALD.X.MI", | 7824 arm_SMLALD_X_MI: "SMLALD.X.MI", |
6468 arm_SMLALD_X_PL: "SMLALD.X.PL", | 7825 arm_SMLALD_X_PL: "SMLALD.X.PL", |
6469 arm_SMLALD_X_VS: "SMLALD.X.VS", | 7826 arm_SMLALD_X_VS: "SMLALD.X.VS", |
6470 arm_SMLALD_X_VC: "SMLALD.X.VC", | 7827 arm_SMLALD_X_VC: "SMLALD.X.VC", |
6471 arm_SMLALD_X_HI: "SMLALD.X.HI", | 7828 arm_SMLALD_X_HI: "SMLALD.X.HI", |
6472 arm_SMLALD_X_LS: "SMLALD.X.LS", | 7829 arm_SMLALD_X_LS: "SMLALD.X.LS", |
6473 arm_SMLALD_X_GE: "SMLALD.X.GE", | 7830 arm_SMLALD_X_GE: "SMLALD.X.GE", |
6474 arm_SMLALD_X_LT: "SMLALD.X.LT", | 7831 arm_SMLALD_X_LT: "SMLALD.X.LT", |
6475 arm_SMLALD_X_GT: "SMLALD.X.GT", | 7832 arm_SMLALD_X_GT: "SMLALD.X.GT", |
6476 arm_SMLALD_X_LE: "SMLALD.X.LE", | 7833 arm_SMLALD_X_LE: "SMLALD.X.LE", |
6477 arm_SMLALD_X: "SMLALD.X", | 7834 arm_SMLALD_X: "SMLALD.X", |
6478 arm_SMLALD_X_ZZ: "SMLALD.X.ZZ", | 7835 arm_SMLALD_X_ZZ: "SMLALD.X.ZZ", |
6479 arm_SMLAWB_EQ: "SMLAWB.EQ", | 7836 arm_SMLAWB_EQ: "SMLAWB.EQ", |
6480 arm_SMLAWB_NE: "SMLAWB.NE", | 7837 arm_SMLAWB_NE: "SMLAWB.NE", |
6481 arm_SMLAWB_CS: "SMLAWB.CS", | 7838 arm_SMLAWB_CS: "SMLAWB.CS", |
6482 arm_SMLAWB_CC: "SMLAWB.CC", | 7839 arm_SMLAWB_CC: "SMLAWB.CC", |
6483 arm_SMLAWB_MI: "SMLAWB.MI", | 7840 arm_SMLAWB_MI: "SMLAWB.MI", |
6484 arm_SMLAWB_PL: "SMLAWB.PL", | 7841 arm_SMLAWB_PL: "SMLAWB.PL", |
6485 arm_SMLAWB_VS: "SMLAWB.VS", | 7842 arm_SMLAWB_VS: "SMLAWB.VS", |
6486 arm_SMLAWB_VC: "SMLAWB.VC", | 7843 arm_SMLAWB_VC: "SMLAWB.VC", |
6487 arm_SMLAWB_HI: "SMLAWB.HI", | 7844 arm_SMLAWB_HI: "SMLAWB.HI", |
6488 arm_SMLAWB_LS: "SMLAWB.LS", | 7845 arm_SMLAWB_LS: "SMLAWB.LS", |
6489 arm_SMLAWB_GE: "SMLAWB.GE", | 7846 arm_SMLAWB_GE: "SMLAWB.GE", |
6490 arm_SMLAWB_LT: "SMLAWB.LT", | 7847 arm_SMLAWB_LT: "SMLAWB.LT", |
6491 arm_SMLAWB_GT: "SMLAWB.GT", | 7848 arm_SMLAWB_GT: "SMLAWB.GT", |
6492 arm_SMLAWB_LE: "SMLAWB.LE", | 7849 arm_SMLAWB_LE: "SMLAWB.LE", |
6493 arm_SMLAWB: "SMLAWB", | 7850 arm_SMLAWB: "SMLAWB", |
6494 arm_SMLAWB_ZZ: "SMLAWB.ZZ", | 7851 arm_SMLAWB_ZZ: "SMLAWB.ZZ", |
6495 arm_SMLAWT_EQ: "SMLAWT.EQ", | 7852 arm_SMLAWT_EQ: "SMLAWT.EQ", |
6496 arm_SMLAWT_NE: "SMLAWT.NE", | 7853 arm_SMLAWT_NE: "SMLAWT.NE", |
6497 arm_SMLAWT_CS: "SMLAWT.CS", | 7854 arm_SMLAWT_CS: "SMLAWT.CS", |
6498 arm_SMLAWT_CC: "SMLAWT.CC", | 7855 arm_SMLAWT_CC: "SMLAWT.CC", |
6499 arm_SMLAWT_MI: "SMLAWT.MI", | 7856 arm_SMLAWT_MI: "SMLAWT.MI", |
6500 arm_SMLAWT_PL: "SMLAWT.PL", | 7857 arm_SMLAWT_PL: "SMLAWT.PL", |
6501 arm_SMLAWT_VS: "SMLAWT.VS", | 7858 arm_SMLAWT_VS: "SMLAWT.VS", |
6502 arm_SMLAWT_VC: "SMLAWT.VC", | 7859 arm_SMLAWT_VC: "SMLAWT.VC", |
6503 arm_SMLAWT_HI: "SMLAWT.HI", | 7860 arm_SMLAWT_HI: "SMLAWT.HI", |
6504 arm_SMLAWT_LS: "SMLAWT.LS", | 7861 arm_SMLAWT_LS: "SMLAWT.LS", |
6505 arm_SMLAWT_GE: "SMLAWT.GE", | 7862 arm_SMLAWT_GE: "SMLAWT.GE", |
6506 arm_SMLAWT_LT: "SMLAWT.LT", | 7863 arm_SMLAWT_LT: "SMLAWT.LT", |
6507 arm_SMLAWT_GT: "SMLAWT.GT", | 7864 arm_SMLAWT_GT: "SMLAWT.GT", |
6508 arm_SMLAWT_LE: "SMLAWT.LE", | 7865 arm_SMLAWT_LE: "SMLAWT.LE", |
6509 arm_SMLAWT: "SMLAWT", | 7866 arm_SMLAWT: "SMLAWT", |
6510 arm_SMLAWT_ZZ: "SMLAWT.ZZ", | 7867 arm_SMLAWT_ZZ: "SMLAWT.ZZ", |
6511 arm_SMLSD_EQ: "SMLSD.EQ", | 7868 arm_SMLSD_EQ: "SMLSD.EQ", |
6512 arm_SMLSD_NE: "SMLSD.NE", | 7869 arm_SMLSD_NE: "SMLSD.NE", |
6513 arm_SMLSD_CS: "SMLSD.CS", | 7870 arm_SMLSD_CS: "SMLSD.CS", |
6514 arm_SMLSD_CC: "SMLSD.CC", | 7871 arm_SMLSD_CC: "SMLSD.CC", |
6515 arm_SMLSD_MI: "SMLSD.MI", | 7872 arm_SMLSD_MI: "SMLSD.MI", |
6516 arm_SMLSD_PL: "SMLSD.PL", | 7873 arm_SMLSD_PL: "SMLSD.PL", |
6517 arm_SMLSD_VS: "SMLSD.VS", | 7874 arm_SMLSD_VS: "SMLSD.VS", |
6518 arm_SMLSD_VC: "SMLSD.VC", | 7875 arm_SMLSD_VC: "SMLSD.VC", |
6519 arm_SMLSD_HI: "SMLSD.HI", | 7876 arm_SMLSD_HI: "SMLSD.HI", |
6520 arm_SMLSD_LS: "SMLSD.LS", | 7877 arm_SMLSD_LS: "SMLSD.LS", |
6521 arm_SMLSD_GE: "SMLSD.GE", | 7878 arm_SMLSD_GE: "SMLSD.GE", |
6522 arm_SMLSD_LT: "SMLSD.LT", | 7879 arm_SMLSD_LT: "SMLSD.LT", |
6523 arm_SMLSD_GT: "SMLSD.GT", | 7880 arm_SMLSD_GT: "SMLSD.GT", |
6524 arm_SMLSD_LE: "SMLSD.LE", | 7881 arm_SMLSD_LE: "SMLSD.LE", |
6525 arm_SMLSD: "SMLSD", | 7882 arm_SMLSD: "SMLSD", |
6526 arm_SMLSD_ZZ: "SMLSD.ZZ", | 7883 arm_SMLSD_ZZ: "SMLSD.ZZ", |
6527 arm_SMLSD_X_EQ: "SMLSD.X.EQ", | 7884 arm_SMLSD_X_EQ: "SMLSD.X.EQ", |
6528 arm_SMLSD_X_NE: "SMLSD.X.NE", | 7885 arm_SMLSD_X_NE: "SMLSD.X.NE", |
6529 arm_SMLSD_X_CS: "SMLSD.X.CS", | 7886 arm_SMLSD_X_CS: "SMLSD.X.CS", |
6530 arm_SMLSD_X_CC: "SMLSD.X.CC", | 7887 arm_SMLSD_X_CC: "SMLSD.X.CC", |
6531 arm_SMLSD_X_MI: "SMLSD.X.MI", | 7888 arm_SMLSD_X_MI: "SMLSD.X.MI", |
6532 arm_SMLSD_X_PL: "SMLSD.X.PL", | 7889 arm_SMLSD_X_PL: "SMLSD.X.PL", |
6533 arm_SMLSD_X_VS: "SMLSD.X.VS", | 7890 arm_SMLSD_X_VS: "SMLSD.X.VS", |
6534 arm_SMLSD_X_VC: "SMLSD.X.VC", | 7891 arm_SMLSD_X_VC: "SMLSD.X.VC", |
6535 arm_SMLSD_X_HI: "SMLSD.X.HI", | 7892 arm_SMLSD_X_HI: "SMLSD.X.HI", |
6536 arm_SMLSD_X_LS: "SMLSD.X.LS", | 7893 arm_SMLSD_X_LS: "SMLSD.X.LS", |
6537 arm_SMLSD_X_GE: "SMLSD.X.GE", | 7894 arm_SMLSD_X_GE: "SMLSD.X.GE", |
6538 arm_SMLSD_X_LT: "SMLSD.X.LT", | 7895 arm_SMLSD_X_LT: "SMLSD.X.LT", |
6539 arm_SMLSD_X_GT: "SMLSD.X.GT", | 7896 arm_SMLSD_X_GT: "SMLSD.X.GT", |
6540 arm_SMLSD_X_LE: "SMLSD.X.LE", | 7897 arm_SMLSD_X_LE: "SMLSD.X.LE", |
6541 arm_SMLSD_X: "SMLSD.X", | 7898 arm_SMLSD_X: "SMLSD.X", |
6542 arm_SMLSD_X_ZZ: "SMLSD.X.ZZ", | 7899 arm_SMLSD_X_ZZ: "SMLSD.X.ZZ", |
6543 arm_SMLSLD_EQ: "SMLSLD.EQ", | 7900 arm_SMLSLD_EQ: "SMLSLD.EQ", |
6544 arm_SMLSLD_NE: "SMLSLD.NE", | 7901 arm_SMLSLD_NE: "SMLSLD.NE", |
6545 arm_SMLSLD_CS: "SMLSLD.CS", | 7902 arm_SMLSLD_CS: "SMLSLD.CS", |
6546 arm_SMLSLD_CC: "SMLSLD.CC", | 7903 arm_SMLSLD_CC: "SMLSLD.CC", |
6547 arm_SMLSLD_MI: "SMLSLD.MI", | 7904 arm_SMLSLD_MI: "SMLSLD.MI", |
6548 arm_SMLSLD_PL: "SMLSLD.PL", | 7905 arm_SMLSLD_PL: "SMLSLD.PL", |
6549 arm_SMLSLD_VS: "SMLSLD.VS", | 7906 arm_SMLSLD_VS: "SMLSLD.VS", |
6550 arm_SMLSLD_VC: "SMLSLD.VC", | 7907 arm_SMLSLD_VC: "SMLSLD.VC", |
6551 arm_SMLSLD_HI: "SMLSLD.HI", | 7908 arm_SMLSLD_HI: "SMLSLD.HI", |
6552 arm_SMLSLD_LS: "SMLSLD.LS", | 7909 arm_SMLSLD_LS: "SMLSLD.LS", |
6553 arm_SMLSLD_GE: "SMLSLD.GE", | 7910 arm_SMLSLD_GE: "SMLSLD.GE", |
6554 arm_SMLSLD_LT: "SMLSLD.LT", | 7911 arm_SMLSLD_LT: "SMLSLD.LT", |
6555 arm_SMLSLD_GT: "SMLSLD.GT", | 7912 arm_SMLSLD_GT: "SMLSLD.GT", |
6556 arm_SMLSLD_LE: "SMLSLD.LE", | 7913 arm_SMLSLD_LE: "SMLSLD.LE", |
6557 arm_SMLSLD: "SMLSLD", | 7914 arm_SMLSLD: "SMLSLD", |
6558 arm_SMLSLD_ZZ: "SMLSLD.ZZ", | 7915 arm_SMLSLD_ZZ: "SMLSLD.ZZ", |
6559 arm_SMLSLD_X_EQ: "SMLSLD.X.EQ", | 7916 arm_SMLSLD_X_EQ: "SMLSLD.X.EQ", |
6560 arm_SMLSLD_X_NE: "SMLSLD.X.NE", | 7917 arm_SMLSLD_X_NE: "SMLSLD.X.NE", |
6561 arm_SMLSLD_X_CS: "SMLSLD.X.CS", | 7918 arm_SMLSLD_X_CS: "SMLSLD.X.CS", |
6562 arm_SMLSLD_X_CC: "SMLSLD.X.CC", | 7919 arm_SMLSLD_X_CC: "SMLSLD.X.CC", |
6563 arm_SMLSLD_X_MI: "SMLSLD.X.MI", | 7920 arm_SMLSLD_X_MI: "SMLSLD.X.MI", |
6564 arm_SMLSLD_X_PL: "SMLSLD.X.PL", | 7921 arm_SMLSLD_X_PL: "SMLSLD.X.PL", |
6565 arm_SMLSLD_X_VS: "SMLSLD.X.VS", | 7922 arm_SMLSLD_X_VS: "SMLSLD.X.VS", |
6566 arm_SMLSLD_X_VC: "SMLSLD.X.VC", | 7923 arm_SMLSLD_X_VC: "SMLSLD.X.VC", |
6567 arm_SMLSLD_X_HI: "SMLSLD.X.HI", | 7924 arm_SMLSLD_X_HI: "SMLSLD.X.HI", |
6568 arm_SMLSLD_X_LS: "SMLSLD.X.LS", | 7925 arm_SMLSLD_X_LS: "SMLSLD.X.LS", |
6569 arm_SMLSLD_X_GE: "SMLSLD.X.GE", | 7926 arm_SMLSLD_X_GE: "SMLSLD.X.GE", |
6570 arm_SMLSLD_X_LT: "SMLSLD.X.LT", | 7927 arm_SMLSLD_X_LT: "SMLSLD.X.LT", |
6571 arm_SMLSLD_X_GT: "SMLSLD.X.GT", | 7928 arm_SMLSLD_X_GT: "SMLSLD.X.GT", |
6572 arm_SMLSLD_X_LE: "SMLSLD.X.LE", | 7929 arm_SMLSLD_X_LE: "SMLSLD.X.LE", |
6573 arm_SMLSLD_X: "SMLSLD.X", | 7930 arm_SMLSLD_X: "SMLSLD.X", |
6574 arm_SMLSLD_X_ZZ: "SMLSLD.X.ZZ", | 7931 arm_SMLSLD_X_ZZ: "SMLSLD.X.ZZ", |
6575 arm_SMMLA_EQ: "SMMLA.EQ", | 7932 arm_SMMLA_EQ: "SMMLA.EQ", |
6576 arm_SMMLA_NE: "SMMLA.NE", | 7933 arm_SMMLA_NE: "SMMLA.NE", |
6577 arm_SMMLA_CS: "SMMLA.CS", | 7934 arm_SMMLA_CS: "SMMLA.CS", |
6578 arm_SMMLA_CC: "SMMLA.CC", | 7935 arm_SMMLA_CC: "SMMLA.CC", |
6579 arm_SMMLA_MI: "SMMLA.MI", | 7936 arm_SMMLA_MI: "SMMLA.MI", |
6580 arm_SMMLA_PL: "SMMLA.PL", | 7937 arm_SMMLA_PL: "SMMLA.PL", |
6581 arm_SMMLA_VS: "SMMLA.VS", | 7938 arm_SMMLA_VS: "SMMLA.VS", |
6582 arm_SMMLA_VC: "SMMLA.VC", | 7939 arm_SMMLA_VC: "SMMLA.VC", |
6583 arm_SMMLA_HI: "SMMLA.HI", | 7940 arm_SMMLA_HI: "SMMLA.HI", |
6584 arm_SMMLA_LS: "SMMLA.LS", | 7941 arm_SMMLA_LS: "SMMLA.LS", |
6585 arm_SMMLA_GE: "SMMLA.GE", | 7942 arm_SMMLA_GE: "SMMLA.GE", |
6586 arm_SMMLA_LT: "SMMLA.LT", | 7943 arm_SMMLA_LT: "SMMLA.LT", |
6587 arm_SMMLA_GT: "SMMLA.GT", | 7944 arm_SMMLA_GT: "SMMLA.GT", |
6588 arm_SMMLA_LE: "SMMLA.LE", | 7945 arm_SMMLA_LE: "SMMLA.LE", |
6589 arm_SMMLA: "SMMLA", | 7946 arm_SMMLA: "SMMLA", |
6590 arm_SMMLA_ZZ: "SMMLA.ZZ", | 7947 arm_SMMLA_ZZ: "SMMLA.ZZ", |
6591 arm_SMMLA_R_EQ: "SMMLA.R.EQ", | 7948 arm_SMMLA_R_EQ: "SMMLA.R.EQ", |
6592 arm_SMMLA_R_NE: "SMMLA.R.NE", | 7949 arm_SMMLA_R_NE: "SMMLA.R.NE", |
6593 arm_SMMLA_R_CS: "SMMLA.R.CS", | 7950 arm_SMMLA_R_CS: "SMMLA.R.CS", |
6594 arm_SMMLA_R_CC: "SMMLA.R.CC", | 7951 arm_SMMLA_R_CC: "SMMLA.R.CC", |
6595 arm_SMMLA_R_MI: "SMMLA.R.MI", | 7952 arm_SMMLA_R_MI: "SMMLA.R.MI", |
6596 arm_SMMLA_R_PL: "SMMLA.R.PL", | 7953 arm_SMMLA_R_PL: "SMMLA.R.PL", |
6597 arm_SMMLA_R_VS: "SMMLA.R.VS", | 7954 arm_SMMLA_R_VS: "SMMLA.R.VS", |
6598 arm_SMMLA_R_VC: "SMMLA.R.VC", | 7955 arm_SMMLA_R_VC: "SMMLA.R.VC", |
6599 arm_SMMLA_R_HI: "SMMLA.R.HI", | 7956 arm_SMMLA_R_HI: "SMMLA.R.HI", |
6600 arm_SMMLA_R_LS: "SMMLA.R.LS", | 7957 arm_SMMLA_R_LS: "SMMLA.R.LS", |
6601 arm_SMMLA_R_GE: "SMMLA.R.GE", | 7958 arm_SMMLA_R_GE: "SMMLA.R.GE", |
6602 arm_SMMLA_R_LT: "SMMLA.R.LT", | 7959 arm_SMMLA_R_LT: "SMMLA.R.LT", |
6603 arm_SMMLA_R_GT: "SMMLA.R.GT", | 7960 arm_SMMLA_R_GT: "SMMLA.R.GT", |
6604 arm_SMMLA_R_LE: "SMMLA.R.LE", | 7961 arm_SMMLA_R_LE: "SMMLA.R.LE", |
6605 arm_SMMLA_R: "SMMLA.R", | 7962 arm_SMMLA_R: "SMMLA.R", |
6606 arm_SMMLA_R_ZZ: "SMMLA.R.ZZ", | 7963 arm_SMMLA_R_ZZ: "SMMLA.R.ZZ", |
6607 arm_SMMLS_EQ: "SMMLS.EQ", | 7964 arm_SMMLS_EQ: "SMMLS.EQ", |
6608 arm_SMMLS_NE: "SMMLS.NE", | 7965 arm_SMMLS_NE: "SMMLS.NE", |
6609 arm_SMMLS_CS: "SMMLS.CS", | 7966 arm_SMMLS_CS: "SMMLS.CS", |
6610 arm_SMMLS_CC: "SMMLS.CC", | 7967 arm_SMMLS_CC: "SMMLS.CC", |
6611 arm_SMMLS_MI: "SMMLS.MI", | 7968 arm_SMMLS_MI: "SMMLS.MI", |
6612 arm_SMMLS_PL: "SMMLS.PL", | 7969 arm_SMMLS_PL: "SMMLS.PL", |
6613 arm_SMMLS_VS: "SMMLS.VS", | 7970 arm_SMMLS_VS: "SMMLS.VS", |
6614 arm_SMMLS_VC: "SMMLS.VC", | 7971 arm_SMMLS_VC: "SMMLS.VC", |
6615 arm_SMMLS_HI: "SMMLS.HI", | 7972 arm_SMMLS_HI: "SMMLS.HI", |
6616 arm_SMMLS_LS: "SMMLS.LS", | 7973 arm_SMMLS_LS: "SMMLS.LS", |
6617 arm_SMMLS_GE: "SMMLS.GE", | 7974 arm_SMMLS_GE: "SMMLS.GE", |
6618 arm_SMMLS_LT: "SMMLS.LT", | 7975 arm_SMMLS_LT: "SMMLS.LT", |
6619 arm_SMMLS_GT: "SMMLS.GT", | 7976 arm_SMMLS_GT: "SMMLS.GT", |
6620 arm_SMMLS_LE: "SMMLS.LE", | 7977 arm_SMMLS_LE: "SMMLS.LE", |
6621 arm_SMMLS: "SMMLS", | 7978 arm_SMMLS: "SMMLS", |
6622 arm_SMMLS_ZZ: "SMMLS.ZZ", | 7979 arm_SMMLS_ZZ: "SMMLS.ZZ", |
6623 arm_SMMLS_R_EQ: "SMMLS.R.EQ", | 7980 arm_SMMLS_R_EQ: "SMMLS.R.EQ", |
6624 arm_SMMLS_R_NE: "SMMLS.R.NE", | 7981 arm_SMMLS_R_NE: "SMMLS.R.NE", |
6625 arm_SMMLS_R_CS: "SMMLS.R.CS", | 7982 arm_SMMLS_R_CS: "SMMLS.R.CS", |
6626 arm_SMMLS_R_CC: "SMMLS.R.CC", | 7983 arm_SMMLS_R_CC: "SMMLS.R.CC", |
6627 arm_SMMLS_R_MI: "SMMLS.R.MI", | 7984 arm_SMMLS_R_MI: "SMMLS.R.MI", |
6628 arm_SMMLS_R_PL: "SMMLS.R.PL", | 7985 arm_SMMLS_R_PL: "SMMLS.R.PL", |
6629 arm_SMMLS_R_VS: "SMMLS.R.VS", | 7986 arm_SMMLS_R_VS: "SMMLS.R.VS", |
6630 arm_SMMLS_R_VC: "SMMLS.R.VC", | 7987 arm_SMMLS_R_VC: "SMMLS.R.VC", |
6631 arm_SMMLS_R_HI: "SMMLS.R.HI", | 7988 arm_SMMLS_R_HI: "SMMLS.R.HI", |
6632 arm_SMMLS_R_LS: "SMMLS.R.LS", | 7989 arm_SMMLS_R_LS: "SMMLS.R.LS", |
6633 arm_SMMLS_R_GE: "SMMLS.R.GE", | 7990 arm_SMMLS_R_GE: "SMMLS.R.GE", |
6634 arm_SMMLS_R_LT: "SMMLS.R.LT", | 7991 arm_SMMLS_R_LT: "SMMLS.R.LT", |
6635 arm_SMMLS_R_GT: "SMMLS.R.GT", | 7992 arm_SMMLS_R_GT: "SMMLS.R.GT", |
6636 arm_SMMLS_R_LE: "SMMLS.R.LE", | 7993 arm_SMMLS_R_LE: "SMMLS.R.LE", |
6637 arm_SMMLS_R: "SMMLS.R", | 7994 arm_SMMLS_R: "SMMLS.R", |
6638 arm_SMMLS_R_ZZ: "SMMLS.R.ZZ", | 7995 arm_SMMLS_R_ZZ: "SMMLS.R.ZZ", |
6639 arm_SMMUL_EQ: "SMMUL.EQ", | 7996 arm_SMMUL_EQ: "SMMUL.EQ", |
6640 arm_SMMUL_NE: "SMMUL.NE", | 7997 arm_SMMUL_NE: "SMMUL.NE", |
6641 arm_SMMUL_CS: "SMMUL.CS", | 7998 arm_SMMUL_CS: "SMMUL.CS", |
6642 arm_SMMUL_CC: "SMMUL.CC", | 7999 arm_SMMUL_CC: "SMMUL.CC", |
6643 arm_SMMUL_MI: "SMMUL.MI", | 8000 arm_SMMUL_MI: "SMMUL.MI", |
6644 arm_SMMUL_PL: "SMMUL.PL", | 8001 arm_SMMUL_PL: "SMMUL.PL", |
6645 arm_SMMUL_VS: "SMMUL.VS", | 8002 arm_SMMUL_VS: "SMMUL.VS", |
6646 arm_SMMUL_VC: "SMMUL.VC", | 8003 arm_SMMUL_VC: "SMMUL.VC", |
6647 arm_SMMUL_HI: "SMMUL.HI", | 8004 arm_SMMUL_HI: "SMMUL.HI", |
6648 arm_SMMUL_LS: "SMMUL.LS", | 8005 arm_SMMUL_LS: "SMMUL.LS", |
6649 arm_SMMUL_GE: "SMMUL.GE", | 8006 arm_SMMUL_GE: "SMMUL.GE", |
6650 arm_SMMUL_LT: "SMMUL.LT", | 8007 arm_SMMUL_LT: "SMMUL.LT", |
6651 arm_SMMUL_GT: "SMMUL.GT", | 8008 arm_SMMUL_GT: "SMMUL.GT", |
6652 arm_SMMUL_LE: "SMMUL.LE", | 8009 arm_SMMUL_LE: "SMMUL.LE", |
6653 arm_SMMUL: "SMMUL", | 8010 arm_SMMUL: "SMMUL", |
6654 arm_SMMUL_ZZ: "SMMUL.ZZ", | 8011 arm_SMMUL_ZZ: "SMMUL.ZZ", |
6655 arm_SMMUL_R_EQ: "SMMUL.R.EQ", | 8012 arm_SMMUL_R_EQ: "SMMUL.R.EQ", |
6656 arm_SMMUL_R_NE: "SMMUL.R.NE", | 8013 arm_SMMUL_R_NE: "SMMUL.R.NE", |
6657 arm_SMMUL_R_CS: "SMMUL.R.CS", | 8014 arm_SMMUL_R_CS: "SMMUL.R.CS", |
6658 arm_SMMUL_R_CC: "SMMUL.R.CC", | 8015 arm_SMMUL_R_CC: "SMMUL.R.CC", |
6659 arm_SMMUL_R_MI: "SMMUL.R.MI", | 8016 arm_SMMUL_R_MI: "SMMUL.R.MI", |
6660 arm_SMMUL_R_PL: "SMMUL.R.PL", | 8017 arm_SMMUL_R_PL: "SMMUL.R.PL", |
6661 arm_SMMUL_R_VS: "SMMUL.R.VS", | 8018 arm_SMMUL_R_VS: "SMMUL.R.VS", |
6662 arm_SMMUL_R_VC: "SMMUL.R.VC", | 8019 arm_SMMUL_R_VC: "SMMUL.R.VC", |
6663 arm_SMMUL_R_HI: "SMMUL.R.HI", | 8020 arm_SMMUL_R_HI: "SMMUL.R.HI", |
6664 arm_SMMUL_R_LS: "SMMUL.R.LS", | 8021 arm_SMMUL_R_LS: "SMMUL.R.LS", |
6665 arm_SMMUL_R_GE: "SMMUL.R.GE", | 8022 arm_SMMUL_R_GE: "SMMUL.R.GE", |
6666 arm_SMMUL_R_LT: "SMMUL.R.LT", | 8023 arm_SMMUL_R_LT: "SMMUL.R.LT", |
6667 arm_SMMUL_R_GT: "SMMUL.R.GT", | 8024 arm_SMMUL_R_GT: "SMMUL.R.GT", |
6668 arm_SMMUL_R_LE: "SMMUL.R.LE", | 8025 arm_SMMUL_R_LE: "SMMUL.R.LE", |
6669 arm_SMMUL_R: "SMMUL.R", | 8026 arm_SMMUL_R: "SMMUL.R", |
6670 arm_SMMUL_R_ZZ: "SMMUL.R.ZZ", | 8027 arm_SMMUL_R_ZZ: "SMMUL.R.ZZ", |
6671 arm_SMUAD_EQ: "SMUAD.EQ", | 8028 arm_SMUAD_EQ: "SMUAD.EQ", |
6672 arm_SMUAD_NE: "SMUAD.NE", | 8029 arm_SMUAD_NE: "SMUAD.NE", |
6673 arm_SMUAD_CS: "SMUAD.CS", | 8030 arm_SMUAD_CS: "SMUAD.CS", |
6674 arm_SMUAD_CC: "SMUAD.CC", | 8031 arm_SMUAD_CC: "SMUAD.CC", |
6675 arm_SMUAD_MI: "SMUAD.MI", | 8032 arm_SMUAD_MI: "SMUAD.MI", |
6676 arm_SMUAD_PL: "SMUAD.PL", | 8033 arm_SMUAD_PL: "SMUAD.PL", |
6677 arm_SMUAD_VS: "SMUAD.VS", | 8034 arm_SMUAD_VS: "SMUAD.VS", |
6678 arm_SMUAD_VC: "SMUAD.VC", | 8035 arm_SMUAD_VC: "SMUAD.VC", |
6679 arm_SMUAD_HI: "SMUAD.HI", | 8036 arm_SMUAD_HI: "SMUAD.HI", |
6680 arm_SMUAD_LS: "SMUAD.LS", | 8037 arm_SMUAD_LS: "SMUAD.LS", |
6681 arm_SMUAD_GE: "SMUAD.GE", | 8038 arm_SMUAD_GE: "SMUAD.GE", |
6682 arm_SMUAD_LT: "SMUAD.LT", | 8039 arm_SMUAD_LT: "SMUAD.LT", |
6683 arm_SMUAD_GT: "SMUAD.GT", | 8040 arm_SMUAD_GT: "SMUAD.GT", |
6684 arm_SMUAD_LE: "SMUAD.LE", | 8041 arm_SMUAD_LE: "SMUAD.LE", |
6685 arm_SMUAD: "SMUAD", | 8042 arm_SMUAD: "SMUAD", |
6686 arm_SMUAD_ZZ: "SMUAD.ZZ", | 8043 arm_SMUAD_ZZ: "SMUAD.ZZ", |
6687 arm_SMUAD_X_EQ: "SMUAD.X.EQ", | 8044 arm_SMUAD_X_EQ: "SMUAD.X.EQ", |
6688 arm_SMUAD_X_NE: "SMUAD.X.NE", | 8045 arm_SMUAD_X_NE: "SMUAD.X.NE", |
6689 arm_SMUAD_X_CS: "SMUAD.X.CS", | 8046 arm_SMUAD_X_CS: "SMUAD.X.CS", |
6690 arm_SMUAD_X_CC: "SMUAD.X.CC", | 8047 arm_SMUAD_X_CC: "SMUAD.X.CC", |
6691 arm_SMUAD_X_MI: "SMUAD.X.MI", | 8048 arm_SMUAD_X_MI: "SMUAD.X.MI", |
6692 arm_SMUAD_X_PL: "SMUAD.X.PL", | 8049 arm_SMUAD_X_PL: "SMUAD.X.PL", |
6693 arm_SMUAD_X_VS: "SMUAD.X.VS", | 8050 arm_SMUAD_X_VS: "SMUAD.X.VS", |
6694 arm_SMUAD_X_VC: "SMUAD.X.VC", | 8051 arm_SMUAD_X_VC: "SMUAD.X.VC", |
6695 arm_SMUAD_X_HI: "SMUAD.X.HI", | 8052 arm_SMUAD_X_HI: "SMUAD.X.HI", |
6696 arm_SMUAD_X_LS: "SMUAD.X.LS", | 8053 arm_SMUAD_X_LS: "SMUAD.X.LS", |
6697 arm_SMUAD_X_GE: "SMUAD.X.GE", | 8054 arm_SMUAD_X_GE: "SMUAD.X.GE", |
6698 arm_SMUAD_X_LT: "SMUAD.X.LT", | 8055 arm_SMUAD_X_LT: "SMUAD.X.LT", |
6699 arm_SMUAD_X_GT: "SMUAD.X.GT", | 8056 arm_SMUAD_X_GT: "SMUAD.X.GT", |
6700 arm_SMUAD_X_LE: "SMUAD.X.LE", | 8057 arm_SMUAD_X_LE: "SMUAD.X.LE", |
6701 arm_SMUAD_X: "SMUAD.X", | 8058 arm_SMUAD_X: "SMUAD.X", |
6702 arm_SMUAD_X_ZZ: "SMUAD.X.ZZ", | 8059 arm_SMUAD_X_ZZ: "SMUAD.X.ZZ", |
6703 arm_SMULBB_EQ: "SMULBB.EQ", | 8060 arm_SMULBB_EQ: "SMULBB.EQ", |
6704 arm_SMULBB_NE: "SMULBB.NE", | 8061 arm_SMULBB_NE: "SMULBB.NE", |
6705 arm_SMULBB_CS: "SMULBB.CS", | 8062 arm_SMULBB_CS: "SMULBB.CS", |
6706 arm_SMULBB_CC: "SMULBB.CC", | 8063 arm_SMULBB_CC: "SMULBB.CC", |
6707 arm_SMULBB_MI: "SMULBB.MI", | 8064 arm_SMULBB_MI: "SMULBB.MI", |
6708 arm_SMULBB_PL: "SMULBB.PL", | 8065 arm_SMULBB_PL: "SMULBB.PL", |
6709 arm_SMULBB_VS: "SMULBB.VS", | 8066 arm_SMULBB_VS: "SMULBB.VS", |
6710 arm_SMULBB_VC: "SMULBB.VC", | 8067 arm_SMULBB_VC: "SMULBB.VC", |
6711 arm_SMULBB_HI: "SMULBB.HI", | 8068 arm_SMULBB_HI: "SMULBB.HI", |
6712 arm_SMULBB_LS: "SMULBB.LS", | 8069 arm_SMULBB_LS: "SMULBB.LS", |
6713 arm_SMULBB_GE: "SMULBB.GE", | 8070 arm_SMULBB_GE: "SMULBB.GE", |
6714 arm_SMULBB_LT: "SMULBB.LT", | 8071 arm_SMULBB_LT: "SMULBB.LT", |
6715 arm_SMULBB_GT: "SMULBB.GT", | 8072 arm_SMULBB_GT: "SMULBB.GT", |
6716 arm_SMULBB_LE: "SMULBB.LE", | 8073 arm_SMULBB_LE: "SMULBB.LE", |
6717 arm_SMULBB: "SMULBB", | 8074 arm_SMULBB: "SMULBB", |
6718 arm_SMULBB_ZZ: "SMULBB.ZZ", | 8075 arm_SMULBB_ZZ: "SMULBB.ZZ", |
6719 arm_SMULBT_EQ: "SMULBT.EQ", | 8076 arm_SMULBT_EQ: "SMULBT.EQ", |
6720 arm_SMULBT_NE: "SMULBT.NE", | 8077 arm_SMULBT_NE: "SMULBT.NE", |
6721 arm_SMULBT_CS: "SMULBT.CS", | 8078 arm_SMULBT_CS: "SMULBT.CS", |
6722 arm_SMULBT_CC: "SMULBT.CC", | 8079 arm_SMULBT_CC: "SMULBT.CC", |
6723 arm_SMULBT_MI: "SMULBT.MI", | 8080 arm_SMULBT_MI: "SMULBT.MI", |
6724 arm_SMULBT_PL: "SMULBT.PL", | 8081 arm_SMULBT_PL: "SMULBT.PL", |
6725 arm_SMULBT_VS: "SMULBT.VS", | 8082 arm_SMULBT_VS: "SMULBT.VS", |
6726 arm_SMULBT_VC: "SMULBT.VC", | 8083 arm_SMULBT_VC: "SMULBT.VC", |
6727 arm_SMULBT_HI: "SMULBT.HI", | 8084 arm_SMULBT_HI: "SMULBT.HI", |
6728 arm_SMULBT_LS: "SMULBT.LS", | 8085 arm_SMULBT_LS: "SMULBT.LS", |
6729 arm_SMULBT_GE: "SMULBT.GE", | 8086 arm_SMULBT_GE: "SMULBT.GE", |
6730 arm_SMULBT_LT: "SMULBT.LT", | 8087 arm_SMULBT_LT: "SMULBT.LT", |
6731 arm_SMULBT_GT: "SMULBT.GT", | 8088 arm_SMULBT_GT: "SMULBT.GT", |
6732 arm_SMULBT_LE: "SMULBT.LE", | 8089 arm_SMULBT_LE: "SMULBT.LE", |
6733 arm_SMULBT: "SMULBT", | 8090 arm_SMULBT: "SMULBT", |
6734 arm_SMULBT_ZZ: "SMULBT.ZZ", | 8091 arm_SMULBT_ZZ: "SMULBT.ZZ", |
6735 arm_SMULTB_EQ: "SMULTB.EQ", | 8092 arm_SMULTB_EQ: "SMULTB.EQ", |
6736 arm_SMULTB_NE: "SMULTB.NE", | 8093 arm_SMULTB_NE: "SMULTB.NE", |
6737 arm_SMULTB_CS: "SMULTB.CS", | 8094 arm_SMULTB_CS: "SMULTB.CS", |
6738 arm_SMULTB_CC: "SMULTB.CC", | 8095 arm_SMULTB_CC: "SMULTB.CC", |
6739 arm_SMULTB_MI: "SMULTB.MI", | 8096 arm_SMULTB_MI: "SMULTB.MI", |
6740 arm_SMULTB_PL: "SMULTB.PL", | 8097 arm_SMULTB_PL: "SMULTB.PL", |
6741 arm_SMULTB_VS: "SMULTB.VS", | 8098 arm_SMULTB_VS: "SMULTB.VS", |
6742 arm_SMULTB_VC: "SMULTB.VC", | 8099 arm_SMULTB_VC: "SMULTB.VC", |
6743 arm_SMULTB_HI: "SMULTB.HI", | 8100 arm_SMULTB_HI: "SMULTB.HI", |
6744 arm_SMULTB_LS: "SMULTB.LS", | 8101 arm_SMULTB_LS: "SMULTB.LS", |
6745 arm_SMULTB_GE: "SMULTB.GE", | 8102 arm_SMULTB_GE: "SMULTB.GE", |
6746 arm_SMULTB_LT: "SMULTB.LT", | 8103 arm_SMULTB_LT: "SMULTB.LT", |
6747 arm_SMULTB_GT: "SMULTB.GT", | 8104 arm_SMULTB_GT: "SMULTB.GT", |
6748 arm_SMULTB_LE: "SMULTB.LE", | 8105 arm_SMULTB_LE: "SMULTB.LE", |
6749 arm_SMULTB: "SMULTB", | 8106 arm_SMULTB: "SMULTB", |
6750 arm_SMULTB_ZZ: "SMULTB.ZZ", | 8107 arm_SMULTB_ZZ: "SMULTB.ZZ", |
6751 arm_SMULTT_EQ: "SMULTT.EQ", | 8108 arm_SMULTT_EQ: "SMULTT.EQ", |
6752 arm_SMULTT_NE: "SMULTT.NE", | 8109 arm_SMULTT_NE: "SMULTT.NE", |
6753 arm_SMULTT_CS: "SMULTT.CS", | 8110 arm_SMULTT_CS: "SMULTT.CS", |
6754 arm_SMULTT_CC: "SMULTT.CC", | 8111 arm_SMULTT_CC: "SMULTT.CC", |
6755 arm_SMULTT_MI: "SMULTT.MI", | 8112 arm_SMULTT_MI: "SMULTT.MI", |
6756 arm_SMULTT_PL: "SMULTT.PL", | 8113 arm_SMULTT_PL: "SMULTT.PL", |
6757 arm_SMULTT_VS: "SMULTT.VS", | 8114 arm_SMULTT_VS: "SMULTT.VS", |
6758 arm_SMULTT_VC: "SMULTT.VC", | 8115 arm_SMULTT_VC: "SMULTT.VC", |
6759 arm_SMULTT_HI: "SMULTT.HI", | 8116 arm_SMULTT_HI: "SMULTT.HI", |
6760 arm_SMULTT_LS: "SMULTT.LS", | 8117 arm_SMULTT_LS: "SMULTT.LS", |
6761 arm_SMULTT_GE: "SMULTT.GE", | 8118 arm_SMULTT_GE: "SMULTT.GE", |
6762 arm_SMULTT_LT: "SMULTT.LT", | 8119 arm_SMULTT_LT: "SMULTT.LT", |
6763 arm_SMULTT_GT: "SMULTT.GT", | 8120 arm_SMULTT_GT: "SMULTT.GT", |
6764 arm_SMULTT_LE: "SMULTT.LE", | 8121 arm_SMULTT_LE: "SMULTT.LE", |
6765 arm_SMULTT: "SMULTT", | 8122 arm_SMULTT: "SMULTT", |
6766 arm_SMULTT_ZZ: "SMULTT.ZZ", | 8123 arm_SMULTT_ZZ: "SMULTT.ZZ", |
6767 arm_SMULL_EQ: "SMULL.EQ", | 8124 arm_SMULL_EQ: "SMULL.EQ", |
6768 arm_SMULL_NE: "SMULL.NE", | 8125 arm_SMULL_NE: "SMULL.NE", |
6769 arm_SMULL_CS: "SMULL.CS", | 8126 arm_SMULL_CS: "SMULL.CS", |
6770 arm_SMULL_CC: "SMULL.CC", | 8127 arm_SMULL_CC: "SMULL.CC", |
6771 arm_SMULL_MI: "SMULL.MI", | 8128 arm_SMULL_MI: "SMULL.MI", |
6772 arm_SMULL_PL: "SMULL.PL", | 8129 arm_SMULL_PL: "SMULL.PL", |
6773 arm_SMULL_VS: "SMULL.VS", | 8130 arm_SMULL_VS: "SMULL.VS", |
6774 arm_SMULL_VC: "SMULL.VC", | 8131 arm_SMULL_VC: "SMULL.VC", |
6775 arm_SMULL_HI: "SMULL.HI", | 8132 arm_SMULL_HI: "SMULL.HI", |
6776 arm_SMULL_LS: "SMULL.LS", | 8133 arm_SMULL_LS: "SMULL.LS", |
6777 arm_SMULL_GE: "SMULL.GE", | 8134 arm_SMULL_GE: "SMULL.GE", |
6778 arm_SMULL_LT: "SMULL.LT", | 8135 arm_SMULL_LT: "SMULL.LT", |
6779 arm_SMULL_GT: "SMULL.GT", | 8136 arm_SMULL_GT: "SMULL.GT", |
6780 arm_SMULL_LE: "SMULL.LE", | 8137 arm_SMULL_LE: "SMULL.LE", |
6781 arm_SMULL: "SMULL", | 8138 arm_SMULL: "SMULL", |
6782 arm_SMULL_ZZ: "SMULL.ZZ", | 8139 arm_SMULL_ZZ: "SMULL.ZZ", |
6783 arm_SMULL_S_EQ: "SMULL.S.EQ", | 8140 arm_SMULL_S_EQ: "SMULL.S.EQ", |
6784 arm_SMULL_S_NE: "SMULL.S.NE", | 8141 arm_SMULL_S_NE: "SMULL.S.NE", |
6785 arm_SMULL_S_CS: "SMULL.S.CS", | 8142 arm_SMULL_S_CS: "SMULL.S.CS", |
6786 arm_SMULL_S_CC: "SMULL.S.CC", | 8143 arm_SMULL_S_CC: "SMULL.S.CC", |
6787 arm_SMULL_S_MI: "SMULL.S.MI", | 8144 arm_SMULL_S_MI: "SMULL.S.MI", |
6788 arm_SMULL_S_PL: "SMULL.S.PL", | 8145 arm_SMULL_S_PL: "SMULL.S.PL", |
6789 arm_SMULL_S_VS: "SMULL.S.VS", | 8146 arm_SMULL_S_VS: "SMULL.S.VS", |
6790 arm_SMULL_S_VC: "SMULL.S.VC", | 8147 arm_SMULL_S_VC: "SMULL.S.VC", |
6791 arm_SMULL_S_HI: "SMULL.S.HI", | 8148 arm_SMULL_S_HI: "SMULL.S.HI", |
6792 arm_SMULL_S_LS: "SMULL.S.LS", | 8149 arm_SMULL_S_LS: "SMULL.S.LS", |
6793 arm_SMULL_S_GE: "SMULL.S.GE", | 8150 arm_SMULL_S_GE: "SMULL.S.GE", |
6794 arm_SMULL_S_LT: "SMULL.S.LT", | 8151 arm_SMULL_S_LT: "SMULL.S.LT", |
6795 arm_SMULL_S_GT: "SMULL.S.GT", | 8152 arm_SMULL_S_GT: "SMULL.S.GT", |
6796 arm_SMULL_S_LE: "SMULL.S.LE", | 8153 arm_SMULL_S_LE: "SMULL.S.LE", |
6797 arm_SMULL_S: "SMULL.S", | 8154 arm_SMULL_S: "SMULL.S", |
6798 arm_SMULL_S_ZZ: "SMULL.S.ZZ", | 8155 arm_SMULL_S_ZZ: "SMULL.S.ZZ", |
6799 arm_SMULWB_EQ: "SMULWB.EQ", | 8156 arm_SMULWB_EQ: "SMULWB.EQ", |
6800 arm_SMULWB_NE: "SMULWB.NE", | 8157 arm_SMULWB_NE: "SMULWB.NE", |
6801 arm_SMULWB_CS: "SMULWB.CS", | 8158 arm_SMULWB_CS: "SMULWB.CS", |
6802 arm_SMULWB_CC: "SMULWB.CC", | 8159 arm_SMULWB_CC: "SMULWB.CC", |
6803 arm_SMULWB_MI: "SMULWB.MI", | 8160 arm_SMULWB_MI: "SMULWB.MI", |
6804 arm_SMULWB_PL: "SMULWB.PL", | 8161 arm_SMULWB_PL: "SMULWB.PL", |
6805 arm_SMULWB_VS: "SMULWB.VS", | 8162 arm_SMULWB_VS: "SMULWB.VS", |
6806 arm_SMULWB_VC: "SMULWB.VC", | 8163 arm_SMULWB_VC: "SMULWB.VC", |
6807 arm_SMULWB_HI: "SMULWB.HI", | 8164 arm_SMULWB_HI: "SMULWB.HI", |
6808 arm_SMULWB_LS: "SMULWB.LS", | 8165 arm_SMULWB_LS: "SMULWB.LS", |
6809 arm_SMULWB_GE: "SMULWB.GE", | 8166 arm_SMULWB_GE: "SMULWB.GE", |
6810 arm_SMULWB_LT: "SMULWB.LT", | 8167 arm_SMULWB_LT: "SMULWB.LT", |
6811 arm_SMULWB_GT: "SMULWB.GT", | 8168 arm_SMULWB_GT: "SMULWB.GT", |
6812 arm_SMULWB_LE: "SMULWB.LE", | 8169 arm_SMULWB_LE: "SMULWB.LE", |
6813 arm_SMULWB: "SMULWB", | 8170 arm_SMULWB: "SMULWB", |
6814 arm_SMULWB_ZZ: "SMULWB.ZZ", | 8171 arm_SMULWB_ZZ: "SMULWB.ZZ", |
6815 arm_SMULWT_EQ: "SMULWT.EQ", | 8172 arm_SMULWT_EQ: "SMULWT.EQ", |
6816 arm_SMULWT_NE: "SMULWT.NE", | 8173 arm_SMULWT_NE: "SMULWT.NE", |
6817 arm_SMULWT_CS: "SMULWT.CS", | 8174 arm_SMULWT_CS: "SMULWT.CS", |
6818 arm_SMULWT_CC: "SMULWT.CC", | 8175 arm_SMULWT_CC: "SMULWT.CC", |
6819 arm_SMULWT_MI: "SMULWT.MI", | 8176 arm_SMULWT_MI: "SMULWT.MI", |
6820 arm_SMULWT_PL: "SMULWT.PL", | 8177 arm_SMULWT_PL: "SMULWT.PL", |
6821 arm_SMULWT_VS: "SMULWT.VS", | 8178 arm_SMULWT_VS: "SMULWT.VS", |
6822 arm_SMULWT_VC: "SMULWT.VC", | 8179 arm_SMULWT_VC: "SMULWT.VC", |
6823 arm_SMULWT_HI: "SMULWT.HI", | 8180 arm_SMULWT_HI: "SMULWT.HI", |
6824 arm_SMULWT_LS: "SMULWT.LS", | 8181 arm_SMULWT_LS: "SMULWT.LS", |
6825 arm_SMULWT_GE: "SMULWT.GE", | 8182 arm_SMULWT_GE: "SMULWT.GE", |
6826 arm_SMULWT_LT: "SMULWT.LT", | 8183 arm_SMULWT_LT: "SMULWT.LT", |
6827 arm_SMULWT_GT: "SMULWT.GT", | 8184 arm_SMULWT_GT: "SMULWT.GT", |
6828 arm_SMULWT_LE: "SMULWT.LE", | 8185 arm_SMULWT_LE: "SMULWT.LE", |
6829 arm_SMULWT: "SMULWT", | 8186 arm_SMULWT: "SMULWT", |
6830 arm_SMULWT_ZZ: "SMULWT.ZZ", | 8187 arm_SMULWT_ZZ: "SMULWT.ZZ", |
6831 arm_SMUSD_EQ: "SMUSD.EQ", | 8188 arm_SMUSD_EQ: "SMUSD.EQ", |
6832 arm_SMUSD_NE: "SMUSD.NE", | 8189 arm_SMUSD_NE: "SMUSD.NE", |
6833 arm_SMUSD_CS: "SMUSD.CS", | 8190 arm_SMUSD_CS: "SMUSD.CS", |
6834 arm_SMUSD_CC: "SMUSD.CC", | 8191 arm_SMUSD_CC: "SMUSD.CC", |
6835 arm_SMUSD_MI: "SMUSD.MI", | 8192 arm_SMUSD_MI: "SMUSD.MI", |
6836 arm_SMUSD_PL: "SMUSD.PL", | 8193 arm_SMUSD_PL: "SMUSD.PL", |
6837 arm_SMUSD_VS: "SMUSD.VS", | 8194 arm_SMUSD_VS: "SMUSD.VS", |
6838 arm_SMUSD_VC: "SMUSD.VC", | 8195 arm_SMUSD_VC: "SMUSD.VC", |
6839 arm_SMUSD_HI: "SMUSD.HI", | 8196 arm_SMUSD_HI: "SMUSD.HI", |
6840 arm_SMUSD_LS: "SMUSD.LS", | 8197 arm_SMUSD_LS: "SMUSD.LS", |
6841 arm_SMUSD_GE: "SMUSD.GE", | 8198 arm_SMUSD_GE: "SMUSD.GE", |
6842 arm_SMUSD_LT: "SMUSD.LT", | 8199 arm_SMUSD_LT: "SMUSD.LT", |
6843 arm_SMUSD_GT: "SMUSD.GT", | 8200 arm_SMUSD_GT: "SMUSD.GT", |
6844 arm_SMUSD_LE: "SMUSD.LE", | 8201 arm_SMUSD_LE: "SMUSD.LE", |
6845 arm_SMUSD: "SMUSD", | 8202 arm_SMUSD: "SMUSD", |
6846 arm_SMUSD_ZZ: "SMUSD.ZZ", | 8203 arm_SMUSD_ZZ: "SMUSD.ZZ", |
6847 arm_SMUSD_X_EQ: "SMUSD.X.EQ", | 8204 arm_SMUSD_X_EQ: "SMUSD.X.EQ", |
6848 arm_SMUSD_X_NE: "SMUSD.X.NE", | 8205 arm_SMUSD_X_NE: "SMUSD.X.NE", |
6849 arm_SMUSD_X_CS: "SMUSD.X.CS", | 8206 arm_SMUSD_X_CS: "SMUSD.X.CS", |
6850 arm_SMUSD_X_CC: "SMUSD.X.CC", | 8207 arm_SMUSD_X_CC: "SMUSD.X.CC", |
6851 arm_SMUSD_X_MI: "SMUSD.X.MI", | 8208 arm_SMUSD_X_MI: "SMUSD.X.MI", |
6852 arm_SMUSD_X_PL: "SMUSD.X.PL", | 8209 arm_SMUSD_X_PL: "SMUSD.X.PL", |
6853 arm_SMUSD_X_VS: "SMUSD.X.VS", | 8210 arm_SMUSD_X_VS: "SMUSD.X.VS", |
6854 arm_SMUSD_X_VC: "SMUSD.X.VC", | 8211 arm_SMUSD_X_VC: "SMUSD.X.VC", |
6855 arm_SMUSD_X_HI: "SMUSD.X.HI", | 8212 arm_SMUSD_X_HI: "SMUSD.X.HI", |
6856 arm_SMUSD_X_LS: "SMUSD.X.LS", | 8213 arm_SMUSD_X_LS: "SMUSD.X.LS", |
6857 arm_SMUSD_X_GE: "SMUSD.X.GE", | 8214 arm_SMUSD_X_GE: "SMUSD.X.GE", |
6858 arm_SMUSD_X_LT: "SMUSD.X.LT", | 8215 arm_SMUSD_X_LT: "SMUSD.X.LT", |
6859 arm_SMUSD_X_GT: "SMUSD.X.GT", | 8216 arm_SMUSD_X_GT: "SMUSD.X.GT", |
6860 arm_SMUSD_X_LE: "SMUSD.X.LE", | 8217 arm_SMUSD_X_LE: "SMUSD.X.LE", |
6861 arm_SMUSD_X: "SMUSD.X", | 8218 arm_SMUSD_X: "SMUSD.X", |
6862 arm_SMUSD_X_ZZ: "SMUSD.X.ZZ", | 8219 arm_SMUSD_X_ZZ: "SMUSD.X.ZZ", |
6863 arm_SSAT_EQ: "SSAT.EQ", | 8220 arm_SSAT_EQ: "SSAT.EQ", |
6864 arm_SSAT_NE: "SSAT.NE", | 8221 arm_SSAT_NE: "SSAT.NE", |
6865 arm_SSAT_CS: "SSAT.CS", | 8222 arm_SSAT_CS: "SSAT.CS", |
6866 arm_SSAT_CC: "SSAT.CC", | 8223 arm_SSAT_CC: "SSAT.CC", |
6867 arm_SSAT_MI: "SSAT.MI", | 8224 arm_SSAT_MI: "SSAT.MI", |
6868 arm_SSAT_PL: "SSAT.PL", | 8225 arm_SSAT_PL: "SSAT.PL", |
6869 arm_SSAT_VS: "SSAT.VS", | 8226 arm_SSAT_VS: "SSAT.VS", |
6870 arm_SSAT_VC: "SSAT.VC", | 8227 arm_SSAT_VC: "SSAT.VC", |
6871 arm_SSAT_HI: "SSAT.HI", | 8228 arm_SSAT_HI: "SSAT.HI", |
6872 arm_SSAT_LS: "SSAT.LS", | 8229 arm_SSAT_LS: "SSAT.LS", |
6873 arm_SSAT_GE: "SSAT.GE", | 8230 arm_SSAT_GE: "SSAT.GE", |
6874 arm_SSAT_LT: "SSAT.LT", | 8231 arm_SSAT_LT: "SSAT.LT", |
6875 arm_SSAT_GT: "SSAT.GT", | 8232 arm_SSAT_GT: "SSAT.GT", |
6876 arm_SSAT_LE: "SSAT.LE", | 8233 arm_SSAT_LE: "SSAT.LE", |
6877 arm_SSAT: "SSAT", | 8234 arm_SSAT: "SSAT", |
6878 arm_SSAT_ZZ: "SSAT.ZZ", | 8235 arm_SSAT_ZZ: "SSAT.ZZ", |
6879 arm_SSAT16_EQ: "SSAT16.EQ", | 8236 arm_SSAT16_EQ: "SSAT16.EQ", |
6880 arm_SSAT16_NE: "SSAT16.NE", | 8237 arm_SSAT16_NE: "SSAT16.NE", |
6881 arm_SSAT16_CS: "SSAT16.CS", | 8238 arm_SSAT16_CS: "SSAT16.CS", |
6882 arm_SSAT16_CC: "SSAT16.CC", | 8239 arm_SSAT16_CC: "SSAT16.CC", |
6883 arm_SSAT16_MI: "SSAT16.MI", | 8240 arm_SSAT16_MI: "SSAT16.MI", |
6884 arm_SSAT16_PL: "SSAT16.PL", | 8241 arm_SSAT16_PL: "SSAT16.PL", |
6885 arm_SSAT16_VS: "SSAT16.VS", | 8242 arm_SSAT16_VS: "SSAT16.VS", |
6886 arm_SSAT16_VC: "SSAT16.VC", | 8243 arm_SSAT16_VC: "SSAT16.VC", |
6887 arm_SSAT16_HI: "SSAT16.HI", | 8244 arm_SSAT16_HI: "SSAT16.HI", |
6888 arm_SSAT16_LS: "SSAT16.LS", | 8245 arm_SSAT16_LS: "SSAT16.LS", |
6889 arm_SSAT16_GE: "SSAT16.GE", | 8246 arm_SSAT16_GE: "SSAT16.GE", |
6890 arm_SSAT16_LT: "SSAT16.LT", | 8247 arm_SSAT16_LT: "SSAT16.LT", |
6891 arm_SSAT16_GT: "SSAT16.GT", | 8248 arm_SSAT16_GT: "SSAT16.GT", |
6892 arm_SSAT16_LE: "SSAT16.LE", | 8249 arm_SSAT16_LE: "SSAT16.LE", |
6893 arm_SSAT16: "SSAT16", | 8250 arm_SSAT16: "SSAT16", |
6894 arm_SSAT16_ZZ: "SSAT16.ZZ", | 8251 arm_SSAT16_ZZ: "SSAT16.ZZ", |
6895 arm_SSAX_EQ: "SSAX.EQ", | 8252 arm_SSAX_EQ: "SSAX.EQ", |
6896 arm_SSAX_NE: "SSAX.NE", | 8253 arm_SSAX_NE: "SSAX.NE", |
6897 arm_SSAX_CS: "SSAX.CS", | 8254 arm_SSAX_CS: "SSAX.CS", |
6898 arm_SSAX_CC: "SSAX.CC", | 8255 arm_SSAX_CC: "SSAX.CC", |
6899 arm_SSAX_MI: "SSAX.MI", | 8256 arm_SSAX_MI: "SSAX.MI", |
6900 arm_SSAX_PL: "SSAX.PL", | 8257 arm_SSAX_PL: "SSAX.PL", |
6901 arm_SSAX_VS: "SSAX.VS", | 8258 arm_SSAX_VS: "SSAX.VS", |
6902 arm_SSAX_VC: "SSAX.VC", | 8259 arm_SSAX_VC: "SSAX.VC", |
6903 arm_SSAX_HI: "SSAX.HI", | 8260 arm_SSAX_HI: "SSAX.HI", |
6904 arm_SSAX_LS: "SSAX.LS", | 8261 arm_SSAX_LS: "SSAX.LS", |
6905 arm_SSAX_GE: "SSAX.GE", | 8262 arm_SSAX_GE: "SSAX.GE", |
6906 arm_SSAX_LT: "SSAX.LT", | 8263 arm_SSAX_LT: "SSAX.LT", |
6907 arm_SSAX_GT: "SSAX.GT", | 8264 arm_SSAX_GT: "SSAX.GT", |
6908 arm_SSAX_LE: "SSAX.LE", | 8265 arm_SSAX_LE: "SSAX.LE", |
6909 arm_SSAX: "SSAX", | 8266 arm_SSAX: "SSAX", |
6910 arm_SSAX_ZZ: "SSAX.ZZ", | 8267 arm_SSAX_ZZ: "SSAX.ZZ", |
6911 arm_SSUB16_EQ: "SSUB16.EQ", | 8268 arm_SSUB16_EQ: "SSUB16.EQ", |
6912 arm_SSUB16_NE: "SSUB16.NE", | 8269 arm_SSUB16_NE: "SSUB16.NE", |
6913 arm_SSUB16_CS: "SSUB16.CS", | 8270 arm_SSUB16_CS: "SSUB16.CS", |
6914 arm_SSUB16_CC: "SSUB16.CC", | 8271 arm_SSUB16_CC: "SSUB16.CC", |
6915 arm_SSUB16_MI: "SSUB16.MI", | 8272 arm_SSUB16_MI: "SSUB16.MI", |
6916 arm_SSUB16_PL: "SSUB16.PL", | 8273 arm_SSUB16_PL: "SSUB16.PL", |
6917 arm_SSUB16_VS: "SSUB16.VS", | 8274 arm_SSUB16_VS: "SSUB16.VS", |
6918 arm_SSUB16_VC: "SSUB16.VC", | 8275 arm_SSUB16_VC: "SSUB16.VC", |
6919 arm_SSUB16_HI: "SSUB16.HI", | 8276 arm_SSUB16_HI: "SSUB16.HI", |
6920 arm_SSUB16_LS: "SSUB16.LS", | 8277 arm_SSUB16_LS: "SSUB16.LS", |
6921 arm_SSUB16_GE: "SSUB16.GE", | 8278 arm_SSUB16_GE: "SSUB16.GE", |
6922 arm_SSUB16_LT: "SSUB16.LT", | 8279 arm_SSUB16_LT: "SSUB16.LT", |
6923 arm_SSUB16_GT: "SSUB16.GT", | 8280 arm_SSUB16_GT: "SSUB16.GT", |
6924 arm_SSUB16_LE: "SSUB16.LE", | 8281 arm_SSUB16_LE: "SSUB16.LE", |
6925 arm_SSUB16: "SSUB16", | 8282 arm_SSUB16: "SSUB16", |
6926 arm_SSUB16_ZZ: "SSUB16.ZZ", | 8283 arm_SSUB16_ZZ: "SSUB16.ZZ", |
6927 arm_SSUB8_EQ: "SSUB8.EQ", | 8284 arm_SSUB8_EQ: "SSUB8.EQ", |
6928 arm_SSUB8_NE: "SSUB8.NE", | 8285 arm_SSUB8_NE: "SSUB8.NE", |
6929 arm_SSUB8_CS: "SSUB8.CS", | 8286 arm_SSUB8_CS: "SSUB8.CS", |
6930 arm_SSUB8_CC: "SSUB8.CC", | 8287 arm_SSUB8_CC: "SSUB8.CC", |
6931 arm_SSUB8_MI: "SSUB8.MI", | 8288 arm_SSUB8_MI: "SSUB8.MI", |
6932 arm_SSUB8_PL: "SSUB8.PL", | 8289 arm_SSUB8_PL: "SSUB8.PL", |
6933 arm_SSUB8_VS: "SSUB8.VS", | 8290 arm_SSUB8_VS: "SSUB8.VS", |
6934 arm_SSUB8_VC: "SSUB8.VC", | 8291 arm_SSUB8_VC: "SSUB8.VC", |
6935 arm_SSUB8_HI: "SSUB8.HI", | 8292 arm_SSUB8_HI: "SSUB8.HI", |
6936 arm_SSUB8_LS: "SSUB8.LS", | 8293 arm_SSUB8_LS: "SSUB8.LS", |
6937 arm_SSUB8_GE: "SSUB8.GE", | 8294 arm_SSUB8_GE: "SSUB8.GE", |
6938 arm_SSUB8_LT: "SSUB8.LT", | 8295 arm_SSUB8_LT: "SSUB8.LT", |
6939 arm_SSUB8_GT: "SSUB8.GT", | 8296 arm_SSUB8_GT: "SSUB8.GT", |
6940 arm_SSUB8_LE: "SSUB8.LE", | 8297 arm_SSUB8_LE: "SSUB8.LE", |
6941 arm_SSUB8: "SSUB8", | 8298 arm_SSUB8: "SSUB8", |
6942 arm_SSUB8_ZZ: "SSUB8.ZZ", | 8299 arm_SSUB8_ZZ: "SSUB8.ZZ", |
6943 arm_STM_EQ: "STM.EQ", | 8300 arm_STM_EQ: "STM.EQ", |
6944 arm_STM_NE: "STM.NE", | 8301 arm_STM_NE: "STM.NE", |
6945 arm_STM_CS: "STM.CS", | 8302 arm_STM_CS: "STM.CS", |
6946 arm_STM_CC: "STM.CC", | 8303 arm_STM_CC: "STM.CC", |
6947 arm_STM_MI: "STM.MI", | 8304 arm_STM_MI: "STM.MI", |
6948 arm_STM_PL: "STM.PL", | 8305 arm_STM_PL: "STM.PL", |
6949 arm_STM_VS: "STM.VS", | 8306 arm_STM_VS: "STM.VS", |
6950 arm_STM_VC: "STM.VC", | 8307 arm_STM_VC: "STM.VC", |
6951 arm_STM_HI: "STM.HI", | 8308 arm_STM_HI: "STM.HI", |
6952 arm_STM_LS: "STM.LS", | 8309 arm_STM_LS: "STM.LS", |
6953 arm_STM_GE: "STM.GE", | 8310 arm_STM_GE: "STM.GE", |
6954 arm_STM_LT: "STM.LT", | 8311 arm_STM_LT: "STM.LT", |
6955 arm_STM_GT: "STM.GT", | 8312 arm_STM_GT: "STM.GT", |
6956 arm_STM_LE: "STM.LE", | 8313 arm_STM_LE: "STM.LE", |
6957 arm_STM: "STM", | 8314 arm_STM: "STM", |
6958 arm_STM_ZZ: "STM.ZZ", | 8315 arm_STM_ZZ: "STM.ZZ", |
6959 arm_STMDA_EQ: "STMDA.EQ", | 8316 arm_STMDA_EQ: "STMDA.EQ", |
6960 arm_STMDA_NE: "STMDA.NE", | 8317 arm_STMDA_NE: "STMDA.NE", |
6961 arm_STMDA_CS: "STMDA.CS", | 8318 arm_STMDA_CS: "STMDA.CS", |
6962 arm_STMDA_CC: "STMDA.CC", | 8319 arm_STMDA_CC: "STMDA.CC", |
6963 arm_STMDA_MI: "STMDA.MI", | 8320 arm_STMDA_MI: "STMDA.MI", |
6964 arm_STMDA_PL: "STMDA.PL", | 8321 arm_STMDA_PL: "STMDA.PL", |
6965 arm_STMDA_VS: "STMDA.VS", | 8322 arm_STMDA_VS: "STMDA.VS", |
6966 arm_STMDA_VC: "STMDA.VC", | 8323 arm_STMDA_VC: "STMDA.VC", |
6967 arm_STMDA_HI: "STMDA.HI", | 8324 arm_STMDA_HI: "STMDA.HI", |
6968 arm_STMDA_LS: "STMDA.LS", | 8325 arm_STMDA_LS: "STMDA.LS", |
6969 arm_STMDA_GE: "STMDA.GE", | 8326 arm_STMDA_GE: "STMDA.GE", |
6970 arm_STMDA_LT: "STMDA.LT", | 8327 arm_STMDA_LT: "STMDA.LT", |
6971 arm_STMDA_GT: "STMDA.GT", | 8328 arm_STMDA_GT: "STMDA.GT", |
6972 arm_STMDA_LE: "STMDA.LE", | 8329 arm_STMDA_LE: "STMDA.LE", |
6973 arm_STMDA: "STMDA", | 8330 arm_STMDA: "STMDA", |
6974 arm_STMDA_ZZ: "STMDA.ZZ", | 8331 arm_STMDA_ZZ: "STMDA.ZZ", |
6975 arm_STMDB_EQ: "STMDB.EQ", | 8332 arm_STMDB_EQ: "STMDB.EQ", |
6976 arm_STMDB_NE: "STMDB.NE", | 8333 arm_STMDB_NE: "STMDB.NE", |
6977 arm_STMDB_CS: "STMDB.CS", | 8334 arm_STMDB_CS: "STMDB.CS", |
6978 arm_STMDB_CC: "STMDB.CC", | 8335 arm_STMDB_CC: "STMDB.CC", |
6979 arm_STMDB_MI: "STMDB.MI", | 8336 arm_STMDB_MI: "STMDB.MI", |
6980 arm_STMDB_PL: "STMDB.PL", | 8337 arm_STMDB_PL: "STMDB.PL", |
6981 arm_STMDB_VS: "STMDB.VS", | 8338 arm_STMDB_VS: "STMDB.VS", |
6982 arm_STMDB_VC: "STMDB.VC", | 8339 arm_STMDB_VC: "STMDB.VC", |
6983 arm_STMDB_HI: "STMDB.HI", | 8340 arm_STMDB_HI: "STMDB.HI", |
6984 arm_STMDB_LS: "STMDB.LS", | 8341 arm_STMDB_LS: "STMDB.LS", |
6985 arm_STMDB_GE: "STMDB.GE", | 8342 arm_STMDB_GE: "STMDB.GE", |
6986 arm_STMDB_LT: "STMDB.LT", | 8343 arm_STMDB_LT: "STMDB.LT", |
6987 arm_STMDB_GT: "STMDB.GT", | 8344 arm_STMDB_GT: "STMDB.GT", |
6988 arm_STMDB_LE: "STMDB.LE", | 8345 arm_STMDB_LE: "STMDB.LE", |
6989 arm_STMDB: "STMDB", | 8346 arm_STMDB: "STMDB", |
6990 arm_STMDB_ZZ: "STMDB.ZZ", | 8347 arm_STMDB_ZZ: "STMDB.ZZ", |
6991 arm_STMIB_EQ: "STMIB.EQ", | 8348 arm_STMIB_EQ: "STMIB.EQ", |
6992 arm_STMIB_NE: "STMIB.NE", | 8349 arm_STMIB_NE: "STMIB.NE", |
6993 arm_STMIB_CS: "STMIB.CS", | 8350 arm_STMIB_CS: "STMIB.CS", |
6994 arm_STMIB_CC: "STMIB.CC", | 8351 arm_STMIB_CC: "STMIB.CC", |
6995 arm_STMIB_MI: "STMIB.MI", | 8352 arm_STMIB_MI: "STMIB.MI", |
6996 arm_STMIB_PL: "STMIB.PL", | 8353 arm_STMIB_PL: "STMIB.PL", |
6997 arm_STMIB_VS: "STMIB.VS", | 8354 arm_STMIB_VS: "STMIB.VS", |
6998 arm_STMIB_VC: "STMIB.VC", | 8355 arm_STMIB_VC: "STMIB.VC", |
6999 arm_STMIB_HI: "STMIB.HI", | 8356 arm_STMIB_HI: "STMIB.HI", |
7000 arm_STMIB_LS: "STMIB.LS", | 8357 arm_STMIB_LS: "STMIB.LS", |
7001 arm_STMIB_GE: "STMIB.GE", | 8358 arm_STMIB_GE: "STMIB.GE", |
7002 arm_STMIB_LT: "STMIB.LT", | 8359 arm_STMIB_LT: "STMIB.LT", |
7003 arm_STMIB_GT: "STMIB.GT", | 8360 arm_STMIB_GT: "STMIB.GT", |
7004 arm_STMIB_LE: "STMIB.LE", | 8361 arm_STMIB_LE: "STMIB.LE", |
7005 arm_STMIB: "STMIB", | 8362 arm_STMIB: "STMIB", |
7006 arm_STMIB_ZZ: "STMIB.ZZ", | 8363 arm_STMIB_ZZ: "STMIB.ZZ", |
7007 arm_STR_EQ: "STR.EQ", | 8364 arm_STR_EQ: "STR.EQ", |
7008 arm_STR_NE: "STR.NE", | 8365 arm_STR_NE: "STR.NE", |
7009 arm_STR_CS: "STR.CS", | 8366 arm_STR_CS: "STR.CS", |
7010 arm_STR_CC: "STR.CC", | 8367 arm_STR_CC: "STR.CC", |
7011 arm_STR_MI: "STR.MI", | 8368 arm_STR_MI: "STR.MI", |
7012 arm_STR_PL: "STR.PL", | 8369 arm_STR_PL: "STR.PL", |
7013 arm_STR_VS: "STR.VS", | 8370 arm_STR_VS: "STR.VS", |
7014 arm_STR_VC: "STR.VC", | 8371 arm_STR_VC: "STR.VC", |
7015 arm_STR_HI: "STR.HI", | 8372 arm_STR_HI: "STR.HI", |
7016 arm_STR_LS: "STR.LS", | 8373 arm_STR_LS: "STR.LS", |
7017 arm_STR_GE: "STR.GE", | 8374 arm_STR_GE: "STR.GE", |
7018 arm_STR_LT: "STR.LT", | 8375 arm_STR_LT: "STR.LT", |
7019 arm_STR_GT: "STR.GT", | 8376 arm_STR_GT: "STR.GT", |
7020 arm_STR_LE: "STR.LE", | 8377 arm_STR_LE: "STR.LE", |
7021 arm_STR: "STR", | 8378 arm_STR: "STR", |
7022 arm_STR_ZZ: "STR.ZZ", | 8379 arm_STR_ZZ: "STR.ZZ", |
7023 arm_STRB_EQ: "STRB.EQ", | 8380 arm_STRB_EQ: "STRB.EQ", |
7024 arm_STRB_NE: "STRB.NE", | 8381 arm_STRB_NE: "STRB.NE", |
7025 arm_STRB_CS: "STRB.CS", | 8382 arm_STRB_CS: "STRB.CS", |
7026 arm_STRB_CC: "STRB.CC", | 8383 arm_STRB_CC: "STRB.CC", |
7027 arm_STRB_MI: "STRB.MI", | 8384 arm_STRB_MI: "STRB.MI", |
7028 arm_STRB_PL: "STRB.PL", | 8385 arm_STRB_PL: "STRB.PL", |
7029 arm_STRB_VS: "STRB.VS", | 8386 arm_STRB_VS: "STRB.VS", |
7030 arm_STRB_VC: "STRB.VC", | 8387 arm_STRB_VC: "STRB.VC", |
7031 arm_STRB_HI: "STRB.HI", | 8388 arm_STRB_HI: "STRB.HI", |
7032 arm_STRB_LS: "STRB.LS", | 8389 arm_STRB_LS: "STRB.LS", |
7033 arm_STRB_GE: "STRB.GE", | 8390 arm_STRB_GE: "STRB.GE", |
7034 arm_STRB_LT: "STRB.LT", | 8391 arm_STRB_LT: "STRB.LT", |
7035 arm_STRB_GT: "STRB.GT", | 8392 arm_STRB_GT: "STRB.GT", |
7036 arm_STRB_LE: "STRB.LE", | 8393 arm_STRB_LE: "STRB.LE", |
7037 arm_STRB: "STRB", | 8394 arm_STRB: "STRB", |
7038 arm_STRB_ZZ: "STRB.ZZ", | 8395 arm_STRB_ZZ: "STRB.ZZ", |
7039 arm_STRBT_EQ: "STRBT.EQ", | 8396 arm_STRBT_EQ: "STRBT.EQ", |
7040 arm_STRBT_NE: "STRBT.NE", | 8397 arm_STRBT_NE: "STRBT.NE", |
7041 arm_STRBT_CS: "STRBT.CS", | 8398 arm_STRBT_CS: "STRBT.CS", |
7042 arm_STRBT_CC: "STRBT.CC", | 8399 arm_STRBT_CC: "STRBT.CC", |
7043 arm_STRBT_MI: "STRBT.MI", | 8400 arm_STRBT_MI: "STRBT.MI", |
7044 arm_STRBT_PL: "STRBT.PL", | 8401 arm_STRBT_PL: "STRBT.PL", |
7045 arm_STRBT_VS: "STRBT.VS", | 8402 arm_STRBT_VS: "STRBT.VS", |
7046 arm_STRBT_VC: "STRBT.VC", | 8403 arm_STRBT_VC: "STRBT.VC", |
7047 arm_STRBT_HI: "STRBT.HI", | 8404 arm_STRBT_HI: "STRBT.HI", |
7048 arm_STRBT_LS: "STRBT.LS", | 8405 arm_STRBT_LS: "STRBT.LS", |
7049 arm_STRBT_GE: "STRBT.GE", | 8406 arm_STRBT_GE: "STRBT.GE", |
7050 arm_STRBT_LT: "STRBT.LT", | 8407 arm_STRBT_LT: "STRBT.LT", |
7051 arm_STRBT_GT: "STRBT.GT", | 8408 arm_STRBT_GT: "STRBT.GT", |
7052 arm_STRBT_LE: "STRBT.LE", | 8409 arm_STRBT_LE: "STRBT.LE", |
7053 arm_STRBT: "STRBT", | 8410 arm_STRBT: "STRBT", |
7054 arm_STRBT_ZZ: "STRBT.ZZ", | 8411 arm_STRBT_ZZ: "STRBT.ZZ", |
7055 arm_STRD_EQ: "STRD.EQ", | 8412 arm_STRD_EQ: "STRD.EQ", |
7056 arm_STRD_NE: "STRD.NE", | 8413 arm_STRD_NE: "STRD.NE", |
7057 arm_STRD_CS: "STRD.CS", | 8414 arm_STRD_CS: "STRD.CS", |
7058 arm_STRD_CC: "STRD.CC", | 8415 arm_STRD_CC: "STRD.CC", |
7059 arm_STRD_MI: "STRD.MI", | 8416 arm_STRD_MI: "STRD.MI", |
7060 arm_STRD_PL: "STRD.PL", | 8417 arm_STRD_PL: "STRD.PL", |
7061 arm_STRD_VS: "STRD.VS", | 8418 arm_STRD_VS: "STRD.VS", |
7062 arm_STRD_VC: "STRD.VC", | 8419 arm_STRD_VC: "STRD.VC", |
7063 arm_STRD_HI: "STRD.HI", | 8420 arm_STRD_HI: "STRD.HI", |
7064 arm_STRD_LS: "STRD.LS", | 8421 arm_STRD_LS: "STRD.LS", |
7065 arm_STRD_GE: "STRD.GE", | 8422 arm_STRD_GE: "STRD.GE", |
7066 arm_STRD_LT: "STRD.LT", | 8423 arm_STRD_LT: "STRD.LT", |
7067 arm_STRD_GT: "STRD.GT", | 8424 arm_STRD_GT: "STRD.GT", |
7068 arm_STRD_LE: "STRD.LE", | 8425 arm_STRD_LE: "STRD.LE", |
7069 arm_STRD: "STRD", | 8426 arm_STRD: "STRD", |
7070 arm_STRD_ZZ: "STRD.ZZ", | 8427 arm_STRD_ZZ: "STRD.ZZ", |
7071 arm_STREX_EQ: "STREX.EQ", | 8428 arm_STREX_EQ: "STREX.EQ", |
7072 arm_STREX_NE: "STREX.NE", | 8429 arm_STREX_NE: "STREX.NE", |
7073 arm_STREX_CS: "STREX.CS", | 8430 arm_STREX_CS: "STREX.CS", |
7074 arm_STREX_CC: "STREX.CC", | 8431 arm_STREX_CC: "STREX.CC", |
7075 arm_STREX_MI: "STREX.MI", | 8432 arm_STREX_MI: "STREX.MI", |
7076 arm_STREX_PL: "STREX.PL", | 8433 arm_STREX_PL: "STREX.PL", |
7077 arm_STREX_VS: "STREX.VS", | 8434 arm_STREX_VS: "STREX.VS", |
7078 arm_STREX_VC: "STREX.VC", | 8435 arm_STREX_VC: "STREX.VC", |
7079 arm_STREX_HI: "STREX.HI", | 8436 arm_STREX_HI: "STREX.HI", |
7080 arm_STREX_LS: "STREX.LS", | 8437 arm_STREX_LS: "STREX.LS", |
7081 arm_STREX_GE: "STREX.GE", | 8438 arm_STREX_GE: "STREX.GE", |
7082 arm_STREX_LT: "STREX.LT", | 8439 arm_STREX_LT: "STREX.LT", |
7083 arm_STREX_GT: "STREX.GT", | 8440 arm_STREX_GT: "STREX.GT", |
7084 arm_STREX_LE: "STREX.LE", | 8441 arm_STREX_LE: "STREX.LE", |
7085 arm_STREX: "STREX", | 8442 arm_STREX: "STREX", |
7086 arm_STREX_ZZ: "STREX.ZZ", | 8443 arm_STREX_ZZ: "STREX.ZZ", |
7087 arm_STREXB_EQ: "STREXB.EQ", | 8444 arm_STREXB_EQ: "STREXB.EQ", |
7088 arm_STREXB_NE: "STREXB.NE", | 8445 arm_STREXB_NE: "STREXB.NE", |
7089 arm_STREXB_CS: "STREXB.CS", | 8446 arm_STREXB_CS: "STREXB.CS", |
7090 arm_STREXB_CC: "STREXB.CC", | 8447 arm_STREXB_CC: "STREXB.CC", |
7091 arm_STREXB_MI: "STREXB.MI", | 8448 arm_STREXB_MI: "STREXB.MI", |
7092 arm_STREXB_PL: "STREXB.PL", | 8449 arm_STREXB_PL: "STREXB.PL", |
7093 arm_STREXB_VS: "STREXB.VS", | 8450 arm_STREXB_VS: "STREXB.VS", |
7094 arm_STREXB_VC: "STREXB.VC", | 8451 arm_STREXB_VC: "STREXB.VC", |
7095 arm_STREXB_HI: "STREXB.HI", | 8452 arm_STREXB_HI: "STREXB.HI", |
7096 arm_STREXB_LS: "STREXB.LS", | 8453 arm_STREXB_LS: "STREXB.LS", |
7097 arm_STREXB_GE: "STREXB.GE", | 8454 arm_STREXB_GE: "STREXB.GE", |
7098 arm_STREXB_LT: "STREXB.LT", | 8455 arm_STREXB_LT: "STREXB.LT", |
7099 arm_STREXB_GT: "STREXB.GT", | 8456 arm_STREXB_GT: "STREXB.GT", |
7100 arm_STREXB_LE: "STREXB.LE", | 8457 arm_STREXB_LE: "STREXB.LE", |
7101 arm_STREXB: "STREXB", | 8458 arm_STREXB: "STREXB", |
7102 arm_STREXB_ZZ: "STREXB.ZZ", | 8459 arm_STREXB_ZZ: "STREXB.ZZ", |
7103 arm_STREXD_EQ: "STREXD.EQ", | 8460 arm_STREXD_EQ: "STREXD.EQ", |
7104 arm_STREXD_NE: "STREXD.NE", | 8461 arm_STREXD_NE: "STREXD.NE", |
7105 arm_STREXD_CS: "STREXD.CS", | 8462 arm_STREXD_CS: "STREXD.CS", |
7106 arm_STREXD_CC: "STREXD.CC", | 8463 arm_STREXD_CC: "STREXD.CC", |
7107 arm_STREXD_MI: "STREXD.MI", | 8464 arm_STREXD_MI: "STREXD.MI", |
7108 arm_STREXD_PL: "STREXD.PL", | 8465 arm_STREXD_PL: "STREXD.PL", |
7109 arm_STREXD_VS: "STREXD.VS", | 8466 arm_STREXD_VS: "STREXD.VS", |
7110 arm_STREXD_VC: "STREXD.VC", | 8467 arm_STREXD_VC: "STREXD.VC", |
7111 arm_STREXD_HI: "STREXD.HI", | 8468 arm_STREXD_HI: "STREXD.HI", |
7112 arm_STREXD_LS: "STREXD.LS", | 8469 arm_STREXD_LS: "STREXD.LS", |
7113 arm_STREXD_GE: "STREXD.GE", | 8470 arm_STREXD_GE: "STREXD.GE", |
7114 arm_STREXD_LT: "STREXD.LT", | 8471 arm_STREXD_LT: "STREXD.LT", |
7115 arm_STREXD_GT: "STREXD.GT", | 8472 arm_STREXD_GT: "STREXD.GT", |
7116 arm_STREXD_LE: "STREXD.LE", | 8473 arm_STREXD_LE: "STREXD.LE", |
7117 arm_STREXD: "STREXD", | 8474 arm_STREXD: "STREXD", |
7118 arm_STREXD_ZZ: "STREXD.ZZ", | 8475 arm_STREXD_ZZ: "STREXD.ZZ", |
7119 arm_STREXH_EQ: "STREXH.EQ", | 8476 arm_STREXH_EQ: "STREXH.EQ", |
7120 arm_STREXH_NE: "STREXH.NE", | 8477 arm_STREXH_NE: "STREXH.NE", |
7121 arm_STREXH_CS: "STREXH.CS", | 8478 arm_STREXH_CS: "STREXH.CS", |
7122 arm_STREXH_CC: "STREXH.CC", | 8479 arm_STREXH_CC: "STREXH.CC", |
7123 arm_STREXH_MI: "STREXH.MI", | 8480 arm_STREXH_MI: "STREXH.MI", |
7124 arm_STREXH_PL: "STREXH.PL", | 8481 arm_STREXH_PL: "STREXH.PL", |
7125 arm_STREXH_VS: "STREXH.VS", | 8482 arm_STREXH_VS: "STREXH.VS", |
7126 arm_STREXH_VC: "STREXH.VC", | 8483 arm_STREXH_VC: "STREXH.VC", |
7127 arm_STREXH_HI: "STREXH.HI", | 8484 arm_STREXH_HI: "STREXH.HI", |
7128 arm_STREXH_LS: "STREXH.LS", | 8485 arm_STREXH_LS: "STREXH.LS", |
7129 arm_STREXH_GE: "STREXH.GE", | 8486 arm_STREXH_GE: "STREXH.GE", |
7130 arm_STREXH_LT: "STREXH.LT", | 8487 arm_STREXH_LT: "STREXH.LT", |
7131 arm_STREXH_GT: "STREXH.GT", | 8488 arm_STREXH_GT: "STREXH.GT", |
7132 arm_STREXH_LE: "STREXH.LE", | 8489 arm_STREXH_LE: "STREXH.LE", |
7133 arm_STREXH: "STREXH", | 8490 arm_STREXH: "STREXH", |
7134 arm_STREXH_ZZ: "STREXH.ZZ", | 8491 arm_STREXH_ZZ: "STREXH.ZZ", |
7135 arm_STRH_EQ: "STRH.EQ", | 8492 arm_STRH_EQ: "STRH.EQ", |
7136 arm_STRH_NE: "STRH.NE", | 8493 arm_STRH_NE: "STRH.NE", |
7137 arm_STRH_CS: "STRH.CS", | 8494 arm_STRH_CS: "STRH.CS", |
7138 arm_STRH_CC: "STRH.CC", | 8495 arm_STRH_CC: "STRH.CC", |
7139 arm_STRH_MI: "STRH.MI", | 8496 arm_STRH_MI: "STRH.MI", |
7140 arm_STRH_PL: "STRH.PL", | 8497 arm_STRH_PL: "STRH.PL", |
7141 arm_STRH_VS: "STRH.VS", | 8498 arm_STRH_VS: "STRH.VS", |
7142 arm_STRH_VC: "STRH.VC", | 8499 arm_STRH_VC: "STRH.VC", |
7143 arm_STRH_HI: "STRH.HI", | 8500 arm_STRH_HI: "STRH.HI", |
7144 arm_STRH_LS: "STRH.LS", | 8501 arm_STRH_LS: "STRH.LS", |
7145 arm_STRH_GE: "STRH.GE", | 8502 arm_STRH_GE: "STRH.GE", |
7146 arm_STRH_LT: "STRH.LT", | 8503 arm_STRH_LT: "STRH.LT", |
7147 arm_STRH_GT: "STRH.GT", | 8504 arm_STRH_GT: "STRH.GT", |
7148 arm_STRH_LE: "STRH.LE", | 8505 arm_STRH_LE: "STRH.LE", |
7149 arm_STRH: "STRH", | 8506 arm_STRH: "STRH", |
7150 arm_STRH_ZZ: "STRH.ZZ", | 8507 arm_STRH_ZZ: "STRH.ZZ", |
7151 arm_STRHT_EQ: "STRHT.EQ", | 8508 arm_STRHT_EQ: "STRHT.EQ", |
7152 arm_STRHT_NE: "STRHT.NE", | 8509 arm_STRHT_NE: "STRHT.NE", |
7153 arm_STRHT_CS: "STRHT.CS", | 8510 arm_STRHT_CS: "STRHT.CS", |
7154 arm_STRHT_CC: "STRHT.CC", | 8511 arm_STRHT_CC: "STRHT.CC", |
7155 arm_STRHT_MI: "STRHT.MI", | 8512 arm_STRHT_MI: "STRHT.MI", |
7156 arm_STRHT_PL: "STRHT.PL", | 8513 arm_STRHT_PL: "STRHT.PL", |
7157 arm_STRHT_VS: "STRHT.VS", | 8514 arm_STRHT_VS: "STRHT.VS", |
7158 arm_STRHT_VC: "STRHT.VC", | 8515 arm_STRHT_VC: "STRHT.VC", |
7159 arm_STRHT_HI: "STRHT.HI", | 8516 arm_STRHT_HI: "STRHT.HI", |
7160 arm_STRHT_LS: "STRHT.LS", | 8517 arm_STRHT_LS: "STRHT.LS", |
7161 arm_STRHT_GE: "STRHT.GE", | 8518 arm_STRHT_GE: "STRHT.GE", |
7162 arm_STRHT_LT: "STRHT.LT", | 8519 arm_STRHT_LT: "STRHT.LT", |
7163 arm_STRHT_GT: "STRHT.GT", | 8520 arm_STRHT_GT: "STRHT.GT", |
7164 arm_STRHT_LE: "STRHT.LE", | 8521 arm_STRHT_LE: "STRHT.LE", |
7165 arm_STRHT: "STRHT", | 8522 arm_STRHT: "STRHT", |
7166 arm_STRHT_ZZ: "STRHT.ZZ", | 8523 arm_STRHT_ZZ: "STRHT.ZZ", |
7167 arm_STRT_EQ: "STRT.EQ", | 8524 arm_STRT_EQ: "STRT.EQ", |
7168 arm_STRT_NE: "STRT.NE", | 8525 arm_STRT_NE: "STRT.NE", |
7169 arm_STRT_CS: "STRT.CS", | 8526 arm_STRT_CS: "STRT.CS", |
7170 arm_STRT_CC: "STRT.CC", | 8527 arm_STRT_CC: "STRT.CC", |
7171 arm_STRT_MI: "STRT.MI", | 8528 arm_STRT_MI: "STRT.MI", |
7172 arm_STRT_PL: "STRT.PL", | 8529 arm_STRT_PL: "STRT.PL", |
7173 arm_STRT_VS: "STRT.VS", | 8530 arm_STRT_VS: "STRT.VS", |
7174 arm_STRT_VC: "STRT.VC", | 8531 arm_STRT_VC: "STRT.VC", |
7175 arm_STRT_HI: "STRT.HI", | 8532 arm_STRT_HI: "STRT.HI", |
7176 arm_STRT_LS: "STRT.LS", | 8533 arm_STRT_LS: "STRT.LS", |
7177 arm_STRT_GE: "STRT.GE", | 8534 arm_STRT_GE: "STRT.GE", |
7178 arm_STRT_LT: "STRT.LT", | 8535 arm_STRT_LT: "STRT.LT", |
7179 arm_STRT_GT: "STRT.GT", | 8536 arm_STRT_GT: "STRT.GT", |
7180 arm_STRT_LE: "STRT.LE", | 8537 arm_STRT_LE: "STRT.LE", |
7181 arm_STRT: "STRT", | 8538 arm_STRT: "STRT", |
7182 arm_STRT_ZZ: "STRT.ZZ", | 8539 arm_STRT_ZZ: "STRT.ZZ", |
7183 arm_SUB_EQ: "SUB.EQ", | 8540 arm_SUB_EQ: "SUB.EQ", |
7184 arm_SUB_NE: "SUB.NE", | 8541 arm_SUB_NE: "SUB.NE", |
7185 arm_SUB_CS: "SUB.CS", | 8542 arm_SUB_CS: "SUB.CS", |
7186 arm_SUB_CC: "SUB.CC", | 8543 arm_SUB_CC: "SUB.CC", |
7187 arm_SUB_MI: "SUB.MI", | 8544 arm_SUB_MI: "SUB.MI", |
7188 arm_SUB_PL: "SUB.PL", | 8545 arm_SUB_PL: "SUB.PL", |
7189 arm_SUB_VS: "SUB.VS", | 8546 arm_SUB_VS: "SUB.VS", |
7190 arm_SUB_VC: "SUB.VC", | 8547 arm_SUB_VC: "SUB.VC", |
7191 arm_SUB_HI: "SUB.HI", | 8548 arm_SUB_HI: "SUB.HI", |
7192 arm_SUB_LS: "SUB.LS", | 8549 arm_SUB_LS: "SUB.LS", |
7193 arm_SUB_GE: "SUB.GE", | 8550 arm_SUB_GE: "SUB.GE", |
7194 arm_SUB_LT: "SUB.LT", | 8551 arm_SUB_LT: "SUB.LT", |
7195 arm_SUB_GT: "SUB.GT", | 8552 arm_SUB_GT: "SUB.GT", |
7196 arm_SUB_LE: "SUB.LE", | 8553 arm_SUB_LE: "SUB.LE", |
7197 arm_SUB: "SUB", | 8554 arm_SUB: "SUB", |
7198 arm_SUB_ZZ: "SUB.ZZ", | 8555 arm_SUB_ZZ: "SUB.ZZ", |
7199 arm_SUB_S_EQ: "SUB.S.EQ", | 8556 arm_SUB_S_EQ: "SUB.S.EQ", |
7200 arm_SUB_S_NE: "SUB.S.NE", | 8557 arm_SUB_S_NE: "SUB.S.NE", |
7201 arm_SUB_S_CS: "SUB.S.CS", | 8558 arm_SUB_S_CS: "SUB.S.CS", |
7202 arm_SUB_S_CC: "SUB.S.CC", | 8559 arm_SUB_S_CC: "SUB.S.CC", |
7203 arm_SUB_S_MI: "SUB.S.MI", | 8560 arm_SUB_S_MI: "SUB.S.MI", |
7204 arm_SUB_S_PL: "SUB.S.PL", | 8561 arm_SUB_S_PL: "SUB.S.PL", |
7205 arm_SUB_S_VS: "SUB.S.VS", | 8562 arm_SUB_S_VS: "SUB.S.VS", |
7206 arm_SUB_S_VC: "SUB.S.VC", | 8563 arm_SUB_S_VC: "SUB.S.VC", |
7207 arm_SUB_S_HI: "SUB.S.HI", | 8564 arm_SUB_S_HI: "SUB.S.HI", |
7208 arm_SUB_S_LS: "SUB.S.LS", | 8565 arm_SUB_S_LS: "SUB.S.LS", |
7209 arm_SUB_S_GE: "SUB.S.GE", | 8566 arm_SUB_S_GE: "SUB.S.GE", |
7210 arm_SUB_S_LT: "SUB.S.LT", | 8567 arm_SUB_S_LT: "SUB.S.LT", |
7211 arm_SUB_S_GT: "SUB.S.GT", | 8568 arm_SUB_S_GT: "SUB.S.GT", |
7212 arm_SUB_S_LE: "SUB.S.LE", | 8569 arm_SUB_S_LE: "SUB.S.LE", |
7213 arm_SUB_S: "SUB.S", | 8570 arm_SUB_S: "SUB.S", |
7214 arm_SUB_S_ZZ: "SUB.S.ZZ", | 8571 arm_SUB_S_ZZ: "SUB.S.ZZ", |
7215 arm_SVC_EQ: "SVC.EQ", | 8572 arm_SVC_EQ: "SVC.EQ", |
7216 arm_SVC_NE: "SVC.NE", | 8573 arm_SVC_NE: "SVC.NE", |
7217 arm_SVC_CS: "SVC.CS", | 8574 arm_SVC_CS: "SVC.CS", |
7218 arm_SVC_CC: "SVC.CC", | 8575 arm_SVC_CC: "SVC.CC", |
7219 arm_SVC_MI: "SVC.MI", | 8576 arm_SVC_MI: "SVC.MI", |
7220 arm_SVC_PL: "SVC.PL", | 8577 arm_SVC_PL: "SVC.PL", |
7221 arm_SVC_VS: "SVC.VS", | 8578 arm_SVC_VS: "SVC.VS", |
7222 arm_SVC_VC: "SVC.VC", | 8579 arm_SVC_VC: "SVC.VC", |
7223 arm_SVC_HI: "SVC.HI", | 8580 arm_SVC_HI: "SVC.HI", |
7224 arm_SVC_LS: "SVC.LS", | 8581 arm_SVC_LS: "SVC.LS", |
7225 arm_SVC_GE: "SVC.GE", | 8582 arm_SVC_GE: "SVC.GE", |
7226 arm_SVC_LT: "SVC.LT", | 8583 arm_SVC_LT: "SVC.LT", |
7227 arm_SVC_GT: "SVC.GT", | 8584 arm_SVC_GT: "SVC.GT", |
7228 arm_SVC_LE: "SVC.LE", | 8585 arm_SVC_LE: "SVC.LE", |
7229 arm_SVC: "SVC", | 8586 arm_SVC: "SVC", |
7230 arm_SVC_ZZ: "SVC.ZZ", | 8587 arm_SVC_ZZ: "SVC.ZZ", |
7231 arm_SWP_EQ: "SWP.EQ", | 8588 arm_SWP_EQ: "SWP.EQ", |
7232 arm_SWP_NE: "SWP.NE", | 8589 arm_SWP_NE: "SWP.NE", |
7233 arm_SWP_CS: "SWP.CS", | 8590 arm_SWP_CS: "SWP.CS", |
7234 arm_SWP_CC: "SWP.CC", | 8591 arm_SWP_CC: "SWP.CC", |
7235 arm_SWP_MI: "SWP.MI", | 8592 arm_SWP_MI: "SWP.MI", |
7236 arm_SWP_PL: "SWP.PL", | 8593 arm_SWP_PL: "SWP.PL", |
7237 arm_SWP_VS: "SWP.VS", | 8594 arm_SWP_VS: "SWP.VS", |
7238 arm_SWP_VC: "SWP.VC", | 8595 arm_SWP_VC: "SWP.VC", |
7239 arm_SWP_HI: "SWP.HI", | 8596 arm_SWP_HI: "SWP.HI", |
7240 arm_SWP_LS: "SWP.LS", | 8597 arm_SWP_LS: "SWP.LS", |
7241 arm_SWP_GE: "SWP.GE", | 8598 arm_SWP_GE: "SWP.GE", |
7242 arm_SWP_LT: "SWP.LT", | 8599 arm_SWP_LT: "SWP.LT", |
7243 arm_SWP_GT: "SWP.GT", | 8600 arm_SWP_GT: "SWP.GT", |
7244 arm_SWP_LE: "SWP.LE", | 8601 arm_SWP_LE: "SWP.LE", |
7245 arm_SWP: "SWP", | 8602 arm_SWP: "SWP", |
7246 arm_SWP_ZZ: "SWP.ZZ", | 8603 arm_SWP_ZZ: "SWP.ZZ", |
7247 arm_SWP_B_EQ: "SWP.B.EQ", | 8604 arm_SWP_B_EQ: "SWP.B.EQ", |
7248 arm_SWP_B_NE: "SWP.B.NE", | 8605 arm_SWP_B_NE: "SWP.B.NE", |
7249 arm_SWP_B_CS: "SWP.B.CS", | 8606 arm_SWP_B_CS: "SWP.B.CS", |
7250 arm_SWP_B_CC: "SWP.B.CC", | 8607 arm_SWP_B_CC: "SWP.B.CC", |
7251 arm_SWP_B_MI: "SWP.B.MI", | 8608 arm_SWP_B_MI: "SWP.B.MI", |
7252 arm_SWP_B_PL: "SWP.B.PL", | 8609 arm_SWP_B_PL: "SWP.B.PL", |
7253 arm_SWP_B_VS: "SWP.B.VS", | 8610 arm_SWP_B_VS: "SWP.B.VS", |
7254 arm_SWP_B_VC: "SWP.B.VC", | 8611 arm_SWP_B_VC: "SWP.B.VC", |
7255 arm_SWP_B_HI: "SWP.B.HI", | 8612 arm_SWP_B_HI: "SWP.B.HI", |
7256 arm_SWP_B_LS: "SWP.B.LS", | 8613 arm_SWP_B_LS: "SWP.B.LS", |
7257 arm_SWP_B_GE: "SWP.B.GE", | 8614 arm_SWP_B_GE: "SWP.B.GE", |
7258 arm_SWP_B_LT: "SWP.B.LT", | 8615 arm_SWP_B_LT: "SWP.B.LT", |
7259 arm_SWP_B_GT: "SWP.B.GT", | 8616 arm_SWP_B_GT: "SWP.B.GT", |
7260 arm_SWP_B_LE: "SWP.B.LE", | 8617 arm_SWP_B_LE: "SWP.B.LE", |
7261 arm_SWP_B: "SWP.B", | 8618 arm_SWP_B: "SWP.B", |
7262 arm_SWP_B_ZZ: "SWP.B.ZZ", | 8619 arm_SWP_B_ZZ: "SWP.B.ZZ", |
7263 arm_SXTAB_EQ: "SXTAB.EQ", | 8620 arm_SXTAB_EQ: "SXTAB.EQ", |
7264 arm_SXTAB_NE: "SXTAB.NE", | 8621 arm_SXTAB_NE: "SXTAB.NE", |
7265 arm_SXTAB_CS: "SXTAB.CS", | 8622 arm_SXTAB_CS: "SXTAB.CS", |
7266 arm_SXTAB_CC: "SXTAB.CC", | 8623 arm_SXTAB_CC: "SXTAB.CC", |
7267 arm_SXTAB_MI: "SXTAB.MI", | 8624 arm_SXTAB_MI: "SXTAB.MI", |
7268 arm_SXTAB_PL: "SXTAB.PL", | 8625 arm_SXTAB_PL: "SXTAB.PL", |
7269 arm_SXTAB_VS: "SXTAB.VS", | 8626 arm_SXTAB_VS: "SXTAB.VS", |
7270 arm_SXTAB_VC: "SXTAB.VC", | 8627 arm_SXTAB_VC: "SXTAB.VC", |
7271 arm_SXTAB_HI: "SXTAB.HI", | 8628 arm_SXTAB_HI: "SXTAB.HI", |
7272 arm_SXTAB_LS: "SXTAB.LS", | 8629 arm_SXTAB_LS: "SXTAB.LS", |
7273 arm_SXTAB_GE: "SXTAB.GE", | 8630 arm_SXTAB_GE: "SXTAB.GE", |
7274 arm_SXTAB_LT: "SXTAB.LT", | 8631 arm_SXTAB_LT: "SXTAB.LT", |
7275 arm_SXTAB_GT: "SXTAB.GT", | 8632 arm_SXTAB_GT: "SXTAB.GT", |
7276 arm_SXTAB_LE: "SXTAB.LE", | 8633 arm_SXTAB_LE: "SXTAB.LE", |
7277 arm_SXTAB: "SXTAB", | 8634 arm_SXTAB: "SXTAB", |
7278 arm_SXTAB_ZZ: "SXTAB.ZZ", | 8635 arm_SXTAB_ZZ: "SXTAB.ZZ", |
7279 arm_SXTAB16_EQ: "SXTAB16.EQ", | 8636 arm_SXTAB16_EQ: "SXTAB16.EQ", |
7280 arm_SXTAB16_NE: "SXTAB16.NE", | 8637 arm_SXTAB16_NE: "SXTAB16.NE", |
7281 arm_SXTAB16_CS: "SXTAB16.CS", | 8638 arm_SXTAB16_CS: "SXTAB16.CS", |
7282 arm_SXTAB16_CC: "SXTAB16.CC", | 8639 arm_SXTAB16_CC: "SXTAB16.CC", |
7283 arm_SXTAB16_MI: "SXTAB16.MI", | 8640 arm_SXTAB16_MI: "SXTAB16.MI", |
7284 arm_SXTAB16_PL: "SXTAB16.PL", | 8641 arm_SXTAB16_PL: "SXTAB16.PL", |
7285 arm_SXTAB16_VS: "SXTAB16.VS", | 8642 arm_SXTAB16_VS: "SXTAB16.VS", |
7286 arm_SXTAB16_VC: "SXTAB16.VC", | 8643 arm_SXTAB16_VC: "SXTAB16.VC", |
7287 arm_SXTAB16_HI: "SXTAB16.HI", | 8644 arm_SXTAB16_HI: "SXTAB16.HI", |
7288 arm_SXTAB16_LS: "SXTAB16.LS", | 8645 arm_SXTAB16_LS: "SXTAB16.LS", |
7289 arm_SXTAB16_GE: "SXTAB16.GE", | 8646 arm_SXTAB16_GE: "SXTAB16.GE", |
7290 arm_SXTAB16_LT: "SXTAB16.LT", | 8647 arm_SXTAB16_LT: "SXTAB16.LT", |
7291 arm_SXTAB16_GT: "SXTAB16.GT", | 8648 arm_SXTAB16_GT: "SXTAB16.GT", |
7292 arm_SXTAB16_LE: "SXTAB16.LE", | 8649 arm_SXTAB16_LE: "SXTAB16.LE", |
7293 arm_SXTAB16: "SXTAB16", | 8650 arm_SXTAB16: "SXTAB16", |
7294 arm_SXTAB16_ZZ: "SXTAB16.ZZ", | 8651 arm_SXTAB16_ZZ: "SXTAB16.ZZ", |
7295 arm_SXTAH_EQ: "SXTAH.EQ", | 8652 arm_SXTAH_EQ: "SXTAH.EQ", |
7296 arm_SXTAH_NE: "SXTAH.NE", | 8653 arm_SXTAH_NE: "SXTAH.NE", |
7297 arm_SXTAH_CS: "SXTAH.CS", | 8654 arm_SXTAH_CS: "SXTAH.CS", |
7298 arm_SXTAH_CC: "SXTAH.CC", | 8655 arm_SXTAH_CC: "SXTAH.CC", |
7299 arm_SXTAH_MI: "SXTAH.MI", | 8656 arm_SXTAH_MI: "SXTAH.MI", |
7300 arm_SXTAH_PL: "SXTAH.PL", | 8657 arm_SXTAH_PL: "SXTAH.PL", |
7301 arm_SXTAH_VS: "SXTAH.VS", | 8658 arm_SXTAH_VS: "SXTAH.VS", |
7302 arm_SXTAH_VC: "SXTAH.VC", | 8659 arm_SXTAH_VC: "SXTAH.VC", |
7303 arm_SXTAH_HI: "SXTAH.HI", | 8660 arm_SXTAH_HI: "SXTAH.HI", |
7304 arm_SXTAH_LS: "SXTAH.LS", | 8661 arm_SXTAH_LS: "SXTAH.LS", |
7305 arm_SXTAH_GE: "SXTAH.GE", | 8662 arm_SXTAH_GE: "SXTAH.GE", |
7306 arm_SXTAH_LT: "SXTAH.LT", | 8663 arm_SXTAH_LT: "SXTAH.LT", |
7307 arm_SXTAH_GT: "SXTAH.GT", | 8664 arm_SXTAH_GT: "SXTAH.GT", |
7308 arm_SXTAH_LE: "SXTAH.LE", | 8665 arm_SXTAH_LE: "SXTAH.LE", |
7309 arm_SXTAH: "SXTAH", | 8666 arm_SXTAH: "SXTAH", |
7310 arm_SXTAH_ZZ: "SXTAH.ZZ", | 8667 arm_SXTAH_ZZ: "SXTAH.ZZ", |
7311 arm_SXTB_EQ: "SXTB.EQ", | 8668 arm_SXTB_EQ: "SXTB.EQ", |
7312 arm_SXTB_NE: "SXTB.NE", | 8669 arm_SXTB_NE: "SXTB.NE", |
7313 arm_SXTB_CS: "SXTB.CS", | 8670 arm_SXTB_CS: "SXTB.CS", |
7314 arm_SXTB_CC: "SXTB.CC", | 8671 arm_SXTB_CC: "SXTB.CC", |
7315 arm_SXTB_MI: "SXTB.MI", | 8672 arm_SXTB_MI: "SXTB.MI", |
7316 arm_SXTB_PL: "SXTB.PL", | 8673 arm_SXTB_PL: "SXTB.PL", |
7317 arm_SXTB_VS: "SXTB.VS", | 8674 arm_SXTB_VS: "SXTB.VS", |
7318 arm_SXTB_VC: "SXTB.VC", | 8675 arm_SXTB_VC: "SXTB.VC", |
7319 arm_SXTB_HI: "SXTB.HI", | 8676 arm_SXTB_HI: "SXTB.HI", |
7320 arm_SXTB_LS: "SXTB.LS", | 8677 arm_SXTB_LS: "SXTB.LS", |
7321 arm_SXTB_GE: "SXTB.GE", | 8678 arm_SXTB_GE: "SXTB.GE", |
7322 arm_SXTB_LT: "SXTB.LT", | 8679 arm_SXTB_LT: "SXTB.LT", |
7323 arm_SXTB_GT: "SXTB.GT", | 8680 arm_SXTB_GT: "SXTB.GT", |
7324 arm_SXTB_LE: "SXTB.LE", | 8681 arm_SXTB_LE: "SXTB.LE", |
7325 arm_SXTB: "SXTB", | 8682 arm_SXTB: "SXTB", |
7326 arm_SXTB_ZZ: "SXTB.ZZ", | 8683 arm_SXTB_ZZ: "SXTB.ZZ", |
7327 arm_SXTB16_EQ: "SXTB16.EQ", | 8684 arm_SXTB16_EQ: "SXTB16.EQ", |
7328 arm_SXTB16_NE: "SXTB16.NE", | 8685 arm_SXTB16_NE: "SXTB16.NE", |
7329 arm_SXTB16_CS: "SXTB16.CS", | 8686 arm_SXTB16_CS: "SXTB16.CS", |
7330 arm_SXTB16_CC: "SXTB16.CC", | 8687 arm_SXTB16_CC: "SXTB16.CC", |
7331 arm_SXTB16_MI: "SXTB16.MI", | 8688 arm_SXTB16_MI: "SXTB16.MI", |
7332 arm_SXTB16_PL: "SXTB16.PL", | 8689 arm_SXTB16_PL: "SXTB16.PL", |
7333 arm_SXTB16_VS: "SXTB16.VS", | 8690 arm_SXTB16_VS: "SXTB16.VS", |
7334 arm_SXTB16_VC: "SXTB16.VC", | 8691 arm_SXTB16_VC: "SXTB16.VC", |
7335 arm_SXTB16_HI: "SXTB16.HI", | 8692 arm_SXTB16_HI: "SXTB16.HI", |
7336 arm_SXTB16_LS: "SXTB16.LS", | 8693 arm_SXTB16_LS: "SXTB16.LS", |
7337 arm_SXTB16_GE: "SXTB16.GE", | 8694 arm_SXTB16_GE: "SXTB16.GE", |
7338 arm_SXTB16_LT: "SXTB16.LT", | 8695 arm_SXTB16_LT: "SXTB16.LT", |
7339 arm_SXTB16_GT: "SXTB16.GT", | 8696 arm_SXTB16_GT: "SXTB16.GT", |
7340 arm_SXTB16_LE: "SXTB16.LE", | 8697 arm_SXTB16_LE: "SXTB16.LE", |
7341 arm_SXTB16: "SXTB16", | 8698 arm_SXTB16: "SXTB16", |
7342 arm_SXTB16_ZZ: "SXTB16.ZZ", | 8699 arm_SXTB16_ZZ: "SXTB16.ZZ", |
7343 arm_SXTH_EQ: "SXTH.EQ", | 8700 arm_SXTH_EQ: "SXTH.EQ", |
7344 arm_SXTH_NE: "SXTH.NE", | 8701 arm_SXTH_NE: "SXTH.NE", |
7345 arm_SXTH_CS: "SXTH.CS", | 8702 arm_SXTH_CS: "SXTH.CS", |
7346 arm_SXTH_CC: "SXTH.CC", | 8703 arm_SXTH_CC: "SXTH.CC", |
7347 arm_SXTH_MI: "SXTH.MI", | 8704 arm_SXTH_MI: "SXTH.MI", |
7348 arm_SXTH_PL: "SXTH.PL", | 8705 arm_SXTH_PL: "SXTH.PL", |
7349 arm_SXTH_VS: "SXTH.VS", | 8706 arm_SXTH_VS: "SXTH.VS", |
7350 arm_SXTH_VC: "SXTH.VC", | 8707 arm_SXTH_VC: "SXTH.VC", |
7351 arm_SXTH_HI: "SXTH.HI", | 8708 arm_SXTH_HI: "SXTH.HI", |
7352 arm_SXTH_LS: "SXTH.LS", | 8709 arm_SXTH_LS: "SXTH.LS", |
7353 arm_SXTH_GE: "SXTH.GE", | 8710 arm_SXTH_GE: "SXTH.GE", |
7354 arm_SXTH_LT: "SXTH.LT", | 8711 arm_SXTH_LT: "SXTH.LT", |
7355 arm_SXTH_GT: "SXTH.GT", | 8712 arm_SXTH_GT: "SXTH.GT", |
7356 arm_SXTH_LE: "SXTH.LE", | 8713 arm_SXTH_LE: "SXTH.LE", |
7357 arm_SXTH: "SXTH", | 8714 arm_SXTH: "SXTH", |
7358 arm_SXTH_ZZ: "SXTH.ZZ", | 8715 arm_SXTH_ZZ: "SXTH.ZZ", |
7359 arm_TEQ_EQ: "TEQ.EQ", | 8716 arm_TEQ_EQ: "TEQ.EQ", |
7360 arm_TEQ_NE: "TEQ.NE", | 8717 arm_TEQ_NE: "TEQ.NE", |
7361 arm_TEQ_CS: "TEQ.CS", | 8718 arm_TEQ_CS: "TEQ.CS", |
7362 arm_TEQ_CC: "TEQ.CC", | 8719 arm_TEQ_CC: "TEQ.CC", |
7363 arm_TEQ_MI: "TEQ.MI", | 8720 arm_TEQ_MI: "TEQ.MI", |
7364 arm_TEQ_PL: "TEQ.PL", | 8721 arm_TEQ_PL: "TEQ.PL", |
7365 arm_TEQ_VS: "TEQ.VS", | 8722 arm_TEQ_VS: "TEQ.VS", |
7366 arm_TEQ_VC: "TEQ.VC", | 8723 arm_TEQ_VC: "TEQ.VC", |
7367 arm_TEQ_HI: "TEQ.HI", | 8724 arm_TEQ_HI: "TEQ.HI", |
7368 arm_TEQ_LS: "TEQ.LS", | 8725 arm_TEQ_LS: "TEQ.LS", |
7369 arm_TEQ_GE: "TEQ.GE", | 8726 arm_TEQ_GE: "TEQ.GE", |
7370 arm_TEQ_LT: "TEQ.LT", | 8727 arm_TEQ_LT: "TEQ.LT", |
7371 arm_TEQ_GT: "TEQ.GT", | 8728 arm_TEQ_GT: "TEQ.GT", |
7372 arm_TEQ_LE: "TEQ.LE", | 8729 arm_TEQ_LE: "TEQ.LE", |
7373 arm_TEQ: "TEQ", | 8730 arm_TEQ: "TEQ", |
7374 arm_TEQ_ZZ: "TEQ.ZZ", | 8731 arm_TEQ_ZZ: "TEQ.ZZ", |
7375 arm_TST_EQ: "TST.EQ", | 8732 arm_TST_EQ: "TST.EQ", |
7376 arm_TST_NE: "TST.NE", | 8733 arm_TST_NE: "TST.NE", |
7377 arm_TST_CS: "TST.CS", | 8734 arm_TST_CS: "TST.CS", |
7378 arm_TST_CC: "TST.CC", | 8735 arm_TST_CC: "TST.CC", |
7379 arm_TST_MI: "TST.MI", | 8736 arm_TST_MI: "TST.MI", |
7380 arm_TST_PL: "TST.PL", | 8737 arm_TST_PL: "TST.PL", |
7381 arm_TST_VS: "TST.VS", | 8738 arm_TST_VS: "TST.VS", |
7382 arm_TST_VC: "TST.VC", | 8739 arm_TST_VC: "TST.VC", |
7383 arm_TST_HI: "TST.HI", | 8740 arm_TST_HI: "TST.HI", |
7384 arm_TST_LS: "TST.LS", | 8741 arm_TST_LS: "TST.LS", |
7385 arm_TST_GE: "TST.GE", | 8742 arm_TST_GE: "TST.GE", |
7386 arm_TST_LT: "TST.LT", | 8743 arm_TST_LT: "TST.LT", |
7387 arm_TST_GT: "TST.GT", | 8744 arm_TST_GT: "TST.GT", |
7388 arm_TST_LE: "TST.LE", | 8745 arm_TST_LE: "TST.LE", |
7389 arm_TST: "TST", | 8746 arm_TST: "TST", |
7390 arm_TST_ZZ: "TST.ZZ", | 8747 arm_TST_ZZ: "TST.ZZ", |
7391 arm_UADD16_EQ: "UADD16.EQ", | 8748 arm_UADD16_EQ: "UADD16.EQ", |
7392 arm_UADD16_NE: "UADD16.NE", | 8749 arm_UADD16_NE: "UADD16.NE", |
7393 arm_UADD16_CS: "UADD16.CS", | 8750 arm_UADD16_CS: "UADD16.CS", |
7394 arm_UADD16_CC: "UADD16.CC", | 8751 arm_UADD16_CC: "UADD16.CC", |
7395 arm_UADD16_MI: "UADD16.MI", | 8752 arm_UADD16_MI: "UADD16.MI", |
7396 arm_UADD16_PL: "UADD16.PL", | 8753 arm_UADD16_PL: "UADD16.PL", |
7397 arm_UADD16_VS: "UADD16.VS", | 8754 arm_UADD16_VS: "UADD16.VS", |
7398 arm_UADD16_VC: "UADD16.VC", | 8755 arm_UADD16_VC: "UADD16.VC", |
7399 arm_UADD16_HI: "UADD16.HI", | 8756 arm_UADD16_HI: "UADD16.HI", |
7400 arm_UADD16_LS: "UADD16.LS", | 8757 arm_UADD16_LS: "UADD16.LS", |
7401 arm_UADD16_GE: "UADD16.GE", | 8758 arm_UADD16_GE: "UADD16.GE", |
7402 arm_UADD16_LT: "UADD16.LT", | 8759 arm_UADD16_LT: "UADD16.LT", |
7403 arm_UADD16_GT: "UADD16.GT", | 8760 arm_UADD16_GT: "UADD16.GT", |
7404 arm_UADD16_LE: "UADD16.LE", | 8761 arm_UADD16_LE: "UADD16.LE", |
7405 arm_UADD16: "UADD16", | 8762 arm_UADD16: "UADD16", |
7406 arm_UADD16_ZZ: "UADD16.ZZ", | 8763 arm_UADD16_ZZ: "UADD16.ZZ", |
7407 arm_UADD8_EQ: "UADD8.EQ", | 8764 arm_UADD8_EQ: "UADD8.EQ", |
7408 arm_UADD8_NE: "UADD8.NE", | 8765 arm_UADD8_NE: "UADD8.NE", |
7409 arm_UADD8_CS: "UADD8.CS", | 8766 arm_UADD8_CS: "UADD8.CS", |
7410 arm_UADD8_CC: "UADD8.CC", | 8767 arm_UADD8_CC: "UADD8.CC", |
7411 arm_UADD8_MI: "UADD8.MI", | 8768 arm_UADD8_MI: "UADD8.MI", |
7412 arm_UADD8_PL: "UADD8.PL", | 8769 arm_UADD8_PL: "UADD8.PL", |
7413 arm_UADD8_VS: "UADD8.VS", | 8770 arm_UADD8_VS: "UADD8.VS", |
7414 arm_UADD8_VC: "UADD8.VC", | 8771 arm_UADD8_VC: "UADD8.VC", |
7415 arm_UADD8_HI: "UADD8.HI", | 8772 arm_UADD8_HI: "UADD8.HI", |
7416 arm_UADD8_LS: "UADD8.LS", | 8773 arm_UADD8_LS: "UADD8.LS", |
7417 arm_UADD8_GE: "UADD8.GE", | 8774 arm_UADD8_GE: "UADD8.GE", |
7418 arm_UADD8_LT: "UADD8.LT", | 8775 arm_UADD8_LT: "UADD8.LT", |
7419 arm_UADD8_GT: "UADD8.GT", | 8776 arm_UADD8_GT: "UADD8.GT", |
7420 arm_UADD8_LE: "UADD8.LE", | 8777 arm_UADD8_LE: "UADD8.LE", |
7421 arm_UADD8: "UADD8", | 8778 arm_UADD8: "UADD8", |
7422 arm_UADD8_ZZ: "UADD8.ZZ", | 8779 arm_UADD8_ZZ: "UADD8.ZZ", |
7423 arm_UASX_EQ: "UASX.EQ", | 8780 arm_UASX_EQ: "UASX.EQ", |
7424 arm_UASX_NE: "UASX.NE", | 8781 arm_UASX_NE: "UASX.NE", |
7425 arm_UASX_CS: "UASX.CS", | 8782 arm_UASX_CS: "UASX.CS", |
7426 arm_UASX_CC: "UASX.CC", | 8783 arm_UASX_CC: "UASX.CC", |
7427 arm_UASX_MI: "UASX.MI", | 8784 arm_UASX_MI: "UASX.MI", |
7428 arm_UASX_PL: "UASX.PL", | 8785 arm_UASX_PL: "UASX.PL", |
7429 arm_UASX_VS: "UASX.VS", | 8786 arm_UASX_VS: "UASX.VS", |
7430 arm_UASX_VC: "UASX.VC", | 8787 arm_UASX_VC: "UASX.VC", |
7431 arm_UASX_HI: "UASX.HI", | 8788 arm_UASX_HI: "UASX.HI", |
7432 arm_UASX_LS: "UASX.LS", | 8789 arm_UASX_LS: "UASX.LS", |
7433 arm_UASX_GE: "UASX.GE", | 8790 arm_UASX_GE: "UASX.GE", |
7434 arm_UASX_LT: "UASX.LT", | 8791 arm_UASX_LT: "UASX.LT", |
7435 arm_UASX_GT: "UASX.GT", | 8792 arm_UASX_GT: "UASX.GT", |
7436 arm_UASX_LE: "UASX.LE", | 8793 arm_UASX_LE: "UASX.LE", |
7437 arm_UASX: "UASX", | 8794 arm_UASX: "UASX", |
7438 arm_UASX_ZZ: "UASX.ZZ", | 8795 arm_UASX_ZZ: "UASX.ZZ", |
7439 arm_UBFX_EQ: "UBFX.EQ", | 8796 arm_UBFX_EQ: "UBFX.EQ", |
7440 arm_UBFX_NE: "UBFX.NE", | 8797 arm_UBFX_NE: "UBFX.NE", |
7441 arm_UBFX_CS: "UBFX.CS", | 8798 arm_UBFX_CS: "UBFX.CS", |
7442 arm_UBFX_CC: "UBFX.CC", | 8799 arm_UBFX_CC: "UBFX.CC", |
7443 arm_UBFX_MI: "UBFX.MI", | 8800 arm_UBFX_MI: "UBFX.MI", |
7444 arm_UBFX_PL: "UBFX.PL", | 8801 arm_UBFX_PL: "UBFX.PL", |
7445 arm_UBFX_VS: "UBFX.VS", | 8802 arm_UBFX_VS: "UBFX.VS", |
7446 arm_UBFX_VC: "UBFX.VC", | 8803 arm_UBFX_VC: "UBFX.VC", |
7447 arm_UBFX_HI: "UBFX.HI", | 8804 arm_UBFX_HI: "UBFX.HI", |
7448 arm_UBFX_LS: "UBFX.LS", | 8805 arm_UBFX_LS: "UBFX.LS", |
7449 arm_UBFX_GE: "UBFX.GE", | 8806 arm_UBFX_GE: "UBFX.GE", |
7450 arm_UBFX_LT: "UBFX.LT", | 8807 arm_UBFX_LT: "UBFX.LT", |
7451 arm_UBFX_GT: "UBFX.GT", | 8808 arm_UBFX_GT: "UBFX.GT", |
7452 arm_UBFX_LE: "UBFX.LE", | 8809 arm_UBFX_LE: "UBFX.LE", |
7453 arm_UBFX: "UBFX", | 8810 arm_UBFX: "UBFX", |
7454 arm_UBFX_ZZ: "UBFX.ZZ", | 8811 arm_UBFX_ZZ: "UBFX.ZZ", |
7455 arm_UHADD16_EQ: "UHADD16.EQ", | 8812 arm_UHADD16_EQ: "UHADD16.EQ", |
7456 arm_UHADD16_NE: "UHADD16.NE", | 8813 arm_UHADD16_NE: "UHADD16.NE", |
7457 arm_UHADD16_CS: "UHADD16.CS", | 8814 arm_UHADD16_CS: "UHADD16.CS", |
7458 arm_UHADD16_CC: "UHADD16.CC", | 8815 arm_UHADD16_CC: "UHADD16.CC", |
7459 arm_UHADD16_MI: "UHADD16.MI", | 8816 arm_UHADD16_MI: "UHADD16.MI", |
7460 arm_UHADD16_PL: "UHADD16.PL", | 8817 arm_UHADD16_PL: "UHADD16.PL", |
7461 arm_UHADD16_VS: "UHADD16.VS", | 8818 arm_UHADD16_VS: "UHADD16.VS", |
7462 arm_UHADD16_VC: "UHADD16.VC", | 8819 arm_UHADD16_VC: "UHADD16.VC", |
7463 arm_UHADD16_HI: "UHADD16.HI", | 8820 arm_UHADD16_HI: "UHADD16.HI", |
7464 arm_UHADD16_LS: "UHADD16.LS", | 8821 arm_UHADD16_LS: "UHADD16.LS", |
7465 arm_UHADD16_GE: "UHADD16.GE", | 8822 arm_UHADD16_GE: "UHADD16.GE", |
7466 arm_UHADD16_LT: "UHADD16.LT", | 8823 arm_UHADD16_LT: "UHADD16.LT", |
7467 arm_UHADD16_GT: "UHADD16.GT", | 8824 arm_UHADD16_GT: "UHADD16.GT", |
7468 arm_UHADD16_LE: "UHADD16.LE", | 8825 arm_UHADD16_LE: "UHADD16.LE", |
7469 arm_UHADD16: "UHADD16", | 8826 arm_UHADD16: "UHADD16", |
7470 arm_UHADD16_ZZ: "UHADD16.ZZ", | 8827 arm_UHADD16_ZZ: "UHADD16.ZZ", |
7471 arm_UHADD8_EQ: "UHADD8.EQ", | 8828 arm_UHADD8_EQ: "UHADD8.EQ", |
7472 arm_UHADD8_NE: "UHADD8.NE", | 8829 arm_UHADD8_NE: "UHADD8.NE", |
7473 arm_UHADD8_CS: "UHADD8.CS", | 8830 arm_UHADD8_CS: "UHADD8.CS", |
7474 arm_UHADD8_CC: "UHADD8.CC", | 8831 arm_UHADD8_CC: "UHADD8.CC", |
7475 arm_UHADD8_MI: "UHADD8.MI", | 8832 arm_UHADD8_MI: "UHADD8.MI", |
7476 arm_UHADD8_PL: "UHADD8.PL", | 8833 arm_UHADD8_PL: "UHADD8.PL", |
7477 arm_UHADD8_VS: "UHADD8.VS", | 8834 arm_UHADD8_VS: "UHADD8.VS", |
7478 arm_UHADD8_VC: "UHADD8.VC", | 8835 arm_UHADD8_VC: "UHADD8.VC", |
7479 arm_UHADD8_HI: "UHADD8.HI", | 8836 arm_UHADD8_HI: "UHADD8.HI", |
7480 arm_UHADD8_LS: "UHADD8.LS", | 8837 arm_UHADD8_LS: "UHADD8.LS", |
7481 arm_UHADD8_GE: "UHADD8.GE", | 8838 arm_UHADD8_GE: "UHADD8.GE", |
7482 arm_UHADD8_LT: "UHADD8.LT", | 8839 arm_UHADD8_LT: "UHADD8.LT", |
7483 arm_UHADD8_GT: "UHADD8.GT", | 8840 arm_UHADD8_GT: "UHADD8.GT", |
7484 arm_UHADD8_LE: "UHADD8.LE", | 8841 arm_UHADD8_LE: "UHADD8.LE", |
7485 arm_UHADD8: "UHADD8", | 8842 arm_UHADD8: "UHADD8", |
7486 arm_UHADD8_ZZ: "UHADD8.ZZ", | 8843 arm_UHADD8_ZZ: "UHADD8.ZZ", |
7487 arm_UHASX_EQ: "UHASX.EQ", | 8844 arm_UHASX_EQ: "UHASX.EQ", |
7488 arm_UHASX_NE: "UHASX.NE", | 8845 arm_UHASX_NE: "UHASX.NE", |
7489 arm_UHASX_CS: "UHASX.CS", | 8846 arm_UHASX_CS: "UHASX.CS", |
7490 arm_UHASX_CC: "UHASX.CC", | 8847 arm_UHASX_CC: "UHASX.CC", |
7491 arm_UHASX_MI: "UHASX.MI", | 8848 arm_UHASX_MI: "UHASX.MI", |
7492 arm_UHASX_PL: "UHASX.PL", | 8849 arm_UHASX_PL: "UHASX.PL", |
7493 arm_UHASX_VS: "UHASX.VS", | 8850 arm_UHASX_VS: "UHASX.VS", |
7494 arm_UHASX_VC: "UHASX.VC", | 8851 arm_UHASX_VC: "UHASX.VC", |
7495 arm_UHASX_HI: "UHASX.HI", | 8852 arm_UHASX_HI: "UHASX.HI", |
7496 arm_UHASX_LS: "UHASX.LS", | 8853 arm_UHASX_LS: "UHASX.LS", |
7497 arm_UHASX_GE: "UHASX.GE", | 8854 arm_UHASX_GE: "UHASX.GE", |
7498 arm_UHASX_LT: "UHASX.LT", | 8855 arm_UHASX_LT: "UHASX.LT", |
7499 arm_UHASX_GT: "UHASX.GT", | 8856 arm_UHASX_GT: "UHASX.GT", |
7500 arm_UHASX_LE: "UHASX.LE", | 8857 arm_UHASX_LE: "UHASX.LE", |
7501 arm_UHASX: "UHASX", | 8858 arm_UHASX: "UHASX", |
7502 arm_UHASX_ZZ: "UHASX.ZZ", | 8859 arm_UHASX_ZZ: "UHASX.ZZ", |
7503 arm_UHSAX_EQ: "UHSAX.EQ", | 8860 arm_UHSAX_EQ: "UHSAX.EQ", |
7504 arm_UHSAX_NE: "UHSAX.NE", | 8861 arm_UHSAX_NE: "UHSAX.NE", |
7505 arm_UHSAX_CS: "UHSAX.CS", | 8862 arm_UHSAX_CS: "UHSAX.CS", |
7506 arm_UHSAX_CC: "UHSAX.CC", | 8863 arm_UHSAX_CC: "UHSAX.CC", |
7507 arm_UHSAX_MI: "UHSAX.MI", | 8864 arm_UHSAX_MI: "UHSAX.MI", |
7508 arm_UHSAX_PL: "UHSAX.PL", | 8865 arm_UHSAX_PL: "UHSAX.PL", |
7509 arm_UHSAX_VS: "UHSAX.VS", | 8866 arm_UHSAX_VS: "UHSAX.VS", |
7510 arm_UHSAX_VC: "UHSAX.VC", | 8867 arm_UHSAX_VC: "UHSAX.VC", |
7511 arm_UHSAX_HI: "UHSAX.HI", | 8868 arm_UHSAX_HI: "UHSAX.HI", |
7512 arm_UHSAX_LS: "UHSAX.LS", | 8869 arm_UHSAX_LS: "UHSAX.LS", |
7513 arm_UHSAX_GE: "UHSAX.GE", | 8870 arm_UHSAX_GE: "UHSAX.GE", |
7514 arm_UHSAX_LT: "UHSAX.LT", | 8871 arm_UHSAX_LT: "UHSAX.LT", |
7515 arm_UHSAX_GT: "UHSAX.GT", | 8872 arm_UHSAX_GT: "UHSAX.GT", |
7516 arm_UHSAX_LE: "UHSAX.LE", | 8873 arm_UHSAX_LE: "UHSAX.LE", |
7517 arm_UHSAX: "UHSAX", | 8874 arm_UHSAX: "UHSAX", |
7518 arm_UHSAX_ZZ: "UHSAX.ZZ", | 8875 arm_UHSAX_ZZ: "UHSAX.ZZ", |
7519 arm_UHSUB16_EQ: "UHSUB16.EQ", | 8876 arm_UHSUB16_EQ: "UHSUB16.EQ", |
7520 arm_UHSUB16_NE: "UHSUB16.NE", | 8877 arm_UHSUB16_NE: "UHSUB16.NE", |
7521 arm_UHSUB16_CS: "UHSUB16.CS", | 8878 arm_UHSUB16_CS: "UHSUB16.CS", |
7522 arm_UHSUB16_CC: "UHSUB16.CC", | 8879 arm_UHSUB16_CC: "UHSUB16.CC", |
7523 arm_UHSUB16_MI: "UHSUB16.MI", | 8880 arm_UHSUB16_MI: "UHSUB16.MI", |
7524 arm_UHSUB16_PL: "UHSUB16.PL", | 8881 arm_UHSUB16_PL: "UHSUB16.PL", |
7525 arm_UHSUB16_VS: "UHSUB16.VS", | 8882 arm_UHSUB16_VS: "UHSUB16.VS", |
7526 arm_UHSUB16_VC: "UHSUB16.VC", | 8883 arm_UHSUB16_VC: "UHSUB16.VC", |
7527 arm_UHSUB16_HI: "UHSUB16.HI", | 8884 arm_UHSUB16_HI: "UHSUB16.HI", |
7528 arm_UHSUB16_LS: "UHSUB16.LS", | 8885 arm_UHSUB16_LS: "UHSUB16.LS", |
7529 arm_UHSUB16_GE: "UHSUB16.GE", | 8886 arm_UHSUB16_GE: "UHSUB16.GE", |
7530 arm_UHSUB16_LT: "UHSUB16.LT", | 8887 arm_UHSUB16_LT: "UHSUB16.LT", |
7531 arm_UHSUB16_GT: "UHSUB16.GT", | 8888 arm_UHSUB16_GT: "UHSUB16.GT", |
7532 arm_UHSUB16_LE: "UHSUB16.LE", | 8889 arm_UHSUB16_LE: "UHSUB16.LE", |
7533 arm_UHSUB16: "UHSUB16", | 8890 arm_UHSUB16: "UHSUB16", |
7534 arm_UHSUB16_ZZ: "UHSUB16.ZZ", | 8891 arm_UHSUB16_ZZ: "UHSUB16.ZZ", |
7535 arm_UHSUB8_EQ: "UHSUB8.EQ", | 8892 arm_UHSUB8_EQ: "UHSUB8.EQ", |
7536 arm_UHSUB8_NE: "UHSUB8.NE", | 8893 arm_UHSUB8_NE: "UHSUB8.NE", |
7537 arm_UHSUB8_CS: "UHSUB8.CS", | 8894 arm_UHSUB8_CS: "UHSUB8.CS", |
7538 arm_UHSUB8_CC: "UHSUB8.CC", | 8895 arm_UHSUB8_CC: "UHSUB8.CC", |
7539 arm_UHSUB8_MI: "UHSUB8.MI", | 8896 arm_UHSUB8_MI: "UHSUB8.MI", |
7540 arm_UHSUB8_PL: "UHSUB8.PL", | 8897 arm_UHSUB8_PL: "UHSUB8.PL", |
7541 arm_UHSUB8_VS: "UHSUB8.VS", | 8898 arm_UHSUB8_VS: "UHSUB8.VS", |
7542 arm_UHSUB8_VC: "UHSUB8.VC", | 8899 arm_UHSUB8_VC: "UHSUB8.VC", |
7543 arm_UHSUB8_HI: "UHSUB8.HI", | 8900 arm_UHSUB8_HI: "UHSUB8.HI", |
7544 arm_UHSUB8_LS: "UHSUB8.LS", | 8901 arm_UHSUB8_LS: "UHSUB8.LS", |
7545 arm_UHSUB8_GE: "UHSUB8.GE", | 8902 arm_UHSUB8_GE: "UHSUB8.GE", |
7546 arm_UHSUB8_LT: "UHSUB8.LT", | 8903 arm_UHSUB8_LT: "UHSUB8.LT", |
7547 arm_UHSUB8_GT: "UHSUB8.GT", | 8904 arm_UHSUB8_GT: "UHSUB8.GT", |
7548 arm_UHSUB8_LE: "UHSUB8.LE", | 8905 arm_UHSUB8_LE: "UHSUB8.LE", |
7549 arm_UHSUB8: "UHSUB8", | 8906 arm_UHSUB8: "UHSUB8", |
7550 arm_UHSUB8_ZZ: "UHSUB8.ZZ", | 8907 arm_UHSUB8_ZZ: "UHSUB8.ZZ", |
7551 arm_UMAAL_EQ: "UMAAL.EQ", | 8908 arm_UMAAL_EQ: "UMAAL.EQ", |
7552 arm_UMAAL_NE: "UMAAL.NE", | 8909 arm_UMAAL_NE: "UMAAL.NE", |
7553 arm_UMAAL_CS: "UMAAL.CS", | 8910 arm_UMAAL_CS: "UMAAL.CS", |
7554 arm_UMAAL_CC: "UMAAL.CC", | 8911 arm_UMAAL_CC: "UMAAL.CC", |
7555 arm_UMAAL_MI: "UMAAL.MI", | 8912 arm_UMAAL_MI: "UMAAL.MI", |
7556 arm_UMAAL_PL: "UMAAL.PL", | 8913 arm_UMAAL_PL: "UMAAL.PL", |
7557 arm_UMAAL_VS: "UMAAL.VS", | 8914 arm_UMAAL_VS: "UMAAL.VS", |
7558 arm_UMAAL_VC: "UMAAL.VC", | 8915 arm_UMAAL_VC: "UMAAL.VC", |
7559 arm_UMAAL_HI: "UMAAL.HI", | 8916 arm_UMAAL_HI: "UMAAL.HI", |
7560 arm_UMAAL_LS: "UMAAL.LS", | 8917 arm_UMAAL_LS: "UMAAL.LS", |
7561 arm_UMAAL_GE: "UMAAL.GE", | 8918 arm_UMAAL_GE: "UMAAL.GE", |
7562 arm_UMAAL_LT: "UMAAL.LT", | 8919 arm_UMAAL_LT: "UMAAL.LT", |
7563 arm_UMAAL_GT: "UMAAL.GT", | 8920 arm_UMAAL_GT: "UMAAL.GT", |
7564 arm_UMAAL_LE: "UMAAL.LE", | 8921 arm_UMAAL_LE: "UMAAL.LE", |
7565 arm_UMAAL: "UMAAL", | 8922 arm_UMAAL: "UMAAL", |
7566 arm_UMAAL_ZZ: "UMAAL.ZZ", | 8923 arm_UMAAL_ZZ: "UMAAL.ZZ", |
7567 arm_UMLAL_EQ: "UMLAL.EQ", | 8924 arm_UMLAL_EQ: "UMLAL.EQ", |
7568 arm_UMLAL_NE: "UMLAL.NE", | 8925 arm_UMLAL_NE: "UMLAL.NE", |
7569 arm_UMLAL_CS: "UMLAL.CS", | 8926 arm_UMLAL_CS: "UMLAL.CS", |
7570 arm_UMLAL_CC: "UMLAL.CC", | 8927 arm_UMLAL_CC: "UMLAL.CC", |
7571 arm_UMLAL_MI: "UMLAL.MI", | 8928 arm_UMLAL_MI: "UMLAL.MI", |
7572 arm_UMLAL_PL: "UMLAL.PL", | 8929 arm_UMLAL_PL: "UMLAL.PL", |
7573 arm_UMLAL_VS: "UMLAL.VS", | 8930 arm_UMLAL_VS: "UMLAL.VS", |
7574 arm_UMLAL_VC: "UMLAL.VC", | 8931 arm_UMLAL_VC: "UMLAL.VC", |
7575 arm_UMLAL_HI: "UMLAL.HI", | 8932 arm_UMLAL_HI: "UMLAL.HI", |
7576 arm_UMLAL_LS: "UMLAL.LS", | 8933 arm_UMLAL_LS: "UMLAL.LS", |
7577 arm_UMLAL_GE: "UMLAL.GE", | 8934 arm_UMLAL_GE: "UMLAL.GE", |
7578 arm_UMLAL_LT: "UMLAL.LT", | 8935 arm_UMLAL_LT: "UMLAL.LT", |
7579 arm_UMLAL_GT: "UMLAL.GT", | 8936 arm_UMLAL_GT: "UMLAL.GT", |
7580 arm_UMLAL_LE: "UMLAL.LE", | 8937 arm_UMLAL_LE: "UMLAL.LE", |
7581 arm_UMLAL: "UMLAL", | 8938 arm_UMLAL: "UMLAL", |
7582 arm_UMLAL_ZZ: "UMLAL.ZZ", | 8939 arm_UMLAL_ZZ: "UMLAL.ZZ", |
7583 arm_UMLAL_S_EQ: "UMLAL.S.EQ", | 8940 arm_UMLAL_S_EQ: "UMLAL.S.EQ", |
7584 arm_UMLAL_S_NE: "UMLAL.S.NE", | 8941 arm_UMLAL_S_NE: "UMLAL.S.NE", |
7585 arm_UMLAL_S_CS: "UMLAL.S.CS", | 8942 arm_UMLAL_S_CS: "UMLAL.S.CS", |
7586 arm_UMLAL_S_CC: "UMLAL.S.CC", | 8943 arm_UMLAL_S_CC: "UMLAL.S.CC", |
7587 arm_UMLAL_S_MI: "UMLAL.S.MI", | 8944 arm_UMLAL_S_MI: "UMLAL.S.MI", |
7588 arm_UMLAL_S_PL: "UMLAL.S.PL", | 8945 arm_UMLAL_S_PL: "UMLAL.S.PL", |
7589 arm_UMLAL_S_VS: "UMLAL.S.VS", | 8946 arm_UMLAL_S_VS: "UMLAL.S.VS", |
7590 arm_UMLAL_S_VC: "UMLAL.S.VC", | 8947 arm_UMLAL_S_VC: "UMLAL.S.VC", |
7591 arm_UMLAL_S_HI: "UMLAL.S.HI", | 8948 arm_UMLAL_S_HI: "UMLAL.S.HI", |
7592 arm_UMLAL_S_LS: "UMLAL.S.LS", | 8949 arm_UMLAL_S_LS: "UMLAL.S.LS", |
7593 arm_UMLAL_S_GE: "UMLAL.S.GE", | 8950 arm_UMLAL_S_GE: "UMLAL.S.GE", |
7594 arm_UMLAL_S_LT: "UMLAL.S.LT", | 8951 arm_UMLAL_S_LT: "UMLAL.S.LT", |
7595 arm_UMLAL_S_GT: "UMLAL.S.GT", | 8952 arm_UMLAL_S_GT: "UMLAL.S.GT", |
7596 arm_UMLAL_S_LE: "UMLAL.S.LE", | 8953 arm_UMLAL_S_LE: "UMLAL.S.LE", |
7597 arm_UMLAL_S: "UMLAL.S", | 8954 arm_UMLAL_S: "UMLAL.S", |
7598 arm_UMLAL_S_ZZ: "UMLAL.S.ZZ", | 8955 arm_UMLAL_S_ZZ: "UMLAL.S.ZZ", |
7599 arm_UMULL_EQ: "UMULL.EQ", | 8956 arm_UMULL_EQ: "UMULL.EQ", |
7600 arm_UMULL_NE: "UMULL.NE", | 8957 arm_UMULL_NE: "UMULL.NE", |
7601 arm_UMULL_CS: "UMULL.CS", | 8958 arm_UMULL_CS: "UMULL.CS", |
7602 arm_UMULL_CC: "UMULL.CC", | 8959 arm_UMULL_CC: "UMULL.CC", |
7603 arm_UMULL_MI: "UMULL.MI", | 8960 arm_UMULL_MI: "UMULL.MI", |
7604 arm_UMULL_PL: "UMULL.PL", | 8961 arm_UMULL_PL: "UMULL.PL", |
7605 arm_UMULL_VS: "UMULL.VS", | 8962 arm_UMULL_VS: "UMULL.VS", |
7606 arm_UMULL_VC: "UMULL.VC", | 8963 arm_UMULL_VC: "UMULL.VC", |
7607 arm_UMULL_HI: "UMULL.HI", | 8964 arm_UMULL_HI: "UMULL.HI", |
7608 arm_UMULL_LS: "UMULL.LS", | 8965 arm_UMULL_LS: "UMULL.LS", |
7609 arm_UMULL_GE: "UMULL.GE", | 8966 arm_UMULL_GE: "UMULL.GE", |
7610 arm_UMULL_LT: "UMULL.LT", | 8967 arm_UMULL_LT: "UMULL.LT", |
7611 arm_UMULL_GT: "UMULL.GT", | 8968 arm_UMULL_GT: "UMULL.GT", |
7612 arm_UMULL_LE: "UMULL.LE", | 8969 arm_UMULL_LE: "UMULL.LE", |
7613 arm_UMULL: "UMULL", | 8970 arm_UMULL: "UMULL", |
7614 arm_UMULL_ZZ: "UMULL.ZZ", | 8971 arm_UMULL_ZZ: "UMULL.ZZ", |
7615 arm_UMULL_S_EQ: "UMULL.S.EQ", | 8972 arm_UMULL_S_EQ: "UMULL.S.EQ", |
7616 arm_UMULL_S_NE: "UMULL.S.NE", | 8973 arm_UMULL_S_NE: "UMULL.S.NE", |
7617 arm_UMULL_S_CS: "UMULL.S.CS", | 8974 arm_UMULL_S_CS: "UMULL.S.CS", |
7618 arm_UMULL_S_CC: "UMULL.S.CC", | 8975 arm_UMULL_S_CC: "UMULL.S.CC", |
7619 arm_UMULL_S_MI: "UMULL.S.MI", | 8976 arm_UMULL_S_MI: "UMULL.S.MI", |
7620 arm_UMULL_S_PL: "UMULL.S.PL", | 8977 arm_UMULL_S_PL: "UMULL.S.PL", |
7621 arm_UMULL_S_VS: "UMULL.S.VS", | 8978 arm_UMULL_S_VS: "UMULL.S.VS", |
7622 arm_UMULL_S_VC: "UMULL.S.VC", | 8979 arm_UMULL_S_VC: "UMULL.S.VC", |
7623 arm_UMULL_S_HI: "UMULL.S.HI", | 8980 arm_UMULL_S_HI: "UMULL.S.HI", |
7624 arm_UMULL_S_LS: "UMULL.S.LS", | 8981 arm_UMULL_S_LS: "UMULL.S.LS", |
7625 arm_UMULL_S_GE: "UMULL.S.GE", | 8982 arm_UMULL_S_GE: "UMULL.S.GE", |
7626 arm_UMULL_S_LT: "UMULL.S.LT", | 8983 arm_UMULL_S_LT: "UMULL.S.LT", |
7627 arm_UMULL_S_GT: "UMULL.S.GT", | 8984 arm_UMULL_S_GT: "UMULL.S.GT", |
7628 arm_UMULL_S_LE: "UMULL.S.LE", | 8985 arm_UMULL_S_LE: "UMULL.S.LE", |
7629 arm_UMULL_S: "UMULL.S", | 8986 arm_UMULL_S: "UMULL.S", |
7630 arm_UMULL_S_ZZ: "UMULL.S.ZZ", | 8987 arm_UMULL_S_ZZ: "UMULL.S.ZZ", |
7631 arm_UQADD16_EQ: "UQADD16.EQ", | 8988 arm_UNDEF: "UNDEF", |
7632 arm_UQADD16_NE: "UQADD16.NE", | 8989 arm_UQADD16_EQ: "UQADD16.EQ", |
7633 arm_UQADD16_CS: "UQADD16.CS", | 8990 arm_UQADD16_NE: "UQADD16.NE", |
7634 arm_UQADD16_CC: "UQADD16.CC", | 8991 arm_UQADD16_CS: "UQADD16.CS", |
7635 arm_UQADD16_MI: "UQADD16.MI", | 8992 arm_UQADD16_CC: "UQADD16.CC", |
7636 arm_UQADD16_PL: "UQADD16.PL", | 8993 arm_UQADD16_MI: "UQADD16.MI", |
7637 arm_UQADD16_VS: "UQADD16.VS", | 8994 arm_UQADD16_PL: "UQADD16.PL", |
7638 arm_UQADD16_VC: "UQADD16.VC", | 8995 arm_UQADD16_VS: "UQADD16.VS", |
7639 arm_UQADD16_HI: "UQADD16.HI", | 8996 arm_UQADD16_VC: "UQADD16.VC", |
7640 arm_UQADD16_LS: "UQADD16.LS", | 8997 arm_UQADD16_HI: "UQADD16.HI", |
7641 arm_UQADD16_GE: "UQADD16.GE", | 8998 arm_UQADD16_LS: "UQADD16.LS", |
7642 arm_UQADD16_LT: "UQADD16.LT", | 8999 arm_UQADD16_GE: "UQADD16.GE", |
7643 arm_UQADD16_GT: "UQADD16.GT", | 9000 arm_UQADD16_LT: "UQADD16.LT", |
7644 arm_UQADD16_LE: "UQADD16.LE", | 9001 arm_UQADD16_GT: "UQADD16.GT", |
7645 arm_UQADD16: "UQADD16", | 9002 arm_UQADD16_LE: "UQADD16.LE", |
7646 arm_UQADD16_ZZ: "UQADD16.ZZ", | 9003 arm_UQADD16: "UQADD16", |
7647 arm_UQADD8_EQ: "UQADD8.EQ", | 9004 arm_UQADD16_ZZ: "UQADD16.ZZ", |
7648 arm_UQADD8_NE: "UQADD8.NE", | 9005 arm_UQADD8_EQ: "UQADD8.EQ", |
7649 arm_UQADD8_CS: "UQADD8.CS", | 9006 arm_UQADD8_NE: "UQADD8.NE", |
7650 arm_UQADD8_CC: "UQADD8.CC", | 9007 arm_UQADD8_CS: "UQADD8.CS", |
7651 arm_UQADD8_MI: "UQADD8.MI", | 9008 arm_UQADD8_CC: "UQADD8.CC", |
7652 arm_UQADD8_PL: "UQADD8.PL", | 9009 arm_UQADD8_MI: "UQADD8.MI", |
7653 arm_UQADD8_VS: "UQADD8.VS", | 9010 arm_UQADD8_PL: "UQADD8.PL", |
7654 arm_UQADD8_VC: "UQADD8.VC", | 9011 arm_UQADD8_VS: "UQADD8.VS", |
7655 arm_UQADD8_HI: "UQADD8.HI", | 9012 arm_UQADD8_VC: "UQADD8.VC", |
7656 arm_UQADD8_LS: "UQADD8.LS", | 9013 arm_UQADD8_HI: "UQADD8.HI", |
7657 arm_UQADD8_GE: "UQADD8.GE", | 9014 arm_UQADD8_LS: "UQADD8.LS", |
7658 arm_UQADD8_LT: "UQADD8.LT", | 9015 arm_UQADD8_GE: "UQADD8.GE", |
7659 arm_UQADD8_GT: "UQADD8.GT", | 9016 arm_UQADD8_LT: "UQADD8.LT", |
7660 arm_UQADD8_LE: "UQADD8.LE", | 9017 arm_UQADD8_GT: "UQADD8.GT", |
7661 arm_UQADD8: "UQADD8", | 9018 arm_UQADD8_LE: "UQADD8.LE", |
7662 arm_UQADD8_ZZ: "UQADD8.ZZ", | 9019 arm_UQADD8: "UQADD8", |
7663 arm_UQASX_EQ: "UQASX.EQ", | 9020 arm_UQADD8_ZZ: "UQADD8.ZZ", |
7664 arm_UQASX_NE: "UQASX.NE", | 9021 arm_UQASX_EQ: "UQASX.EQ", |
7665 arm_UQASX_CS: "UQASX.CS", | 9022 arm_UQASX_NE: "UQASX.NE", |
7666 arm_UQASX_CC: "UQASX.CC", | 9023 arm_UQASX_CS: "UQASX.CS", |
7667 arm_UQASX_MI: "UQASX.MI", | 9024 arm_UQASX_CC: "UQASX.CC", |
7668 arm_UQASX_PL: "UQASX.PL", | 9025 arm_UQASX_MI: "UQASX.MI", |
7669 arm_UQASX_VS: "UQASX.VS", | 9026 arm_UQASX_PL: "UQASX.PL", |
7670 arm_UQASX_VC: "UQASX.VC", | 9027 arm_UQASX_VS: "UQASX.VS", |
7671 arm_UQASX_HI: "UQASX.HI", | 9028 arm_UQASX_VC: "UQASX.VC", |
7672 arm_UQASX_LS: "UQASX.LS", | 9029 arm_UQASX_HI: "UQASX.HI", |
7673 arm_UQASX_GE: "UQASX.GE", | 9030 arm_UQASX_LS: "UQASX.LS", |
7674 arm_UQASX_LT: "UQASX.LT", | 9031 arm_UQASX_GE: "UQASX.GE", |
7675 arm_UQASX_GT: "UQASX.GT", | 9032 arm_UQASX_LT: "UQASX.LT", |
7676 arm_UQASX_LE: "UQASX.LE", | 9033 arm_UQASX_GT: "UQASX.GT", |
7677 arm_UQASX: "UQASX", | 9034 arm_UQASX_LE: "UQASX.LE", |
7678 arm_UQASX_ZZ: "UQASX.ZZ", | 9035 arm_UQASX: "UQASX", |
7679 arm_UQSAX_EQ: "UQSAX.EQ", | 9036 arm_UQASX_ZZ: "UQASX.ZZ", |
7680 arm_UQSAX_NE: "UQSAX.NE", | 9037 arm_UQSAX_EQ: "UQSAX.EQ", |
7681 arm_UQSAX_CS: "UQSAX.CS", | 9038 arm_UQSAX_NE: "UQSAX.NE", |
7682 arm_UQSAX_CC: "UQSAX.CC", | 9039 arm_UQSAX_CS: "UQSAX.CS", |
7683 arm_UQSAX_MI: "UQSAX.MI", | 9040 arm_UQSAX_CC: "UQSAX.CC", |
7684 arm_UQSAX_PL: "UQSAX.PL", | 9041 arm_UQSAX_MI: "UQSAX.MI", |
7685 arm_UQSAX_VS: "UQSAX.VS", | 9042 arm_UQSAX_PL: "UQSAX.PL", |
7686 arm_UQSAX_VC: "UQSAX.VC", | 9043 arm_UQSAX_VS: "UQSAX.VS", |
7687 arm_UQSAX_HI: "UQSAX.HI", | 9044 arm_UQSAX_VC: "UQSAX.VC", |
7688 arm_UQSAX_LS: "UQSAX.LS", | 9045 arm_UQSAX_HI: "UQSAX.HI", |
7689 arm_UQSAX_GE: "UQSAX.GE", | 9046 arm_UQSAX_LS: "UQSAX.LS", |
7690 arm_UQSAX_LT: "UQSAX.LT", | 9047 arm_UQSAX_GE: "UQSAX.GE", |
7691 arm_UQSAX_GT: "UQSAX.GT", | 9048 arm_UQSAX_LT: "UQSAX.LT", |
7692 arm_UQSAX_LE: "UQSAX.LE", | 9049 arm_UQSAX_GT: "UQSAX.GT", |
7693 arm_UQSAX: "UQSAX", | 9050 arm_UQSAX_LE: "UQSAX.LE", |
7694 arm_UQSAX_ZZ: "UQSAX.ZZ", | 9051 arm_UQSAX: "UQSAX", |
7695 arm_UQSUB16_EQ: "UQSUB16.EQ", | 9052 arm_UQSAX_ZZ: "UQSAX.ZZ", |
7696 arm_UQSUB16_NE: "UQSUB16.NE", | 9053 arm_UQSUB16_EQ: "UQSUB16.EQ", |
7697 arm_UQSUB16_CS: "UQSUB16.CS", | 9054 arm_UQSUB16_NE: "UQSUB16.NE", |
7698 arm_UQSUB16_CC: "UQSUB16.CC", | 9055 arm_UQSUB16_CS: "UQSUB16.CS", |
7699 arm_UQSUB16_MI: "UQSUB16.MI", | 9056 arm_UQSUB16_CC: "UQSUB16.CC", |
7700 arm_UQSUB16_PL: "UQSUB16.PL", | 9057 arm_UQSUB16_MI: "UQSUB16.MI", |
7701 arm_UQSUB16_VS: "UQSUB16.VS", | 9058 arm_UQSUB16_PL: "UQSUB16.PL", |
7702 arm_UQSUB16_VC: "UQSUB16.VC", | 9059 arm_UQSUB16_VS: "UQSUB16.VS", |
7703 arm_UQSUB16_HI: "UQSUB16.HI", | 9060 arm_UQSUB16_VC: "UQSUB16.VC", |
7704 arm_UQSUB16_LS: "UQSUB16.LS", | 9061 arm_UQSUB16_HI: "UQSUB16.HI", |
7705 arm_UQSUB16_GE: "UQSUB16.GE", | 9062 arm_UQSUB16_LS: "UQSUB16.LS", |
7706 arm_UQSUB16_LT: "UQSUB16.LT", | 9063 arm_UQSUB16_GE: "UQSUB16.GE", |
7707 arm_UQSUB16_GT: "UQSUB16.GT", | 9064 arm_UQSUB16_LT: "UQSUB16.LT", |
7708 arm_UQSUB16_LE: "UQSUB16.LE", | 9065 arm_UQSUB16_GT: "UQSUB16.GT", |
7709 arm_UQSUB16: "UQSUB16", | 9066 arm_UQSUB16_LE: "UQSUB16.LE", |
7710 arm_UQSUB16_ZZ: "UQSUB16.ZZ", | 9067 arm_UQSUB16: "UQSUB16", |
7711 arm_UQSUB8_EQ: "UQSUB8.EQ", | 9068 arm_UQSUB16_ZZ: "UQSUB16.ZZ", |
7712 arm_UQSUB8_NE: "UQSUB8.NE", | 9069 arm_UQSUB8_EQ: "UQSUB8.EQ", |
7713 arm_UQSUB8_CS: "UQSUB8.CS", | 9070 arm_UQSUB8_NE: "UQSUB8.NE", |
7714 arm_UQSUB8_CC: "UQSUB8.CC", | 9071 arm_UQSUB8_CS: "UQSUB8.CS", |
7715 arm_UQSUB8_MI: "UQSUB8.MI", | 9072 arm_UQSUB8_CC: "UQSUB8.CC", |
7716 arm_UQSUB8_PL: "UQSUB8.PL", | 9073 arm_UQSUB8_MI: "UQSUB8.MI", |
7717 arm_UQSUB8_VS: "UQSUB8.VS", | 9074 arm_UQSUB8_PL: "UQSUB8.PL", |
7718 arm_UQSUB8_VC: "UQSUB8.VC", | 9075 arm_UQSUB8_VS: "UQSUB8.VS", |
7719 arm_UQSUB8_HI: "UQSUB8.HI", | 9076 arm_UQSUB8_VC: "UQSUB8.VC", |
7720 arm_UQSUB8_LS: "UQSUB8.LS", | 9077 arm_UQSUB8_HI: "UQSUB8.HI", |
7721 arm_UQSUB8_GE: "UQSUB8.GE", | 9078 arm_UQSUB8_LS: "UQSUB8.LS", |
7722 arm_UQSUB8_LT: "UQSUB8.LT", | 9079 arm_UQSUB8_GE: "UQSUB8.GE", |
7723 arm_UQSUB8_GT: "UQSUB8.GT", | 9080 arm_UQSUB8_LT: "UQSUB8.LT", |
7724 arm_UQSUB8_LE: "UQSUB8.LE", | 9081 arm_UQSUB8_GT: "UQSUB8.GT", |
7725 arm_UQSUB8: "UQSUB8", | 9082 arm_UQSUB8_LE: "UQSUB8.LE", |
7726 arm_UQSUB8_ZZ: "UQSUB8.ZZ", | 9083 arm_UQSUB8: "UQSUB8", |
7727 arm_USAD8_EQ: "USAD8.EQ", | 9084 arm_UQSUB8_ZZ: "UQSUB8.ZZ", |
7728 arm_USAD8_NE: "USAD8.NE", | 9085 arm_USAD8_EQ: "USAD8.EQ", |
7729 arm_USAD8_CS: "USAD8.CS", | 9086 arm_USAD8_NE: "USAD8.NE", |
7730 arm_USAD8_CC: "USAD8.CC", | 9087 arm_USAD8_CS: "USAD8.CS", |
7731 arm_USAD8_MI: "USAD8.MI", | 9088 arm_USAD8_CC: "USAD8.CC", |
7732 arm_USAD8_PL: "USAD8.PL", | 9089 arm_USAD8_MI: "USAD8.MI", |
7733 arm_USAD8_VS: "USAD8.VS", | 9090 arm_USAD8_PL: "USAD8.PL", |
7734 arm_USAD8_VC: "USAD8.VC", | 9091 arm_USAD8_VS: "USAD8.VS", |
7735 arm_USAD8_HI: "USAD8.HI", | 9092 arm_USAD8_VC: "USAD8.VC", |
7736 arm_USAD8_LS: "USAD8.LS", | 9093 arm_USAD8_HI: "USAD8.HI", |
7737 arm_USAD8_GE: "USAD8.GE", | 9094 arm_USAD8_LS: "USAD8.LS", |
7738 arm_USAD8_LT: "USAD8.LT", | 9095 arm_USAD8_GE: "USAD8.GE", |
7739 arm_USAD8_GT: "USAD8.GT", | 9096 arm_USAD8_LT: "USAD8.LT", |
7740 arm_USAD8_LE: "USAD8.LE", | 9097 arm_USAD8_GT: "USAD8.GT", |
7741 arm_USAD8: "USAD8", | 9098 arm_USAD8_LE: "USAD8.LE", |
7742 arm_USAD8_ZZ: "USAD8.ZZ", | 9099 arm_USAD8: "USAD8", |
7743 arm_USADA8_EQ: "USADA8.EQ", | 9100 arm_USAD8_ZZ: "USAD8.ZZ", |
7744 arm_USADA8_NE: "USADA8.NE", | 9101 arm_USADA8_EQ: "USADA8.EQ", |
7745 arm_USADA8_CS: "USADA8.CS", | 9102 arm_USADA8_NE: "USADA8.NE", |
7746 arm_USADA8_CC: "USADA8.CC", | 9103 arm_USADA8_CS: "USADA8.CS", |
7747 arm_USADA8_MI: "USADA8.MI", | 9104 arm_USADA8_CC: "USADA8.CC", |
7748 arm_USADA8_PL: "USADA8.PL", | 9105 arm_USADA8_MI: "USADA8.MI", |
7749 arm_USADA8_VS: "USADA8.VS", | 9106 arm_USADA8_PL: "USADA8.PL", |
7750 arm_USADA8_VC: "USADA8.VC", | 9107 arm_USADA8_VS: "USADA8.VS", |
7751 arm_USADA8_HI: "USADA8.HI", | 9108 arm_USADA8_VC: "USADA8.VC", |
7752 arm_USADA8_LS: "USADA8.LS", | 9109 arm_USADA8_HI: "USADA8.HI", |
7753 arm_USADA8_GE: "USADA8.GE", | 9110 arm_USADA8_LS: "USADA8.LS", |
7754 arm_USADA8_LT: "USADA8.LT", | 9111 arm_USADA8_GE: "USADA8.GE", |
7755 arm_USADA8_GT: "USADA8.GT", | 9112 arm_USADA8_LT: "USADA8.LT", |
7756 arm_USADA8_LE: "USADA8.LE", | 9113 arm_USADA8_GT: "USADA8.GT", |
7757 arm_USADA8: "USADA8", | 9114 arm_USADA8_LE: "USADA8.LE", |
7758 arm_USADA8_ZZ: "USADA8.ZZ", | 9115 arm_USADA8: "USADA8", |
7759 arm_USAT_EQ: "USAT.EQ", | 9116 arm_USADA8_ZZ: "USADA8.ZZ", |
7760 arm_USAT_NE: "USAT.NE", | 9117 arm_USAT_EQ: "USAT.EQ", |
7761 arm_USAT_CS: "USAT.CS", | 9118 arm_USAT_NE: "USAT.NE", |
7762 arm_USAT_CC: "USAT.CC", | 9119 arm_USAT_CS: "USAT.CS", |
7763 arm_USAT_MI: "USAT.MI", | 9120 arm_USAT_CC: "USAT.CC", |
7764 arm_USAT_PL: "USAT.PL", | 9121 arm_USAT_MI: "USAT.MI", |
7765 arm_USAT_VS: "USAT.VS", | 9122 arm_USAT_PL: "USAT.PL", |
7766 arm_USAT_VC: "USAT.VC", | 9123 arm_USAT_VS: "USAT.VS", |
7767 arm_USAT_HI: "USAT.HI", | 9124 arm_USAT_VC: "USAT.VC", |
7768 arm_USAT_LS: "USAT.LS", | 9125 arm_USAT_HI: "USAT.HI", |
7769 arm_USAT_GE: "USAT.GE", | 9126 arm_USAT_LS: "USAT.LS", |
7770 arm_USAT_LT: "USAT.LT", | 9127 arm_USAT_GE: "USAT.GE", |
7771 arm_USAT_GT: "USAT.GT", | 9128 arm_USAT_LT: "USAT.LT", |
7772 arm_USAT_LE: "USAT.LE", | 9129 arm_USAT_GT: "USAT.GT", |
7773 arm_USAT: "USAT", | 9130 arm_USAT_LE: "USAT.LE", |
7774 arm_USAT_ZZ: "USAT.ZZ", | 9131 arm_USAT: "USAT", |
7775 arm_USAT16_EQ: "USAT16.EQ", | 9132 arm_USAT_ZZ: "USAT.ZZ", |
7776 arm_USAT16_NE: "USAT16.NE", | 9133 arm_USAT16_EQ: "USAT16.EQ", |
7777 arm_USAT16_CS: "USAT16.CS", | 9134 arm_USAT16_NE: "USAT16.NE", |
7778 arm_USAT16_CC: "USAT16.CC", | 9135 arm_USAT16_CS: "USAT16.CS", |
7779 arm_USAT16_MI: "USAT16.MI", | 9136 arm_USAT16_CC: "USAT16.CC", |
7780 arm_USAT16_PL: "USAT16.PL", | 9137 arm_USAT16_MI: "USAT16.MI", |
7781 arm_USAT16_VS: "USAT16.VS", | 9138 arm_USAT16_PL: "USAT16.PL", |
7782 arm_USAT16_VC: "USAT16.VC", | 9139 arm_USAT16_VS: "USAT16.VS", |
7783 arm_USAT16_HI: "USAT16.HI", | 9140 arm_USAT16_VC: "USAT16.VC", |
7784 arm_USAT16_LS: "USAT16.LS", | 9141 arm_USAT16_HI: "USAT16.HI", |
7785 arm_USAT16_GE: "USAT16.GE", | 9142 arm_USAT16_LS: "USAT16.LS", |
7786 arm_USAT16_LT: "USAT16.LT", | 9143 arm_USAT16_GE: "USAT16.GE", |
7787 arm_USAT16_GT: "USAT16.GT", | 9144 arm_USAT16_LT: "USAT16.LT", |
7788 arm_USAT16_LE: "USAT16.LE", | 9145 arm_USAT16_GT: "USAT16.GT", |
7789 arm_USAT16: "USAT16", | 9146 arm_USAT16_LE: "USAT16.LE", |
7790 arm_USAT16_ZZ: "USAT16.ZZ", | 9147 arm_USAT16: "USAT16", |
7791 arm_USAX_EQ: "USAX.EQ", | 9148 arm_USAT16_ZZ: "USAT16.ZZ", |
7792 arm_USAX_NE: "USAX.NE", | 9149 arm_USAX_EQ: "USAX.EQ", |
7793 arm_USAX_CS: "USAX.CS", | 9150 arm_USAX_NE: "USAX.NE", |
7794 arm_USAX_CC: "USAX.CC", | 9151 arm_USAX_CS: "USAX.CS", |
7795 arm_USAX_MI: "USAX.MI", | 9152 arm_USAX_CC: "USAX.CC", |
7796 arm_USAX_PL: "USAX.PL", | 9153 arm_USAX_MI: "USAX.MI", |
7797 arm_USAX_VS: "USAX.VS", | 9154 arm_USAX_PL: "USAX.PL", |
7798 arm_USAX_VC: "USAX.VC", | 9155 arm_USAX_VS: "USAX.VS", |
7799 arm_USAX_HI: "USAX.HI", | 9156 arm_USAX_VC: "USAX.VC", |
7800 arm_USAX_LS: "USAX.LS", | 9157 arm_USAX_HI: "USAX.HI", |
7801 arm_USAX_GE: "USAX.GE", | 9158 arm_USAX_LS: "USAX.LS", |
7802 arm_USAX_LT: "USAX.LT", | 9159 arm_USAX_GE: "USAX.GE", |
7803 arm_USAX_GT: "USAX.GT", | 9160 arm_USAX_LT: "USAX.LT", |
7804 arm_USAX_LE: "USAX.LE", | 9161 arm_USAX_GT: "USAX.GT", |
7805 arm_USAX: "USAX", | 9162 arm_USAX_LE: "USAX.LE", |
7806 arm_USAX_ZZ: "USAX.ZZ", | 9163 arm_USAX: "USAX", |
7807 arm_USUB16_EQ: "USUB16.EQ", | 9164 arm_USAX_ZZ: "USAX.ZZ", |
7808 arm_USUB16_NE: "USUB16.NE", | 9165 arm_USUB16_EQ: "USUB16.EQ", |
7809 arm_USUB16_CS: "USUB16.CS", | 9166 arm_USUB16_NE: "USUB16.NE", |
7810 arm_USUB16_CC: "USUB16.CC", | 9167 arm_USUB16_CS: "USUB16.CS", |
7811 arm_USUB16_MI: "USUB16.MI", | 9168 arm_USUB16_CC: "USUB16.CC", |
7812 arm_USUB16_PL: "USUB16.PL", | 9169 arm_USUB16_MI: "USUB16.MI", |
7813 arm_USUB16_VS: "USUB16.VS", | 9170 arm_USUB16_PL: "USUB16.PL", |
7814 arm_USUB16_VC: "USUB16.VC", | 9171 arm_USUB16_VS: "USUB16.VS", |
7815 arm_USUB16_HI: "USUB16.HI", | 9172 arm_USUB16_VC: "USUB16.VC", |
7816 arm_USUB16_LS: "USUB16.LS", | 9173 arm_USUB16_HI: "USUB16.HI", |
7817 arm_USUB16_GE: "USUB16.GE", | 9174 arm_USUB16_LS: "USUB16.LS", |
7818 arm_USUB16_LT: "USUB16.LT", | 9175 arm_USUB16_GE: "USUB16.GE", |
7819 arm_USUB16_GT: "USUB16.GT", | 9176 arm_USUB16_LT: "USUB16.LT", |
7820 arm_USUB16_LE: "USUB16.LE", | 9177 arm_USUB16_GT: "USUB16.GT", |
7821 arm_USUB16: "USUB16", | 9178 arm_USUB16_LE: "USUB16.LE", |
7822 arm_USUB16_ZZ: "USUB16.ZZ", | 9179 arm_USUB16: "USUB16", |
7823 arm_USUB8_EQ: "USUB8.EQ", | 9180 arm_USUB16_ZZ: "USUB16.ZZ", |
7824 arm_USUB8_NE: "USUB8.NE", | 9181 arm_USUB8_EQ: "USUB8.EQ", |
7825 arm_USUB8_CS: "USUB8.CS", | 9182 arm_USUB8_NE: "USUB8.NE", |
7826 arm_USUB8_CC: "USUB8.CC", | 9183 arm_USUB8_CS: "USUB8.CS", |
7827 arm_USUB8_MI: "USUB8.MI", | 9184 arm_USUB8_CC: "USUB8.CC", |
7828 arm_USUB8_PL: "USUB8.PL", | 9185 arm_USUB8_MI: "USUB8.MI", |
7829 arm_USUB8_VS: "USUB8.VS", | 9186 arm_USUB8_PL: "USUB8.PL", |
7830 arm_USUB8_VC: "USUB8.VC", | 9187 arm_USUB8_VS: "USUB8.VS", |
7831 arm_USUB8_HI: "USUB8.HI", | 9188 arm_USUB8_VC: "USUB8.VC", |
7832 arm_USUB8_LS: "USUB8.LS", | 9189 arm_USUB8_HI: "USUB8.HI", |
7833 arm_USUB8_GE: "USUB8.GE", | 9190 arm_USUB8_LS: "USUB8.LS", |
7834 arm_USUB8_LT: "USUB8.LT", | 9191 arm_USUB8_GE: "USUB8.GE", |
7835 arm_USUB8_GT: "USUB8.GT", | 9192 arm_USUB8_LT: "USUB8.LT", |
7836 arm_USUB8_LE: "USUB8.LE", | 9193 arm_USUB8_GT: "USUB8.GT", |
7837 arm_USUB8: "USUB8", | 9194 arm_USUB8_LE: "USUB8.LE", |
7838 arm_USUB8_ZZ: "USUB8.ZZ", | 9195 arm_USUB8: "USUB8", |
7839 arm_UXTAB_EQ: "UXTAB.EQ", | 9196 arm_USUB8_ZZ: "USUB8.ZZ", |
7840 arm_UXTAB_NE: "UXTAB.NE", | 9197 arm_UXTAB_EQ: "UXTAB.EQ", |
7841 arm_UXTAB_CS: "UXTAB.CS", | 9198 arm_UXTAB_NE: "UXTAB.NE", |
7842 arm_UXTAB_CC: "UXTAB.CC", | 9199 arm_UXTAB_CS: "UXTAB.CS", |
7843 arm_UXTAB_MI: "UXTAB.MI", | 9200 arm_UXTAB_CC: "UXTAB.CC", |
7844 arm_UXTAB_PL: "UXTAB.PL", | 9201 arm_UXTAB_MI: "UXTAB.MI", |
7845 arm_UXTAB_VS: "UXTAB.VS", | 9202 arm_UXTAB_PL: "UXTAB.PL", |
7846 arm_UXTAB_VC: "UXTAB.VC", | 9203 arm_UXTAB_VS: "UXTAB.VS", |
7847 arm_UXTAB_HI: "UXTAB.HI", | 9204 arm_UXTAB_VC: "UXTAB.VC", |
7848 arm_UXTAB_LS: "UXTAB.LS", | 9205 arm_UXTAB_HI: "UXTAB.HI", |
7849 arm_UXTAB_GE: "UXTAB.GE", | 9206 arm_UXTAB_LS: "UXTAB.LS", |
7850 arm_UXTAB_LT: "UXTAB.LT", | 9207 arm_UXTAB_GE: "UXTAB.GE", |
7851 arm_UXTAB_GT: "UXTAB.GT", | 9208 arm_UXTAB_LT: "UXTAB.LT", |
7852 arm_UXTAB_LE: "UXTAB.LE", | 9209 arm_UXTAB_GT: "UXTAB.GT", |
7853 arm_UXTAB: "UXTAB", | 9210 arm_UXTAB_LE: "UXTAB.LE", |
7854 arm_UXTAB_ZZ: "UXTAB.ZZ", | 9211 arm_UXTAB: "UXTAB", |
7855 arm_UXTAB16_EQ: "UXTAB16.EQ", | 9212 arm_UXTAB_ZZ: "UXTAB.ZZ", |
7856 arm_UXTAB16_NE: "UXTAB16.NE", | 9213 arm_UXTAB16_EQ: "UXTAB16.EQ", |
7857 arm_UXTAB16_CS: "UXTAB16.CS", | 9214 arm_UXTAB16_NE: "UXTAB16.NE", |
7858 arm_UXTAB16_CC: "UXTAB16.CC", | 9215 arm_UXTAB16_CS: "UXTAB16.CS", |
7859 arm_UXTAB16_MI: "UXTAB16.MI", | 9216 arm_UXTAB16_CC: "UXTAB16.CC", |
7860 arm_UXTAB16_PL: "UXTAB16.PL", | 9217 arm_UXTAB16_MI: "UXTAB16.MI", |
7861 arm_UXTAB16_VS: "UXTAB16.VS", | 9218 arm_UXTAB16_PL: "UXTAB16.PL", |
7862 arm_UXTAB16_VC: "UXTAB16.VC", | 9219 arm_UXTAB16_VS: "UXTAB16.VS", |
7863 arm_UXTAB16_HI: "UXTAB16.HI", | 9220 arm_UXTAB16_VC: "UXTAB16.VC", |
7864 arm_UXTAB16_LS: "UXTAB16.LS", | 9221 arm_UXTAB16_HI: "UXTAB16.HI", |
7865 arm_UXTAB16_GE: "UXTAB16.GE", | 9222 arm_UXTAB16_LS: "UXTAB16.LS", |
7866 arm_UXTAB16_LT: "UXTAB16.LT", | 9223 arm_UXTAB16_GE: "UXTAB16.GE", |
7867 arm_UXTAB16_GT: "UXTAB16.GT", | 9224 arm_UXTAB16_LT: "UXTAB16.LT", |
7868 arm_UXTAB16_LE: "UXTAB16.LE", | 9225 arm_UXTAB16_GT: "UXTAB16.GT", |
7869 arm_UXTAB16: "UXTAB16", | 9226 arm_UXTAB16_LE: "UXTAB16.LE", |
7870 arm_UXTAB16_ZZ: "UXTAB16.ZZ", | 9227 arm_UXTAB16: "UXTAB16", |
7871 arm_UXTAH_EQ: "UXTAH.EQ", | 9228 arm_UXTAB16_ZZ: "UXTAB16.ZZ", |
7872 arm_UXTAH_NE: "UXTAH.NE", | 9229 arm_UXTAH_EQ: "UXTAH.EQ", |
7873 arm_UXTAH_CS: "UXTAH.CS", | 9230 arm_UXTAH_NE: "UXTAH.NE", |
7874 arm_UXTAH_CC: "UXTAH.CC", | 9231 arm_UXTAH_CS: "UXTAH.CS", |
7875 arm_UXTAH_MI: "UXTAH.MI", | 9232 arm_UXTAH_CC: "UXTAH.CC", |
7876 arm_UXTAH_PL: "UXTAH.PL", | 9233 arm_UXTAH_MI: "UXTAH.MI", |
7877 arm_UXTAH_VS: "UXTAH.VS", | 9234 arm_UXTAH_PL: "UXTAH.PL", |
7878 arm_UXTAH_VC: "UXTAH.VC", | 9235 arm_UXTAH_VS: "UXTAH.VS", |
7879 arm_UXTAH_HI: "UXTAH.HI", | 9236 arm_UXTAH_VC: "UXTAH.VC", |
7880 arm_UXTAH_LS: "UXTAH.LS", | 9237 arm_UXTAH_HI: "UXTAH.HI", |
7881 arm_UXTAH_GE: "UXTAH.GE", | 9238 arm_UXTAH_LS: "UXTAH.LS", |
7882 arm_UXTAH_LT: "UXTAH.LT", | 9239 arm_UXTAH_GE: "UXTAH.GE", |
7883 arm_UXTAH_GT: "UXTAH.GT", | 9240 arm_UXTAH_LT: "UXTAH.LT", |
7884 arm_UXTAH_LE: "UXTAH.LE", | 9241 arm_UXTAH_GT: "UXTAH.GT", |
7885 arm_UXTAH: "UXTAH", | 9242 arm_UXTAH_LE: "UXTAH.LE", |
7886 arm_UXTAH_ZZ: "UXTAH.ZZ", | 9243 arm_UXTAH: "UXTAH", |
7887 arm_UXTB_EQ: "UXTB.EQ", | 9244 arm_UXTAH_ZZ: "UXTAH.ZZ", |
7888 arm_UXTB_NE: "UXTB.NE", | 9245 arm_UXTB_EQ: "UXTB.EQ", |
7889 arm_UXTB_CS: "UXTB.CS", | 9246 arm_UXTB_NE: "UXTB.NE", |
7890 arm_UXTB_CC: "UXTB.CC", | 9247 arm_UXTB_CS: "UXTB.CS", |
7891 arm_UXTB_MI: "UXTB.MI", | 9248 arm_UXTB_CC: "UXTB.CC", |
7892 arm_UXTB_PL: "UXTB.PL", | 9249 arm_UXTB_MI: "UXTB.MI", |
7893 arm_UXTB_VS: "UXTB.VS", | 9250 arm_UXTB_PL: "UXTB.PL", |
7894 arm_UXTB_VC: "UXTB.VC", | 9251 arm_UXTB_VS: "UXTB.VS", |
7895 arm_UXTB_HI: "UXTB.HI", | 9252 arm_UXTB_VC: "UXTB.VC", |
7896 arm_UXTB_LS: "UXTB.LS", | 9253 arm_UXTB_HI: "UXTB.HI", |
7897 arm_UXTB_GE: "UXTB.GE", | 9254 arm_UXTB_LS: "UXTB.LS", |
7898 arm_UXTB_LT: "UXTB.LT", | 9255 arm_UXTB_GE: "UXTB.GE", |
7899 arm_UXTB_GT: "UXTB.GT", | 9256 arm_UXTB_LT: "UXTB.LT", |
7900 arm_UXTB_LE: "UXTB.LE", | 9257 arm_UXTB_GT: "UXTB.GT", |
7901 arm_UXTB: "UXTB", | 9258 arm_UXTB_LE: "UXTB.LE", |
7902 arm_UXTB_ZZ: "UXTB.ZZ", | 9259 arm_UXTB: "UXTB", |
7903 arm_UXTB16_EQ: "UXTB16.EQ", | 9260 arm_UXTB_ZZ: "UXTB.ZZ", |
7904 arm_UXTB16_NE: "UXTB16.NE", | 9261 arm_UXTB16_EQ: "UXTB16.EQ", |
7905 arm_UXTB16_CS: "UXTB16.CS", | 9262 arm_UXTB16_NE: "UXTB16.NE", |
7906 arm_UXTB16_CC: "UXTB16.CC", | 9263 arm_UXTB16_CS: "UXTB16.CS", |
7907 arm_UXTB16_MI: "UXTB16.MI", | 9264 arm_UXTB16_CC: "UXTB16.CC", |
7908 arm_UXTB16_PL: "UXTB16.PL", | 9265 arm_UXTB16_MI: "UXTB16.MI", |
7909 arm_UXTB16_VS: "UXTB16.VS", | 9266 arm_UXTB16_PL: "UXTB16.PL", |
7910 arm_UXTB16_VC: "UXTB16.VC", | 9267 arm_UXTB16_VS: "UXTB16.VS", |
7911 arm_UXTB16_HI: "UXTB16.HI", | 9268 arm_UXTB16_VC: "UXTB16.VC", |
7912 arm_UXTB16_LS: "UXTB16.LS", | 9269 arm_UXTB16_HI: "UXTB16.HI", |
7913 arm_UXTB16_GE: "UXTB16.GE", | 9270 arm_UXTB16_LS: "UXTB16.LS", |
7914 arm_UXTB16_LT: "UXTB16.LT", | 9271 arm_UXTB16_GE: "UXTB16.GE", |
7915 arm_UXTB16_GT: "UXTB16.GT", | 9272 arm_UXTB16_LT: "UXTB16.LT", |
7916 arm_UXTB16_LE: "UXTB16.LE", | 9273 arm_UXTB16_GT: "UXTB16.GT", |
7917 arm_UXTB16: "UXTB16", | 9274 arm_UXTB16_LE: "UXTB16.LE", |
7918 arm_UXTB16_ZZ: "UXTB16.ZZ", | 9275 arm_UXTB16: "UXTB16", |
7919 arm_UXTH_EQ: "UXTH.EQ", | 9276 arm_UXTB16_ZZ: "UXTB16.ZZ", |
7920 arm_UXTH_NE: "UXTH.NE", | 9277 arm_UXTH_EQ: "UXTH.EQ", |
7921 arm_UXTH_CS: "UXTH.CS", | 9278 arm_UXTH_NE: "UXTH.NE", |
7922 arm_UXTH_CC: "UXTH.CC", | 9279 arm_UXTH_CS: "UXTH.CS", |
7923 arm_UXTH_MI: "UXTH.MI", | 9280 arm_UXTH_CC: "UXTH.CC", |
7924 arm_UXTH_PL: "UXTH.PL", | 9281 arm_UXTH_MI: "UXTH.MI", |
7925 arm_UXTH_VS: "UXTH.VS", | 9282 arm_UXTH_PL: "UXTH.PL", |
7926 arm_UXTH_VC: "UXTH.VC", | 9283 arm_UXTH_VS: "UXTH.VS", |
7927 arm_UXTH_HI: "UXTH.HI", | 9284 arm_UXTH_VC: "UXTH.VC", |
7928 arm_UXTH_LS: "UXTH.LS", | 9285 arm_UXTH_HI: "UXTH.HI", |
7929 arm_UXTH_GE: "UXTH.GE", | 9286 arm_UXTH_LS: "UXTH.LS", |
7930 arm_UXTH_LT: "UXTH.LT", | 9287 arm_UXTH_GE: "UXTH.GE", |
7931 arm_UXTH_GT: "UXTH.GT", | 9288 arm_UXTH_LT: "UXTH.LT", |
7932 arm_UXTH_LE: "UXTH.LE", | 9289 arm_UXTH_GT: "UXTH.GT", |
7933 arm_UXTH: "UXTH", | 9290 arm_UXTH_LE: "UXTH.LE", |
7934 arm_UXTH_ZZ: "UXTH.ZZ", | 9291 arm_UXTH: "UXTH", |
7935 arm_WFE_EQ: "WFE.EQ", | 9292 arm_UXTH_ZZ: "UXTH.ZZ", |
7936 arm_WFE_NE: "WFE.NE", | 9293 arm_VABS_EQ_F32: "VABS.EQ.F32", |
7937 arm_WFE_CS: "WFE.CS", | 9294 arm_VABS_NE_F32: "VABS.NE.F32", |
7938 arm_WFE_CC: "WFE.CC", | 9295 arm_VABS_CS_F32: "VABS.CS.F32", |
7939 arm_WFE_MI: "WFE.MI", | 9296 arm_VABS_CC_F32: "VABS.CC.F32", |
7940 arm_WFE_PL: "WFE.PL", | 9297 arm_VABS_MI_F32: "VABS.MI.F32", |
7941 arm_WFE_VS: "WFE.VS", | 9298 arm_VABS_PL_F32: "VABS.PL.F32", |
7942 arm_WFE_VC: "WFE.VC", | 9299 arm_VABS_VS_F32: "VABS.VS.F32", |
7943 arm_WFE_HI: "WFE.HI", | 9300 arm_VABS_VC_F32: "VABS.VC.F32", |
7944 arm_WFE_LS: "WFE.LS", | 9301 arm_VABS_HI_F32: "VABS.HI.F32", |
7945 arm_WFE_GE: "WFE.GE", | 9302 arm_VABS_LS_F32: "VABS.LS.F32", |
7946 arm_WFE_LT: "WFE.LT", | 9303 arm_VABS_GE_F32: "VABS.GE.F32", |
7947 arm_WFE_GT: "WFE.GT", | 9304 arm_VABS_LT_F32: "VABS.LT.F32", |
7948 arm_WFE_LE: "WFE.LE", | 9305 arm_VABS_GT_F32: "VABS.GT.F32", |
7949 arm_WFE: "WFE", | 9306 arm_VABS_LE_F32: "VABS.LE.F32", |
7950 arm_WFE_ZZ: "WFE.ZZ", | 9307 arm_VABS_F32: "VABS.F32", |
7951 arm_WFI_EQ: "WFI.EQ", | 9308 arm_VABS_ZZ_F32: "VABS.ZZ.F32", |
7952 arm_WFI_NE: "WFI.NE", | 9309 arm_VABS_EQ_F64: "VABS.EQ.F64", |
7953 arm_WFI_CS: "WFI.CS", | 9310 arm_VABS_NE_F64: "VABS.NE.F64", |
7954 arm_WFI_CC: "WFI.CC", | 9311 arm_VABS_CS_F64: "VABS.CS.F64", |
7955 arm_WFI_MI: "WFI.MI", | 9312 arm_VABS_CC_F64: "VABS.CC.F64", |
7956 arm_WFI_PL: "WFI.PL", | 9313 arm_VABS_MI_F64: "VABS.MI.F64", |
7957 arm_WFI_VS: "WFI.VS", | 9314 arm_VABS_PL_F64: "VABS.PL.F64", |
7958 arm_WFI_VC: "WFI.VC", | 9315 arm_VABS_VS_F64: "VABS.VS.F64", |
7959 arm_WFI_HI: "WFI.HI", | 9316 arm_VABS_VC_F64: "VABS.VC.F64", |
7960 arm_WFI_LS: "WFI.LS", | 9317 arm_VABS_HI_F64: "VABS.HI.F64", |
7961 arm_WFI_GE: "WFI.GE", | 9318 arm_VABS_LS_F64: "VABS.LS.F64", |
7962 arm_WFI_LT: "WFI.LT", | 9319 arm_VABS_GE_F64: "VABS.GE.F64", |
7963 arm_WFI_GT: "WFI.GT", | 9320 arm_VABS_LT_F64: "VABS.LT.F64", |
7964 arm_WFI_LE: "WFI.LE", | 9321 arm_VABS_GT_F64: "VABS.GT.F64", |
7965 arm_WFI: "WFI", | 9322 arm_VABS_LE_F64: "VABS.LE.F64", |
7966 arm_WFI_ZZ: "WFI.ZZ", | 9323 arm_VABS_F64: "VABS.F64", |
7967 arm_YIELD_EQ: "YIELD.EQ", | 9324 arm_VABS_ZZ_F64: "VABS.ZZ.F64", |
7968 arm_YIELD_NE: "YIELD.NE", | 9325 arm_VADD_EQ_F32: "VADD.EQ.F32", |
7969 arm_YIELD_CS: "YIELD.CS", | 9326 arm_VADD_NE_F32: "VADD.NE.F32", |
7970 arm_YIELD_CC: "YIELD.CC", | 9327 arm_VADD_CS_F32: "VADD.CS.F32", |
7971 arm_YIELD_MI: "YIELD.MI", | 9328 arm_VADD_CC_F32: "VADD.CC.F32", |
7972 arm_YIELD_PL: "YIELD.PL", | 9329 arm_VADD_MI_F32: "VADD.MI.F32", |
7973 arm_YIELD_VS: "YIELD.VS", | 9330 arm_VADD_PL_F32: "VADD.PL.F32", |
7974 arm_YIELD_VC: "YIELD.VC", | 9331 arm_VADD_VS_F32: "VADD.VS.F32", |
7975 arm_YIELD_HI: "YIELD.HI", | 9332 arm_VADD_VC_F32: "VADD.VC.F32", |
7976 arm_YIELD_LS: "YIELD.LS", | 9333 arm_VADD_HI_F32: "VADD.HI.F32", |
7977 arm_YIELD_GE: "YIELD.GE", | 9334 arm_VADD_LS_F32: "VADD.LS.F32", |
7978 arm_YIELD_LT: "YIELD.LT", | 9335 arm_VADD_GE_F32: "VADD.GE.F32", |
7979 arm_YIELD_GT: "YIELD.GT", | 9336 arm_VADD_LT_F32: "VADD.LT.F32", |
7980 arm_YIELD_LE: "YIELD.LE", | 9337 arm_VADD_GT_F32: "VADD.GT.F32", |
7981 arm_YIELD: "YIELD", | 9338 arm_VADD_LE_F32: "VADD.LE.F32", |
7982 arm_YIELD_ZZ: "YIELD.ZZ", | 9339 arm_VADD_F32: "VADD.F32", |
| 9340 arm_VADD_ZZ_F32: "VADD.ZZ.F32", |
| 9341 arm_VADD_EQ_F64: "VADD.EQ.F64", |
| 9342 arm_VADD_NE_F64: "VADD.NE.F64", |
| 9343 arm_VADD_CS_F64: "VADD.CS.F64", |
| 9344 arm_VADD_CC_F64: "VADD.CC.F64", |
| 9345 arm_VADD_MI_F64: "VADD.MI.F64", |
| 9346 arm_VADD_PL_F64: "VADD.PL.F64", |
| 9347 arm_VADD_VS_F64: "VADD.VS.F64", |
| 9348 arm_VADD_VC_F64: "VADD.VC.F64", |
| 9349 arm_VADD_HI_F64: "VADD.HI.F64", |
| 9350 arm_VADD_LS_F64: "VADD.LS.F64", |
| 9351 arm_VADD_GE_F64: "VADD.GE.F64", |
| 9352 arm_VADD_LT_F64: "VADD.LT.F64", |
| 9353 arm_VADD_GT_F64: "VADD.GT.F64", |
| 9354 arm_VADD_LE_F64: "VADD.LE.F64", |
| 9355 arm_VADD_F64: "VADD.F64", |
| 9356 arm_VADD_ZZ_F64: "VADD.ZZ.F64", |
| 9357 arm_VCMP_EQ_F32: "VCMP.EQ.F32", |
| 9358 arm_VCMP_NE_F32: "VCMP.NE.F32", |
| 9359 arm_VCMP_CS_F32: "VCMP.CS.F32", |
| 9360 arm_VCMP_CC_F32: "VCMP.CC.F32", |
| 9361 arm_VCMP_MI_F32: "VCMP.MI.F32", |
| 9362 arm_VCMP_PL_F32: "VCMP.PL.F32", |
| 9363 arm_VCMP_VS_F32: "VCMP.VS.F32", |
| 9364 arm_VCMP_VC_F32: "VCMP.VC.F32", |
| 9365 arm_VCMP_HI_F32: "VCMP.HI.F32", |
| 9366 arm_VCMP_LS_F32: "VCMP.LS.F32", |
| 9367 arm_VCMP_GE_F32: "VCMP.GE.F32", |
| 9368 arm_VCMP_LT_F32: "VCMP.LT.F32", |
| 9369 arm_VCMP_GT_F32: "VCMP.GT.F32", |
| 9370 arm_VCMP_LE_F32: "VCMP.LE.F32", |
| 9371 arm_VCMP_F32: "VCMP.F32", |
| 9372 arm_VCMP_ZZ_F32: "VCMP.ZZ.F32", |
| 9373 arm_VCMP_EQ_F64: "VCMP.EQ.F64", |
| 9374 arm_VCMP_NE_F64: "VCMP.NE.F64", |
| 9375 arm_VCMP_CS_F64: "VCMP.CS.F64", |
| 9376 arm_VCMP_CC_F64: "VCMP.CC.F64", |
| 9377 arm_VCMP_MI_F64: "VCMP.MI.F64", |
| 9378 arm_VCMP_PL_F64: "VCMP.PL.F64", |
| 9379 arm_VCMP_VS_F64: "VCMP.VS.F64", |
| 9380 arm_VCMP_VC_F64: "VCMP.VC.F64", |
| 9381 arm_VCMP_HI_F64: "VCMP.HI.F64", |
| 9382 arm_VCMP_LS_F64: "VCMP.LS.F64", |
| 9383 arm_VCMP_GE_F64: "VCMP.GE.F64", |
| 9384 arm_VCMP_LT_F64: "VCMP.LT.F64", |
| 9385 arm_VCMP_GT_F64: "VCMP.GT.F64", |
| 9386 arm_VCMP_LE_F64: "VCMP.LE.F64", |
| 9387 arm_VCMP_F64: "VCMP.F64", |
| 9388 arm_VCMP_ZZ_F64: "VCMP.ZZ.F64", |
| 9389 arm_VCMP_E_EQ_F32: "VCMP.E.EQ.F32", |
| 9390 arm_VCMP_E_NE_F32: "VCMP.E.NE.F32", |
| 9391 arm_VCMP_E_CS_F32: "VCMP.E.CS.F32", |
| 9392 arm_VCMP_E_CC_F32: "VCMP.E.CC.F32", |
| 9393 arm_VCMP_E_MI_F32: "VCMP.E.MI.F32", |
| 9394 arm_VCMP_E_PL_F32: "VCMP.E.PL.F32", |
| 9395 arm_VCMP_E_VS_F32: "VCMP.E.VS.F32", |
| 9396 arm_VCMP_E_VC_F32: "VCMP.E.VC.F32", |
| 9397 arm_VCMP_E_HI_F32: "VCMP.E.HI.F32", |
| 9398 arm_VCMP_E_LS_F32: "VCMP.E.LS.F32", |
| 9399 arm_VCMP_E_GE_F32: "VCMP.E.GE.F32", |
| 9400 arm_VCMP_E_LT_F32: "VCMP.E.LT.F32", |
| 9401 arm_VCMP_E_GT_F32: "VCMP.E.GT.F32", |
| 9402 arm_VCMP_E_LE_F32: "VCMP.E.LE.F32", |
| 9403 arm_VCMP_E_F32: "VCMP.E.F32", |
| 9404 arm_VCMP_E_ZZ_F32: "VCMP.E.ZZ.F32", |
| 9405 arm_VCMP_E_EQ_F64: "VCMP.E.EQ.F64", |
| 9406 arm_VCMP_E_NE_F64: "VCMP.E.NE.F64", |
| 9407 arm_VCMP_E_CS_F64: "VCMP.E.CS.F64", |
| 9408 arm_VCMP_E_CC_F64: "VCMP.E.CC.F64", |
| 9409 arm_VCMP_E_MI_F64: "VCMP.E.MI.F64", |
| 9410 arm_VCMP_E_PL_F64: "VCMP.E.PL.F64", |
| 9411 arm_VCMP_E_VS_F64: "VCMP.E.VS.F64", |
| 9412 arm_VCMP_E_VC_F64: "VCMP.E.VC.F64", |
| 9413 arm_VCMP_E_HI_F64: "VCMP.E.HI.F64", |
| 9414 arm_VCMP_E_LS_F64: "VCMP.E.LS.F64", |
| 9415 arm_VCMP_E_GE_F64: "VCMP.E.GE.F64", |
| 9416 arm_VCMP_E_LT_F64: "VCMP.E.LT.F64", |
| 9417 arm_VCMP_E_GT_F64: "VCMP.E.GT.F64", |
| 9418 arm_VCMP_E_LE_F64: "VCMP.E.LE.F64", |
| 9419 arm_VCMP_E_F64: "VCMP.E.F64", |
| 9420 arm_VCMP_E_ZZ_F64: "VCMP.E.ZZ.F64", |
| 9421 arm_VCVT_EQ_F32_FXS16: "VCVT.EQ.F32.FXS16", |
| 9422 arm_VCVT_NE_F32_FXS16: "VCVT.NE.F32.FXS16", |
| 9423 arm_VCVT_CS_F32_FXS16: "VCVT.CS.F32.FXS16", |
| 9424 arm_VCVT_CC_F32_FXS16: "VCVT.CC.F32.FXS16", |
| 9425 arm_VCVT_MI_F32_FXS16: "VCVT.MI.F32.FXS16", |
| 9426 arm_VCVT_PL_F32_FXS16: "VCVT.PL.F32.FXS16", |
| 9427 arm_VCVT_VS_F32_FXS16: "VCVT.VS.F32.FXS16", |
| 9428 arm_VCVT_VC_F32_FXS16: "VCVT.VC.F32.FXS16", |
| 9429 arm_VCVT_HI_F32_FXS16: "VCVT.HI.F32.FXS16", |
| 9430 arm_VCVT_LS_F32_FXS16: "VCVT.LS.F32.FXS16", |
| 9431 arm_VCVT_GE_F32_FXS16: "VCVT.GE.F32.FXS16", |
| 9432 arm_VCVT_LT_F32_FXS16: "VCVT.LT.F32.FXS16", |
| 9433 arm_VCVT_GT_F32_FXS16: "VCVT.GT.F32.FXS16", |
| 9434 arm_VCVT_LE_F32_FXS16: "VCVT.LE.F32.FXS16", |
| 9435 arm_VCVT_F32_FXS16: "VCVT.F32.FXS16", |
| 9436 arm_VCVT_ZZ_F32_FXS16: "VCVT.ZZ.F32.FXS16", |
| 9437 arm_VCVT_EQ_F32_FXS32: "VCVT.EQ.F32.FXS32", |
| 9438 arm_VCVT_NE_F32_FXS32: "VCVT.NE.F32.FXS32", |
| 9439 arm_VCVT_CS_F32_FXS32: "VCVT.CS.F32.FXS32", |
| 9440 arm_VCVT_CC_F32_FXS32: "VCVT.CC.F32.FXS32", |
| 9441 arm_VCVT_MI_F32_FXS32: "VCVT.MI.F32.FXS32", |
| 9442 arm_VCVT_PL_F32_FXS32: "VCVT.PL.F32.FXS32", |
| 9443 arm_VCVT_VS_F32_FXS32: "VCVT.VS.F32.FXS32", |
| 9444 arm_VCVT_VC_F32_FXS32: "VCVT.VC.F32.FXS32", |
| 9445 arm_VCVT_HI_F32_FXS32: "VCVT.HI.F32.FXS32", |
| 9446 arm_VCVT_LS_F32_FXS32: "VCVT.LS.F32.FXS32", |
| 9447 arm_VCVT_GE_F32_FXS32: "VCVT.GE.F32.FXS32", |
| 9448 arm_VCVT_LT_F32_FXS32: "VCVT.LT.F32.FXS32", |
| 9449 arm_VCVT_GT_F32_FXS32: "VCVT.GT.F32.FXS32", |
| 9450 arm_VCVT_LE_F32_FXS32: "VCVT.LE.F32.FXS32", |
| 9451 arm_VCVT_F32_FXS32: "VCVT.F32.FXS32", |
| 9452 arm_VCVT_ZZ_F32_FXS32: "VCVT.ZZ.F32.FXS32", |
| 9453 arm_VCVT_EQ_F32_FXU16: "VCVT.EQ.F32.FXU16", |
| 9454 arm_VCVT_NE_F32_FXU16: "VCVT.NE.F32.FXU16", |
| 9455 arm_VCVT_CS_F32_FXU16: "VCVT.CS.F32.FXU16", |
| 9456 arm_VCVT_CC_F32_FXU16: "VCVT.CC.F32.FXU16", |
| 9457 arm_VCVT_MI_F32_FXU16: "VCVT.MI.F32.FXU16", |
| 9458 arm_VCVT_PL_F32_FXU16: "VCVT.PL.F32.FXU16", |
| 9459 arm_VCVT_VS_F32_FXU16: "VCVT.VS.F32.FXU16", |
| 9460 arm_VCVT_VC_F32_FXU16: "VCVT.VC.F32.FXU16", |
| 9461 arm_VCVT_HI_F32_FXU16: "VCVT.HI.F32.FXU16", |
| 9462 arm_VCVT_LS_F32_FXU16: "VCVT.LS.F32.FXU16", |
| 9463 arm_VCVT_GE_F32_FXU16: "VCVT.GE.F32.FXU16", |
| 9464 arm_VCVT_LT_F32_FXU16: "VCVT.LT.F32.FXU16", |
| 9465 arm_VCVT_GT_F32_FXU16: "VCVT.GT.F32.FXU16", |
| 9466 arm_VCVT_LE_F32_FXU16: "VCVT.LE.F32.FXU16", |
| 9467 arm_VCVT_F32_FXU16: "VCVT.F32.FXU16", |
| 9468 arm_VCVT_ZZ_F32_FXU16: "VCVT.ZZ.F32.FXU16", |
| 9469 arm_VCVT_EQ_F32_FXU32: "VCVT.EQ.F32.FXU32", |
| 9470 arm_VCVT_NE_F32_FXU32: "VCVT.NE.F32.FXU32", |
| 9471 arm_VCVT_CS_F32_FXU32: "VCVT.CS.F32.FXU32", |
| 9472 arm_VCVT_CC_F32_FXU32: "VCVT.CC.F32.FXU32", |
| 9473 arm_VCVT_MI_F32_FXU32: "VCVT.MI.F32.FXU32", |
| 9474 arm_VCVT_PL_F32_FXU32: "VCVT.PL.F32.FXU32", |
| 9475 arm_VCVT_VS_F32_FXU32: "VCVT.VS.F32.FXU32", |
| 9476 arm_VCVT_VC_F32_FXU32: "VCVT.VC.F32.FXU32", |
| 9477 arm_VCVT_HI_F32_FXU32: "VCVT.HI.F32.FXU32", |
| 9478 arm_VCVT_LS_F32_FXU32: "VCVT.LS.F32.FXU32", |
| 9479 arm_VCVT_GE_F32_FXU32: "VCVT.GE.F32.FXU32", |
| 9480 arm_VCVT_LT_F32_FXU32: "VCVT.LT.F32.FXU32", |
| 9481 arm_VCVT_GT_F32_FXU32: "VCVT.GT.F32.FXU32", |
| 9482 arm_VCVT_LE_F32_FXU32: "VCVT.LE.F32.FXU32", |
| 9483 arm_VCVT_F32_FXU32: "VCVT.F32.FXU32", |
| 9484 arm_VCVT_ZZ_F32_FXU32: "VCVT.ZZ.F32.FXU32", |
| 9485 arm_VCVT_EQ_F64_FXS16: "VCVT.EQ.F64.FXS16", |
| 9486 arm_VCVT_NE_F64_FXS16: "VCVT.NE.F64.FXS16", |
| 9487 arm_VCVT_CS_F64_FXS16: "VCVT.CS.F64.FXS16", |
| 9488 arm_VCVT_CC_F64_FXS16: "VCVT.CC.F64.FXS16", |
| 9489 arm_VCVT_MI_F64_FXS16: "VCVT.MI.F64.FXS16", |
| 9490 arm_VCVT_PL_F64_FXS16: "VCVT.PL.F64.FXS16", |
| 9491 arm_VCVT_VS_F64_FXS16: "VCVT.VS.F64.FXS16", |
| 9492 arm_VCVT_VC_F64_FXS16: "VCVT.VC.F64.FXS16", |
| 9493 arm_VCVT_HI_F64_FXS16: "VCVT.HI.F64.FXS16", |
| 9494 arm_VCVT_LS_F64_FXS16: "VCVT.LS.F64.FXS16", |
| 9495 arm_VCVT_GE_F64_FXS16: "VCVT.GE.F64.FXS16", |
| 9496 arm_VCVT_LT_F64_FXS16: "VCVT.LT.F64.FXS16", |
| 9497 arm_VCVT_GT_F64_FXS16: "VCVT.GT.F64.FXS16", |
| 9498 arm_VCVT_LE_F64_FXS16: "VCVT.LE.F64.FXS16", |
| 9499 arm_VCVT_F64_FXS16: "VCVT.F64.FXS16", |
| 9500 arm_VCVT_ZZ_F64_FXS16: "VCVT.ZZ.F64.FXS16", |
| 9501 arm_VCVT_EQ_F64_FXS32: "VCVT.EQ.F64.FXS32", |
| 9502 arm_VCVT_NE_F64_FXS32: "VCVT.NE.F64.FXS32", |
| 9503 arm_VCVT_CS_F64_FXS32: "VCVT.CS.F64.FXS32", |
| 9504 arm_VCVT_CC_F64_FXS32: "VCVT.CC.F64.FXS32", |
| 9505 arm_VCVT_MI_F64_FXS32: "VCVT.MI.F64.FXS32", |
| 9506 arm_VCVT_PL_F64_FXS32: "VCVT.PL.F64.FXS32", |
| 9507 arm_VCVT_VS_F64_FXS32: "VCVT.VS.F64.FXS32", |
| 9508 arm_VCVT_VC_F64_FXS32: "VCVT.VC.F64.FXS32", |
| 9509 arm_VCVT_HI_F64_FXS32: "VCVT.HI.F64.FXS32", |
| 9510 arm_VCVT_LS_F64_FXS32: "VCVT.LS.F64.FXS32", |
| 9511 arm_VCVT_GE_F64_FXS32: "VCVT.GE.F64.FXS32", |
| 9512 arm_VCVT_LT_F64_FXS32: "VCVT.LT.F64.FXS32", |
| 9513 arm_VCVT_GT_F64_FXS32: "VCVT.GT.F64.FXS32", |
| 9514 arm_VCVT_LE_F64_FXS32: "VCVT.LE.F64.FXS32", |
| 9515 arm_VCVT_F64_FXS32: "VCVT.F64.FXS32", |
| 9516 arm_VCVT_ZZ_F64_FXS32: "VCVT.ZZ.F64.FXS32", |
| 9517 arm_VCVT_EQ_F64_FXU16: "VCVT.EQ.F64.FXU16", |
| 9518 arm_VCVT_NE_F64_FXU16: "VCVT.NE.F64.FXU16", |
| 9519 arm_VCVT_CS_F64_FXU16: "VCVT.CS.F64.FXU16", |
| 9520 arm_VCVT_CC_F64_FXU16: "VCVT.CC.F64.FXU16", |
| 9521 arm_VCVT_MI_F64_FXU16: "VCVT.MI.F64.FXU16", |
| 9522 arm_VCVT_PL_F64_FXU16: "VCVT.PL.F64.FXU16", |
| 9523 arm_VCVT_VS_F64_FXU16: "VCVT.VS.F64.FXU16", |
| 9524 arm_VCVT_VC_F64_FXU16: "VCVT.VC.F64.FXU16", |
| 9525 arm_VCVT_HI_F64_FXU16: "VCVT.HI.F64.FXU16", |
| 9526 arm_VCVT_LS_F64_FXU16: "VCVT.LS.F64.FXU16", |
| 9527 arm_VCVT_GE_F64_FXU16: "VCVT.GE.F64.FXU16", |
| 9528 arm_VCVT_LT_F64_FXU16: "VCVT.LT.F64.FXU16", |
| 9529 arm_VCVT_GT_F64_FXU16: "VCVT.GT.F64.FXU16", |
| 9530 arm_VCVT_LE_F64_FXU16: "VCVT.LE.F64.FXU16", |
| 9531 arm_VCVT_F64_FXU16: "VCVT.F64.FXU16", |
| 9532 arm_VCVT_ZZ_F64_FXU16: "VCVT.ZZ.F64.FXU16", |
| 9533 arm_VCVT_EQ_F64_FXU32: "VCVT.EQ.F64.FXU32", |
| 9534 arm_VCVT_NE_F64_FXU32: "VCVT.NE.F64.FXU32", |
| 9535 arm_VCVT_CS_F64_FXU32: "VCVT.CS.F64.FXU32", |
| 9536 arm_VCVT_CC_F64_FXU32: "VCVT.CC.F64.FXU32", |
| 9537 arm_VCVT_MI_F64_FXU32: "VCVT.MI.F64.FXU32", |
| 9538 arm_VCVT_PL_F64_FXU32: "VCVT.PL.F64.FXU32", |
| 9539 arm_VCVT_VS_F64_FXU32: "VCVT.VS.F64.FXU32", |
| 9540 arm_VCVT_VC_F64_FXU32: "VCVT.VC.F64.FXU32", |
| 9541 arm_VCVT_HI_F64_FXU32: "VCVT.HI.F64.FXU32", |
| 9542 arm_VCVT_LS_F64_FXU32: "VCVT.LS.F64.FXU32", |
| 9543 arm_VCVT_GE_F64_FXU32: "VCVT.GE.F64.FXU32", |
| 9544 arm_VCVT_LT_F64_FXU32: "VCVT.LT.F64.FXU32", |
| 9545 arm_VCVT_GT_F64_FXU32: "VCVT.GT.F64.FXU32", |
| 9546 arm_VCVT_LE_F64_FXU32: "VCVT.LE.F64.FXU32", |
| 9547 arm_VCVT_F64_FXU32: "VCVT.F64.FXU32", |
| 9548 arm_VCVT_ZZ_F64_FXU32: "VCVT.ZZ.F64.FXU32", |
| 9549 arm_VCVT_EQ_F32_U32: "VCVT.EQ.F32.U32", |
| 9550 arm_VCVT_NE_F32_U32: "VCVT.NE.F32.U32", |
| 9551 arm_VCVT_CS_F32_U32: "VCVT.CS.F32.U32", |
| 9552 arm_VCVT_CC_F32_U32: "VCVT.CC.F32.U32", |
| 9553 arm_VCVT_MI_F32_U32: "VCVT.MI.F32.U32", |
| 9554 arm_VCVT_PL_F32_U32: "VCVT.PL.F32.U32", |
| 9555 arm_VCVT_VS_F32_U32: "VCVT.VS.F32.U32", |
| 9556 arm_VCVT_VC_F32_U32: "VCVT.VC.F32.U32", |
| 9557 arm_VCVT_HI_F32_U32: "VCVT.HI.F32.U32", |
| 9558 arm_VCVT_LS_F32_U32: "VCVT.LS.F32.U32", |
| 9559 arm_VCVT_GE_F32_U32: "VCVT.GE.F32.U32", |
| 9560 arm_VCVT_LT_F32_U32: "VCVT.LT.F32.U32", |
| 9561 arm_VCVT_GT_F32_U32: "VCVT.GT.F32.U32", |
| 9562 arm_VCVT_LE_F32_U32: "VCVT.LE.F32.U32", |
| 9563 arm_VCVT_F32_U32: "VCVT.F32.U32", |
| 9564 arm_VCVT_ZZ_F32_U32: "VCVT.ZZ.F32.U32", |
| 9565 arm_VCVT_EQ_F32_S32: "VCVT.EQ.F32.S32", |
| 9566 arm_VCVT_NE_F32_S32: "VCVT.NE.F32.S32", |
| 9567 arm_VCVT_CS_F32_S32: "VCVT.CS.F32.S32", |
| 9568 arm_VCVT_CC_F32_S32: "VCVT.CC.F32.S32", |
| 9569 arm_VCVT_MI_F32_S32: "VCVT.MI.F32.S32", |
| 9570 arm_VCVT_PL_F32_S32: "VCVT.PL.F32.S32", |
| 9571 arm_VCVT_VS_F32_S32: "VCVT.VS.F32.S32", |
| 9572 arm_VCVT_VC_F32_S32: "VCVT.VC.F32.S32", |
| 9573 arm_VCVT_HI_F32_S32: "VCVT.HI.F32.S32", |
| 9574 arm_VCVT_LS_F32_S32: "VCVT.LS.F32.S32", |
| 9575 arm_VCVT_GE_F32_S32: "VCVT.GE.F32.S32", |
| 9576 arm_VCVT_LT_F32_S32: "VCVT.LT.F32.S32", |
| 9577 arm_VCVT_GT_F32_S32: "VCVT.GT.F32.S32", |
| 9578 arm_VCVT_LE_F32_S32: "VCVT.LE.F32.S32", |
| 9579 arm_VCVT_F32_S32: "VCVT.F32.S32", |
| 9580 arm_VCVT_ZZ_F32_S32: "VCVT.ZZ.F32.S32", |
| 9581 arm_VCVT_EQ_F64_U32: "VCVT.EQ.F64.U32", |
| 9582 arm_VCVT_NE_F64_U32: "VCVT.NE.F64.U32", |
| 9583 arm_VCVT_CS_F64_U32: "VCVT.CS.F64.U32", |
| 9584 arm_VCVT_CC_F64_U32: "VCVT.CC.F64.U32", |
| 9585 arm_VCVT_MI_F64_U32: "VCVT.MI.F64.U32", |
| 9586 arm_VCVT_PL_F64_U32: "VCVT.PL.F64.U32", |
| 9587 arm_VCVT_VS_F64_U32: "VCVT.VS.F64.U32", |
| 9588 arm_VCVT_VC_F64_U32: "VCVT.VC.F64.U32", |
| 9589 arm_VCVT_HI_F64_U32: "VCVT.HI.F64.U32", |
| 9590 arm_VCVT_LS_F64_U32: "VCVT.LS.F64.U32", |
| 9591 arm_VCVT_GE_F64_U32: "VCVT.GE.F64.U32", |
| 9592 arm_VCVT_LT_F64_U32: "VCVT.LT.F64.U32", |
| 9593 arm_VCVT_GT_F64_U32: "VCVT.GT.F64.U32", |
| 9594 arm_VCVT_LE_F64_U32: "VCVT.LE.F64.U32", |
| 9595 arm_VCVT_F64_U32: "VCVT.F64.U32", |
| 9596 arm_VCVT_ZZ_F64_U32: "VCVT.ZZ.F64.U32", |
| 9597 arm_VCVT_EQ_F64_S32: "VCVT.EQ.F64.S32", |
| 9598 arm_VCVT_NE_F64_S32: "VCVT.NE.F64.S32", |
| 9599 arm_VCVT_CS_F64_S32: "VCVT.CS.F64.S32", |
| 9600 arm_VCVT_CC_F64_S32: "VCVT.CC.F64.S32", |
| 9601 arm_VCVT_MI_F64_S32: "VCVT.MI.F64.S32", |
| 9602 arm_VCVT_PL_F64_S32: "VCVT.PL.F64.S32", |
| 9603 arm_VCVT_VS_F64_S32: "VCVT.VS.F64.S32", |
| 9604 arm_VCVT_VC_F64_S32: "VCVT.VC.F64.S32", |
| 9605 arm_VCVT_HI_F64_S32: "VCVT.HI.F64.S32", |
| 9606 arm_VCVT_LS_F64_S32: "VCVT.LS.F64.S32", |
| 9607 arm_VCVT_GE_F64_S32: "VCVT.GE.F64.S32", |
| 9608 arm_VCVT_LT_F64_S32: "VCVT.LT.F64.S32", |
| 9609 arm_VCVT_GT_F64_S32: "VCVT.GT.F64.S32", |
| 9610 arm_VCVT_LE_F64_S32: "VCVT.LE.F64.S32", |
| 9611 arm_VCVT_F64_S32: "VCVT.F64.S32", |
| 9612 arm_VCVT_ZZ_F64_S32: "VCVT.ZZ.F64.S32", |
| 9613 arm_VCVT_EQ_F64_F32: "VCVT.EQ.F64.F32", |
| 9614 arm_VCVT_NE_F64_F32: "VCVT.NE.F64.F32", |
| 9615 arm_VCVT_CS_F64_F32: "VCVT.CS.F64.F32", |
| 9616 arm_VCVT_CC_F64_F32: "VCVT.CC.F64.F32", |
| 9617 arm_VCVT_MI_F64_F32: "VCVT.MI.F64.F32", |
| 9618 arm_VCVT_PL_F64_F32: "VCVT.PL.F64.F32", |
| 9619 arm_VCVT_VS_F64_F32: "VCVT.VS.F64.F32", |
| 9620 arm_VCVT_VC_F64_F32: "VCVT.VC.F64.F32", |
| 9621 arm_VCVT_HI_F64_F32: "VCVT.HI.F64.F32", |
| 9622 arm_VCVT_LS_F64_F32: "VCVT.LS.F64.F32", |
| 9623 arm_VCVT_GE_F64_F32: "VCVT.GE.F64.F32", |
| 9624 arm_VCVT_LT_F64_F32: "VCVT.LT.F64.F32", |
| 9625 arm_VCVT_GT_F64_F32: "VCVT.GT.F64.F32", |
| 9626 arm_VCVT_LE_F64_F32: "VCVT.LE.F64.F32", |
| 9627 arm_VCVT_F64_F32: "VCVT.F64.F32", |
| 9628 arm_VCVT_ZZ_F64_F32: "VCVT.ZZ.F64.F32", |
| 9629 arm_VCVT_EQ_F32_F64: "VCVT.EQ.F32.F64", |
| 9630 arm_VCVT_NE_F32_F64: "VCVT.NE.F32.F64", |
| 9631 arm_VCVT_CS_F32_F64: "VCVT.CS.F32.F64", |
| 9632 arm_VCVT_CC_F32_F64: "VCVT.CC.F32.F64", |
| 9633 arm_VCVT_MI_F32_F64: "VCVT.MI.F32.F64", |
| 9634 arm_VCVT_PL_F32_F64: "VCVT.PL.F32.F64", |
| 9635 arm_VCVT_VS_F32_F64: "VCVT.VS.F32.F64", |
| 9636 arm_VCVT_VC_F32_F64: "VCVT.VC.F32.F64", |
| 9637 arm_VCVT_HI_F32_F64: "VCVT.HI.F32.F64", |
| 9638 arm_VCVT_LS_F32_F64: "VCVT.LS.F32.F64", |
| 9639 arm_VCVT_GE_F32_F64: "VCVT.GE.F32.F64", |
| 9640 arm_VCVT_LT_F32_F64: "VCVT.LT.F32.F64", |
| 9641 arm_VCVT_GT_F32_F64: "VCVT.GT.F32.F64", |
| 9642 arm_VCVT_LE_F32_F64: "VCVT.LE.F32.F64", |
| 9643 arm_VCVT_F32_F64: "VCVT.F32.F64", |
| 9644 arm_VCVT_ZZ_F32_F64: "VCVT.ZZ.F32.F64", |
| 9645 arm_VCVT_EQ_FXS16_F32: "VCVT.EQ.FXS16.F32", |
| 9646 arm_VCVT_NE_FXS16_F32: "VCVT.NE.FXS16.F32", |
| 9647 arm_VCVT_CS_FXS16_F32: "VCVT.CS.FXS16.F32", |
| 9648 arm_VCVT_CC_FXS16_F32: "VCVT.CC.FXS16.F32", |
| 9649 arm_VCVT_MI_FXS16_F32: "VCVT.MI.FXS16.F32", |
| 9650 arm_VCVT_PL_FXS16_F32: "VCVT.PL.FXS16.F32", |
| 9651 arm_VCVT_VS_FXS16_F32: "VCVT.VS.FXS16.F32", |
| 9652 arm_VCVT_VC_FXS16_F32: "VCVT.VC.FXS16.F32", |
| 9653 arm_VCVT_HI_FXS16_F32: "VCVT.HI.FXS16.F32", |
| 9654 arm_VCVT_LS_FXS16_F32: "VCVT.LS.FXS16.F32", |
| 9655 arm_VCVT_GE_FXS16_F32: "VCVT.GE.FXS16.F32", |
| 9656 arm_VCVT_LT_FXS16_F32: "VCVT.LT.FXS16.F32", |
| 9657 arm_VCVT_GT_FXS16_F32: "VCVT.GT.FXS16.F32", |
| 9658 arm_VCVT_LE_FXS16_F32: "VCVT.LE.FXS16.F32", |
| 9659 arm_VCVT_FXS16_F32: "VCVT.FXS16.F32", |
| 9660 arm_VCVT_ZZ_FXS16_F32: "VCVT.ZZ.FXS16.F32", |
| 9661 arm_VCVT_EQ_FXS16_F64: "VCVT.EQ.FXS16.F64", |
| 9662 arm_VCVT_NE_FXS16_F64: "VCVT.NE.FXS16.F64", |
| 9663 arm_VCVT_CS_FXS16_F64: "VCVT.CS.FXS16.F64", |
| 9664 arm_VCVT_CC_FXS16_F64: "VCVT.CC.FXS16.F64", |
| 9665 arm_VCVT_MI_FXS16_F64: "VCVT.MI.FXS16.F64", |
| 9666 arm_VCVT_PL_FXS16_F64: "VCVT.PL.FXS16.F64", |
| 9667 arm_VCVT_VS_FXS16_F64: "VCVT.VS.FXS16.F64", |
| 9668 arm_VCVT_VC_FXS16_F64: "VCVT.VC.FXS16.F64", |
| 9669 arm_VCVT_HI_FXS16_F64: "VCVT.HI.FXS16.F64", |
| 9670 arm_VCVT_LS_FXS16_F64: "VCVT.LS.FXS16.F64", |
| 9671 arm_VCVT_GE_FXS16_F64: "VCVT.GE.FXS16.F64", |
| 9672 arm_VCVT_LT_FXS16_F64: "VCVT.LT.FXS16.F64", |
| 9673 arm_VCVT_GT_FXS16_F64: "VCVT.GT.FXS16.F64", |
| 9674 arm_VCVT_LE_FXS16_F64: "VCVT.LE.FXS16.F64", |
| 9675 arm_VCVT_FXS16_F64: "VCVT.FXS16.F64", |
| 9676 arm_VCVT_ZZ_FXS16_F64: "VCVT.ZZ.FXS16.F64", |
| 9677 arm_VCVT_EQ_FXS32_F32: "VCVT.EQ.FXS32.F32", |
| 9678 arm_VCVT_NE_FXS32_F32: "VCVT.NE.FXS32.F32", |
| 9679 arm_VCVT_CS_FXS32_F32: "VCVT.CS.FXS32.F32", |
| 9680 arm_VCVT_CC_FXS32_F32: "VCVT.CC.FXS32.F32", |
| 9681 arm_VCVT_MI_FXS32_F32: "VCVT.MI.FXS32.F32", |
| 9682 arm_VCVT_PL_FXS32_F32: "VCVT.PL.FXS32.F32", |
| 9683 arm_VCVT_VS_FXS32_F32: "VCVT.VS.FXS32.F32", |
| 9684 arm_VCVT_VC_FXS32_F32: "VCVT.VC.FXS32.F32", |
| 9685 arm_VCVT_HI_FXS32_F32: "VCVT.HI.FXS32.F32", |
| 9686 arm_VCVT_LS_FXS32_F32: "VCVT.LS.FXS32.F32", |
| 9687 arm_VCVT_GE_FXS32_F32: "VCVT.GE.FXS32.F32", |
| 9688 arm_VCVT_LT_FXS32_F32: "VCVT.LT.FXS32.F32", |
| 9689 arm_VCVT_GT_FXS32_F32: "VCVT.GT.FXS32.F32", |
| 9690 arm_VCVT_LE_FXS32_F32: "VCVT.LE.FXS32.F32", |
| 9691 arm_VCVT_FXS32_F32: "VCVT.FXS32.F32", |
| 9692 arm_VCVT_ZZ_FXS32_F32: "VCVT.ZZ.FXS32.F32", |
| 9693 arm_VCVT_EQ_FXS32_F64: "VCVT.EQ.FXS32.F64", |
| 9694 arm_VCVT_NE_FXS32_F64: "VCVT.NE.FXS32.F64", |
| 9695 arm_VCVT_CS_FXS32_F64: "VCVT.CS.FXS32.F64", |
| 9696 arm_VCVT_CC_FXS32_F64: "VCVT.CC.FXS32.F64", |
| 9697 arm_VCVT_MI_FXS32_F64: "VCVT.MI.FXS32.F64", |
| 9698 arm_VCVT_PL_FXS32_F64: "VCVT.PL.FXS32.F64", |
| 9699 arm_VCVT_VS_FXS32_F64: "VCVT.VS.FXS32.F64", |
| 9700 arm_VCVT_VC_FXS32_F64: "VCVT.VC.FXS32.F64", |
| 9701 arm_VCVT_HI_FXS32_F64: "VCVT.HI.FXS32.F64", |
| 9702 arm_VCVT_LS_FXS32_F64: "VCVT.LS.FXS32.F64", |
| 9703 arm_VCVT_GE_FXS32_F64: "VCVT.GE.FXS32.F64", |
| 9704 arm_VCVT_LT_FXS32_F64: "VCVT.LT.FXS32.F64", |
| 9705 arm_VCVT_GT_FXS32_F64: "VCVT.GT.FXS32.F64", |
| 9706 arm_VCVT_LE_FXS32_F64: "VCVT.LE.FXS32.F64", |
| 9707 arm_VCVT_FXS32_F64: "VCVT.FXS32.F64", |
| 9708 arm_VCVT_ZZ_FXS32_F64: "VCVT.ZZ.FXS32.F64", |
| 9709 arm_VCVT_EQ_FXU16_F32: "VCVT.EQ.FXU16.F32", |
| 9710 arm_VCVT_NE_FXU16_F32: "VCVT.NE.FXU16.F32", |
| 9711 arm_VCVT_CS_FXU16_F32: "VCVT.CS.FXU16.F32", |
| 9712 arm_VCVT_CC_FXU16_F32: "VCVT.CC.FXU16.F32", |
| 9713 arm_VCVT_MI_FXU16_F32: "VCVT.MI.FXU16.F32", |
| 9714 arm_VCVT_PL_FXU16_F32: "VCVT.PL.FXU16.F32", |
| 9715 arm_VCVT_VS_FXU16_F32: "VCVT.VS.FXU16.F32", |
| 9716 arm_VCVT_VC_FXU16_F32: "VCVT.VC.FXU16.F32", |
| 9717 arm_VCVT_HI_FXU16_F32: "VCVT.HI.FXU16.F32", |
| 9718 arm_VCVT_LS_FXU16_F32: "VCVT.LS.FXU16.F32", |
| 9719 arm_VCVT_GE_FXU16_F32: "VCVT.GE.FXU16.F32", |
| 9720 arm_VCVT_LT_FXU16_F32: "VCVT.LT.FXU16.F32", |
| 9721 arm_VCVT_GT_FXU16_F32: "VCVT.GT.FXU16.F32", |
| 9722 arm_VCVT_LE_FXU16_F32: "VCVT.LE.FXU16.F32", |
| 9723 arm_VCVT_FXU16_F32: "VCVT.FXU16.F32", |
| 9724 arm_VCVT_ZZ_FXU16_F32: "VCVT.ZZ.FXU16.F32", |
| 9725 arm_VCVT_EQ_FXU16_F64: "VCVT.EQ.FXU16.F64", |
| 9726 arm_VCVT_NE_FXU16_F64: "VCVT.NE.FXU16.F64", |
| 9727 arm_VCVT_CS_FXU16_F64: "VCVT.CS.FXU16.F64", |
| 9728 arm_VCVT_CC_FXU16_F64: "VCVT.CC.FXU16.F64", |
| 9729 arm_VCVT_MI_FXU16_F64: "VCVT.MI.FXU16.F64", |
| 9730 arm_VCVT_PL_FXU16_F64: "VCVT.PL.FXU16.F64", |
| 9731 arm_VCVT_VS_FXU16_F64: "VCVT.VS.FXU16.F64", |
| 9732 arm_VCVT_VC_FXU16_F64: "VCVT.VC.FXU16.F64", |
| 9733 arm_VCVT_HI_FXU16_F64: "VCVT.HI.FXU16.F64", |
| 9734 arm_VCVT_LS_FXU16_F64: "VCVT.LS.FXU16.F64", |
| 9735 arm_VCVT_GE_FXU16_F64: "VCVT.GE.FXU16.F64", |
| 9736 arm_VCVT_LT_FXU16_F64: "VCVT.LT.FXU16.F64", |
| 9737 arm_VCVT_GT_FXU16_F64: "VCVT.GT.FXU16.F64", |
| 9738 arm_VCVT_LE_FXU16_F64: "VCVT.LE.FXU16.F64", |
| 9739 arm_VCVT_FXU16_F64: "VCVT.FXU16.F64", |
| 9740 arm_VCVT_ZZ_FXU16_F64: "VCVT.ZZ.FXU16.F64", |
| 9741 arm_VCVT_EQ_FXU32_F32: "VCVT.EQ.FXU32.F32", |
| 9742 arm_VCVT_NE_FXU32_F32: "VCVT.NE.FXU32.F32", |
| 9743 arm_VCVT_CS_FXU32_F32: "VCVT.CS.FXU32.F32", |
| 9744 arm_VCVT_CC_FXU32_F32: "VCVT.CC.FXU32.F32", |
| 9745 arm_VCVT_MI_FXU32_F32: "VCVT.MI.FXU32.F32", |
| 9746 arm_VCVT_PL_FXU32_F32: "VCVT.PL.FXU32.F32", |
| 9747 arm_VCVT_VS_FXU32_F32: "VCVT.VS.FXU32.F32", |
| 9748 arm_VCVT_VC_FXU32_F32: "VCVT.VC.FXU32.F32", |
| 9749 arm_VCVT_HI_FXU32_F32: "VCVT.HI.FXU32.F32", |
| 9750 arm_VCVT_LS_FXU32_F32: "VCVT.LS.FXU32.F32", |
| 9751 arm_VCVT_GE_FXU32_F32: "VCVT.GE.FXU32.F32", |
| 9752 arm_VCVT_LT_FXU32_F32: "VCVT.LT.FXU32.F32", |
| 9753 arm_VCVT_GT_FXU32_F32: "VCVT.GT.FXU32.F32", |
| 9754 arm_VCVT_LE_FXU32_F32: "VCVT.LE.FXU32.F32", |
| 9755 arm_VCVT_FXU32_F32: "VCVT.FXU32.F32", |
| 9756 arm_VCVT_ZZ_FXU32_F32: "VCVT.ZZ.FXU32.F32", |
| 9757 arm_VCVT_EQ_FXU32_F64: "VCVT.EQ.FXU32.F64", |
| 9758 arm_VCVT_NE_FXU32_F64: "VCVT.NE.FXU32.F64", |
| 9759 arm_VCVT_CS_FXU32_F64: "VCVT.CS.FXU32.F64", |
| 9760 arm_VCVT_CC_FXU32_F64: "VCVT.CC.FXU32.F64", |
| 9761 arm_VCVT_MI_FXU32_F64: "VCVT.MI.FXU32.F64", |
| 9762 arm_VCVT_PL_FXU32_F64: "VCVT.PL.FXU32.F64", |
| 9763 arm_VCVT_VS_FXU32_F64: "VCVT.VS.FXU32.F64", |
| 9764 arm_VCVT_VC_FXU32_F64: "VCVT.VC.FXU32.F64", |
| 9765 arm_VCVT_HI_FXU32_F64: "VCVT.HI.FXU32.F64", |
| 9766 arm_VCVT_LS_FXU32_F64: "VCVT.LS.FXU32.F64", |
| 9767 arm_VCVT_GE_FXU32_F64: "VCVT.GE.FXU32.F64", |
| 9768 arm_VCVT_LT_FXU32_F64: "VCVT.LT.FXU32.F64", |
| 9769 arm_VCVT_GT_FXU32_F64: "VCVT.GT.FXU32.F64", |
| 9770 arm_VCVT_LE_FXU32_F64: "VCVT.LE.FXU32.F64", |
| 9771 arm_VCVT_FXU32_F64: "VCVT.FXU32.F64", |
| 9772 arm_VCVT_ZZ_FXU32_F64: "VCVT.ZZ.FXU32.F64", |
| 9773 arm_VCVTB_EQ_F32_F16: "VCVTB.EQ.F32.F16", |
| 9774 arm_VCVTB_NE_F32_F16: "VCVTB.NE.F32.F16", |
| 9775 arm_VCVTB_CS_F32_F16: "VCVTB.CS.F32.F16", |
| 9776 arm_VCVTB_CC_F32_F16: "VCVTB.CC.F32.F16", |
| 9777 arm_VCVTB_MI_F32_F16: "VCVTB.MI.F32.F16", |
| 9778 arm_VCVTB_PL_F32_F16: "VCVTB.PL.F32.F16", |
| 9779 arm_VCVTB_VS_F32_F16: "VCVTB.VS.F32.F16", |
| 9780 arm_VCVTB_VC_F32_F16: "VCVTB.VC.F32.F16", |
| 9781 arm_VCVTB_HI_F32_F16: "VCVTB.HI.F32.F16", |
| 9782 arm_VCVTB_LS_F32_F16: "VCVTB.LS.F32.F16", |
| 9783 arm_VCVTB_GE_F32_F16: "VCVTB.GE.F32.F16", |
| 9784 arm_VCVTB_LT_F32_F16: "VCVTB.LT.F32.F16", |
| 9785 arm_VCVTB_GT_F32_F16: "VCVTB.GT.F32.F16", |
| 9786 arm_VCVTB_LE_F32_F16: "VCVTB.LE.F32.F16", |
| 9787 arm_VCVTB_F32_F16: "VCVTB.F32.F16", |
| 9788 arm_VCVTB_ZZ_F32_F16: "VCVTB.ZZ.F32.F16", |
| 9789 arm_VCVTB_EQ_F16_F32: "VCVTB.EQ.F16.F32", |
| 9790 arm_VCVTB_NE_F16_F32: "VCVTB.NE.F16.F32", |
| 9791 arm_VCVTB_CS_F16_F32: "VCVTB.CS.F16.F32", |
| 9792 arm_VCVTB_CC_F16_F32: "VCVTB.CC.F16.F32", |
| 9793 arm_VCVTB_MI_F16_F32: "VCVTB.MI.F16.F32", |
| 9794 arm_VCVTB_PL_F16_F32: "VCVTB.PL.F16.F32", |
| 9795 arm_VCVTB_VS_F16_F32: "VCVTB.VS.F16.F32", |
| 9796 arm_VCVTB_VC_F16_F32: "VCVTB.VC.F16.F32", |
| 9797 arm_VCVTB_HI_F16_F32: "VCVTB.HI.F16.F32", |
| 9798 arm_VCVTB_LS_F16_F32: "VCVTB.LS.F16.F32", |
| 9799 arm_VCVTB_GE_F16_F32: "VCVTB.GE.F16.F32", |
| 9800 arm_VCVTB_LT_F16_F32: "VCVTB.LT.F16.F32", |
| 9801 arm_VCVTB_GT_F16_F32: "VCVTB.GT.F16.F32", |
| 9802 arm_VCVTB_LE_F16_F32: "VCVTB.LE.F16.F32", |
| 9803 arm_VCVTB_F16_F32: "VCVTB.F16.F32", |
| 9804 arm_VCVTB_ZZ_F16_F32: "VCVTB.ZZ.F16.F32", |
| 9805 arm_VCVTT_EQ_F32_F16: "VCVTT.EQ.F32.F16", |
| 9806 arm_VCVTT_NE_F32_F16: "VCVTT.NE.F32.F16", |
| 9807 arm_VCVTT_CS_F32_F16: "VCVTT.CS.F32.F16", |
| 9808 arm_VCVTT_CC_F32_F16: "VCVTT.CC.F32.F16", |
| 9809 arm_VCVTT_MI_F32_F16: "VCVTT.MI.F32.F16", |
| 9810 arm_VCVTT_PL_F32_F16: "VCVTT.PL.F32.F16", |
| 9811 arm_VCVTT_VS_F32_F16: "VCVTT.VS.F32.F16", |
| 9812 arm_VCVTT_VC_F32_F16: "VCVTT.VC.F32.F16", |
| 9813 arm_VCVTT_HI_F32_F16: "VCVTT.HI.F32.F16", |
| 9814 arm_VCVTT_LS_F32_F16: "VCVTT.LS.F32.F16", |
| 9815 arm_VCVTT_GE_F32_F16: "VCVTT.GE.F32.F16", |
| 9816 arm_VCVTT_LT_F32_F16: "VCVTT.LT.F32.F16", |
| 9817 arm_VCVTT_GT_F32_F16: "VCVTT.GT.F32.F16", |
| 9818 arm_VCVTT_LE_F32_F16: "VCVTT.LE.F32.F16", |
| 9819 arm_VCVTT_F32_F16: "VCVTT.F32.F16", |
| 9820 arm_VCVTT_ZZ_F32_F16: "VCVTT.ZZ.F32.F16", |
| 9821 arm_VCVTT_EQ_F16_F32: "VCVTT.EQ.F16.F32", |
| 9822 arm_VCVTT_NE_F16_F32: "VCVTT.NE.F16.F32", |
| 9823 arm_VCVTT_CS_F16_F32: "VCVTT.CS.F16.F32", |
| 9824 arm_VCVTT_CC_F16_F32: "VCVTT.CC.F16.F32", |
| 9825 arm_VCVTT_MI_F16_F32: "VCVTT.MI.F16.F32", |
| 9826 arm_VCVTT_PL_F16_F32: "VCVTT.PL.F16.F32", |
| 9827 arm_VCVTT_VS_F16_F32: "VCVTT.VS.F16.F32", |
| 9828 arm_VCVTT_VC_F16_F32: "VCVTT.VC.F16.F32", |
| 9829 arm_VCVTT_HI_F16_F32: "VCVTT.HI.F16.F32", |
| 9830 arm_VCVTT_LS_F16_F32: "VCVTT.LS.F16.F32", |
| 9831 arm_VCVTT_GE_F16_F32: "VCVTT.GE.F16.F32", |
| 9832 arm_VCVTT_LT_F16_F32: "VCVTT.LT.F16.F32", |
| 9833 arm_VCVTT_GT_F16_F32: "VCVTT.GT.F16.F32", |
| 9834 arm_VCVTT_LE_F16_F32: "VCVTT.LE.F16.F32", |
| 9835 arm_VCVTT_F16_F32: "VCVTT.F16.F32", |
| 9836 arm_VCVTT_ZZ_F16_F32: "VCVTT.ZZ.F16.F32", |
| 9837 arm_VCVTR_EQ_U32_F32: "VCVTR.EQ.U32.F32", |
| 9838 arm_VCVTR_NE_U32_F32: "VCVTR.NE.U32.F32", |
| 9839 arm_VCVTR_CS_U32_F32: "VCVTR.CS.U32.F32", |
| 9840 arm_VCVTR_CC_U32_F32: "VCVTR.CC.U32.F32", |
| 9841 arm_VCVTR_MI_U32_F32: "VCVTR.MI.U32.F32", |
| 9842 arm_VCVTR_PL_U32_F32: "VCVTR.PL.U32.F32", |
| 9843 arm_VCVTR_VS_U32_F32: "VCVTR.VS.U32.F32", |
| 9844 arm_VCVTR_VC_U32_F32: "VCVTR.VC.U32.F32", |
| 9845 arm_VCVTR_HI_U32_F32: "VCVTR.HI.U32.F32", |
| 9846 arm_VCVTR_LS_U32_F32: "VCVTR.LS.U32.F32", |
| 9847 arm_VCVTR_GE_U32_F32: "VCVTR.GE.U32.F32", |
| 9848 arm_VCVTR_LT_U32_F32: "VCVTR.LT.U32.F32", |
| 9849 arm_VCVTR_GT_U32_F32: "VCVTR.GT.U32.F32", |
| 9850 arm_VCVTR_LE_U32_F32: "VCVTR.LE.U32.F32", |
| 9851 arm_VCVTR_U32_F32: "VCVTR.U32.F32", |
| 9852 arm_VCVTR_ZZ_U32_F32: "VCVTR.ZZ.U32.F32", |
| 9853 arm_VCVTR_EQ_U32_F64: "VCVTR.EQ.U32.F64", |
| 9854 arm_VCVTR_NE_U32_F64: "VCVTR.NE.U32.F64", |
| 9855 arm_VCVTR_CS_U32_F64: "VCVTR.CS.U32.F64", |
| 9856 arm_VCVTR_CC_U32_F64: "VCVTR.CC.U32.F64", |
| 9857 arm_VCVTR_MI_U32_F64: "VCVTR.MI.U32.F64", |
| 9858 arm_VCVTR_PL_U32_F64: "VCVTR.PL.U32.F64", |
| 9859 arm_VCVTR_VS_U32_F64: "VCVTR.VS.U32.F64", |
| 9860 arm_VCVTR_VC_U32_F64: "VCVTR.VC.U32.F64", |
| 9861 arm_VCVTR_HI_U32_F64: "VCVTR.HI.U32.F64", |
| 9862 arm_VCVTR_LS_U32_F64: "VCVTR.LS.U32.F64", |
| 9863 arm_VCVTR_GE_U32_F64: "VCVTR.GE.U32.F64", |
| 9864 arm_VCVTR_LT_U32_F64: "VCVTR.LT.U32.F64", |
| 9865 arm_VCVTR_GT_U32_F64: "VCVTR.GT.U32.F64", |
| 9866 arm_VCVTR_LE_U32_F64: "VCVTR.LE.U32.F64", |
| 9867 arm_VCVTR_U32_F64: "VCVTR.U32.F64", |
| 9868 arm_VCVTR_ZZ_U32_F64: "VCVTR.ZZ.U32.F64", |
| 9869 arm_VCVTR_EQ_S32_F32: "VCVTR.EQ.S32.F32", |
| 9870 arm_VCVTR_NE_S32_F32: "VCVTR.NE.S32.F32", |
| 9871 arm_VCVTR_CS_S32_F32: "VCVTR.CS.S32.F32", |
| 9872 arm_VCVTR_CC_S32_F32: "VCVTR.CC.S32.F32", |
| 9873 arm_VCVTR_MI_S32_F32: "VCVTR.MI.S32.F32", |
| 9874 arm_VCVTR_PL_S32_F32: "VCVTR.PL.S32.F32", |
| 9875 arm_VCVTR_VS_S32_F32: "VCVTR.VS.S32.F32", |
| 9876 arm_VCVTR_VC_S32_F32: "VCVTR.VC.S32.F32", |
| 9877 arm_VCVTR_HI_S32_F32: "VCVTR.HI.S32.F32", |
| 9878 arm_VCVTR_LS_S32_F32: "VCVTR.LS.S32.F32", |
| 9879 arm_VCVTR_GE_S32_F32: "VCVTR.GE.S32.F32", |
| 9880 arm_VCVTR_LT_S32_F32: "VCVTR.LT.S32.F32", |
| 9881 arm_VCVTR_GT_S32_F32: "VCVTR.GT.S32.F32", |
| 9882 arm_VCVTR_LE_S32_F32: "VCVTR.LE.S32.F32", |
| 9883 arm_VCVTR_S32_F32: "VCVTR.S32.F32", |
| 9884 arm_VCVTR_ZZ_S32_F32: "VCVTR.ZZ.S32.F32", |
| 9885 arm_VCVTR_EQ_S32_F64: "VCVTR.EQ.S32.F64", |
| 9886 arm_VCVTR_NE_S32_F64: "VCVTR.NE.S32.F64", |
| 9887 arm_VCVTR_CS_S32_F64: "VCVTR.CS.S32.F64", |
| 9888 arm_VCVTR_CC_S32_F64: "VCVTR.CC.S32.F64", |
| 9889 arm_VCVTR_MI_S32_F64: "VCVTR.MI.S32.F64", |
| 9890 arm_VCVTR_PL_S32_F64: "VCVTR.PL.S32.F64", |
| 9891 arm_VCVTR_VS_S32_F64: "VCVTR.VS.S32.F64", |
| 9892 arm_VCVTR_VC_S32_F64: "VCVTR.VC.S32.F64", |
| 9893 arm_VCVTR_HI_S32_F64: "VCVTR.HI.S32.F64", |
| 9894 arm_VCVTR_LS_S32_F64: "VCVTR.LS.S32.F64", |
| 9895 arm_VCVTR_GE_S32_F64: "VCVTR.GE.S32.F64", |
| 9896 arm_VCVTR_LT_S32_F64: "VCVTR.LT.S32.F64", |
| 9897 arm_VCVTR_GT_S32_F64: "VCVTR.GT.S32.F64", |
| 9898 arm_VCVTR_LE_S32_F64: "VCVTR.LE.S32.F64", |
| 9899 arm_VCVTR_S32_F64: "VCVTR.S32.F64", |
| 9900 arm_VCVTR_ZZ_S32_F64: "VCVTR.ZZ.S32.F64", |
| 9901 arm_VCVT_EQ_U32_F32: "VCVT.EQ.U32.F32", |
| 9902 arm_VCVT_NE_U32_F32: "VCVT.NE.U32.F32", |
| 9903 arm_VCVT_CS_U32_F32: "VCVT.CS.U32.F32", |
| 9904 arm_VCVT_CC_U32_F32: "VCVT.CC.U32.F32", |
| 9905 arm_VCVT_MI_U32_F32: "VCVT.MI.U32.F32", |
| 9906 arm_VCVT_PL_U32_F32: "VCVT.PL.U32.F32", |
| 9907 arm_VCVT_VS_U32_F32: "VCVT.VS.U32.F32", |
| 9908 arm_VCVT_VC_U32_F32: "VCVT.VC.U32.F32", |
| 9909 arm_VCVT_HI_U32_F32: "VCVT.HI.U32.F32", |
| 9910 arm_VCVT_LS_U32_F32: "VCVT.LS.U32.F32", |
| 9911 arm_VCVT_GE_U32_F32: "VCVT.GE.U32.F32", |
| 9912 arm_VCVT_LT_U32_F32: "VCVT.LT.U32.F32", |
| 9913 arm_VCVT_GT_U32_F32: "VCVT.GT.U32.F32", |
| 9914 arm_VCVT_LE_U32_F32: "VCVT.LE.U32.F32", |
| 9915 arm_VCVT_U32_F32: "VCVT.U32.F32", |
| 9916 arm_VCVT_ZZ_U32_F32: "VCVT.ZZ.U32.F32", |
| 9917 arm_VCVT_EQ_U32_F64: "VCVT.EQ.U32.F64", |
| 9918 arm_VCVT_NE_U32_F64: "VCVT.NE.U32.F64", |
| 9919 arm_VCVT_CS_U32_F64: "VCVT.CS.U32.F64", |
| 9920 arm_VCVT_CC_U32_F64: "VCVT.CC.U32.F64", |
| 9921 arm_VCVT_MI_U32_F64: "VCVT.MI.U32.F64", |
| 9922 arm_VCVT_PL_U32_F64: "VCVT.PL.U32.F64", |
| 9923 arm_VCVT_VS_U32_F64: "VCVT.VS.U32.F64", |
| 9924 arm_VCVT_VC_U32_F64: "VCVT.VC.U32.F64", |
| 9925 arm_VCVT_HI_U32_F64: "VCVT.HI.U32.F64", |
| 9926 arm_VCVT_LS_U32_F64: "VCVT.LS.U32.F64", |
| 9927 arm_VCVT_GE_U32_F64: "VCVT.GE.U32.F64", |
| 9928 arm_VCVT_LT_U32_F64: "VCVT.LT.U32.F64", |
| 9929 arm_VCVT_GT_U32_F64: "VCVT.GT.U32.F64", |
| 9930 arm_VCVT_LE_U32_F64: "VCVT.LE.U32.F64", |
| 9931 arm_VCVT_U32_F64: "VCVT.U32.F64", |
| 9932 arm_VCVT_ZZ_U32_F64: "VCVT.ZZ.U32.F64", |
| 9933 arm_VCVT_EQ_S32_F32: "VCVT.EQ.S32.F32", |
| 9934 arm_VCVT_NE_S32_F32: "VCVT.NE.S32.F32", |
| 9935 arm_VCVT_CS_S32_F32: "VCVT.CS.S32.F32", |
| 9936 arm_VCVT_CC_S32_F32: "VCVT.CC.S32.F32", |
| 9937 arm_VCVT_MI_S32_F32: "VCVT.MI.S32.F32", |
| 9938 arm_VCVT_PL_S32_F32: "VCVT.PL.S32.F32", |
| 9939 arm_VCVT_VS_S32_F32: "VCVT.VS.S32.F32", |
| 9940 arm_VCVT_VC_S32_F32: "VCVT.VC.S32.F32", |
| 9941 arm_VCVT_HI_S32_F32: "VCVT.HI.S32.F32", |
| 9942 arm_VCVT_LS_S32_F32: "VCVT.LS.S32.F32", |
| 9943 arm_VCVT_GE_S32_F32: "VCVT.GE.S32.F32", |
| 9944 arm_VCVT_LT_S32_F32: "VCVT.LT.S32.F32", |
| 9945 arm_VCVT_GT_S32_F32: "VCVT.GT.S32.F32", |
| 9946 arm_VCVT_LE_S32_F32: "VCVT.LE.S32.F32", |
| 9947 arm_VCVT_S32_F32: "VCVT.S32.F32", |
| 9948 arm_VCVT_ZZ_S32_F32: "VCVT.ZZ.S32.F32", |
| 9949 arm_VCVT_EQ_S32_F64: "VCVT.EQ.S32.F64", |
| 9950 arm_VCVT_NE_S32_F64: "VCVT.NE.S32.F64", |
| 9951 arm_VCVT_CS_S32_F64: "VCVT.CS.S32.F64", |
| 9952 arm_VCVT_CC_S32_F64: "VCVT.CC.S32.F64", |
| 9953 arm_VCVT_MI_S32_F64: "VCVT.MI.S32.F64", |
| 9954 arm_VCVT_PL_S32_F64: "VCVT.PL.S32.F64", |
| 9955 arm_VCVT_VS_S32_F64: "VCVT.VS.S32.F64", |
| 9956 arm_VCVT_VC_S32_F64: "VCVT.VC.S32.F64", |
| 9957 arm_VCVT_HI_S32_F64: "VCVT.HI.S32.F64", |
| 9958 arm_VCVT_LS_S32_F64: "VCVT.LS.S32.F64", |
| 9959 arm_VCVT_GE_S32_F64: "VCVT.GE.S32.F64", |
| 9960 arm_VCVT_LT_S32_F64: "VCVT.LT.S32.F64", |
| 9961 arm_VCVT_GT_S32_F64: "VCVT.GT.S32.F64", |
| 9962 arm_VCVT_LE_S32_F64: "VCVT.LE.S32.F64", |
| 9963 arm_VCVT_S32_F64: "VCVT.S32.F64", |
| 9964 arm_VCVT_ZZ_S32_F64: "VCVT.ZZ.S32.F64", |
| 9965 arm_VDIV_EQ_F32: "VDIV.EQ.F32", |
| 9966 arm_VDIV_NE_F32: "VDIV.NE.F32", |
| 9967 arm_VDIV_CS_F32: "VDIV.CS.F32", |
| 9968 arm_VDIV_CC_F32: "VDIV.CC.F32", |
| 9969 arm_VDIV_MI_F32: "VDIV.MI.F32", |
| 9970 arm_VDIV_PL_F32: "VDIV.PL.F32", |
| 9971 arm_VDIV_VS_F32: "VDIV.VS.F32", |
| 9972 arm_VDIV_VC_F32: "VDIV.VC.F32", |
| 9973 arm_VDIV_HI_F32: "VDIV.HI.F32", |
| 9974 arm_VDIV_LS_F32: "VDIV.LS.F32", |
| 9975 arm_VDIV_GE_F32: "VDIV.GE.F32", |
| 9976 arm_VDIV_LT_F32: "VDIV.LT.F32", |
| 9977 arm_VDIV_GT_F32: "VDIV.GT.F32", |
| 9978 arm_VDIV_LE_F32: "VDIV.LE.F32", |
| 9979 arm_VDIV_F32: "VDIV.F32", |
| 9980 arm_VDIV_ZZ_F32: "VDIV.ZZ.F32", |
| 9981 arm_VDIV_EQ_F64: "VDIV.EQ.F64", |
| 9982 arm_VDIV_NE_F64: "VDIV.NE.F64", |
| 9983 arm_VDIV_CS_F64: "VDIV.CS.F64", |
| 9984 arm_VDIV_CC_F64: "VDIV.CC.F64", |
| 9985 arm_VDIV_MI_F64: "VDIV.MI.F64", |
| 9986 arm_VDIV_PL_F64: "VDIV.PL.F64", |
| 9987 arm_VDIV_VS_F64: "VDIV.VS.F64", |
| 9988 arm_VDIV_VC_F64: "VDIV.VC.F64", |
| 9989 arm_VDIV_HI_F64: "VDIV.HI.F64", |
| 9990 arm_VDIV_LS_F64: "VDIV.LS.F64", |
| 9991 arm_VDIV_GE_F64: "VDIV.GE.F64", |
| 9992 arm_VDIV_LT_F64: "VDIV.LT.F64", |
| 9993 arm_VDIV_GT_F64: "VDIV.GT.F64", |
| 9994 arm_VDIV_LE_F64: "VDIV.LE.F64", |
| 9995 arm_VDIV_F64: "VDIV.F64", |
| 9996 arm_VDIV_ZZ_F64: "VDIV.ZZ.F64", |
| 9997 arm_VLDR_EQ: "VLDR.EQ", |
| 9998 arm_VLDR_NE: "VLDR.NE", |
| 9999 arm_VLDR_CS: "VLDR.CS", |
| 10000 arm_VLDR_CC: "VLDR.CC", |
| 10001 arm_VLDR_MI: "VLDR.MI", |
| 10002 arm_VLDR_PL: "VLDR.PL", |
| 10003 arm_VLDR_VS: "VLDR.VS", |
| 10004 arm_VLDR_VC: "VLDR.VC", |
| 10005 arm_VLDR_HI: "VLDR.HI", |
| 10006 arm_VLDR_LS: "VLDR.LS", |
| 10007 arm_VLDR_GE: "VLDR.GE", |
| 10008 arm_VLDR_LT: "VLDR.LT", |
| 10009 arm_VLDR_GT: "VLDR.GT", |
| 10010 arm_VLDR_LE: "VLDR.LE", |
| 10011 arm_VLDR: "VLDR", |
| 10012 arm_VLDR_ZZ: "VLDR.ZZ", |
| 10013 arm_VMLA_EQ_F32: "VMLA.EQ.F32", |
| 10014 arm_VMLA_NE_F32: "VMLA.NE.F32", |
| 10015 arm_VMLA_CS_F32: "VMLA.CS.F32", |
| 10016 arm_VMLA_CC_F32: "VMLA.CC.F32", |
| 10017 arm_VMLA_MI_F32: "VMLA.MI.F32", |
| 10018 arm_VMLA_PL_F32: "VMLA.PL.F32", |
| 10019 arm_VMLA_VS_F32: "VMLA.VS.F32", |
| 10020 arm_VMLA_VC_F32: "VMLA.VC.F32", |
| 10021 arm_VMLA_HI_F32: "VMLA.HI.F32", |
| 10022 arm_VMLA_LS_F32: "VMLA.LS.F32", |
| 10023 arm_VMLA_GE_F32: "VMLA.GE.F32", |
| 10024 arm_VMLA_LT_F32: "VMLA.LT.F32", |
| 10025 arm_VMLA_GT_F32: "VMLA.GT.F32", |
| 10026 arm_VMLA_LE_F32: "VMLA.LE.F32", |
| 10027 arm_VMLA_F32: "VMLA.F32", |
| 10028 arm_VMLA_ZZ_F32: "VMLA.ZZ.F32", |
| 10029 arm_VMLA_EQ_F64: "VMLA.EQ.F64", |
| 10030 arm_VMLA_NE_F64: "VMLA.NE.F64", |
| 10031 arm_VMLA_CS_F64: "VMLA.CS.F64", |
| 10032 arm_VMLA_CC_F64: "VMLA.CC.F64", |
| 10033 arm_VMLA_MI_F64: "VMLA.MI.F64", |
| 10034 arm_VMLA_PL_F64: "VMLA.PL.F64", |
| 10035 arm_VMLA_VS_F64: "VMLA.VS.F64", |
| 10036 arm_VMLA_VC_F64: "VMLA.VC.F64", |
| 10037 arm_VMLA_HI_F64: "VMLA.HI.F64", |
| 10038 arm_VMLA_LS_F64: "VMLA.LS.F64", |
| 10039 arm_VMLA_GE_F64: "VMLA.GE.F64", |
| 10040 arm_VMLA_LT_F64: "VMLA.LT.F64", |
| 10041 arm_VMLA_GT_F64: "VMLA.GT.F64", |
| 10042 arm_VMLA_LE_F64: "VMLA.LE.F64", |
| 10043 arm_VMLA_F64: "VMLA.F64", |
| 10044 arm_VMLA_ZZ_F64: "VMLA.ZZ.F64", |
| 10045 arm_VMLS_EQ_F32: "VMLS.EQ.F32", |
| 10046 arm_VMLS_NE_F32: "VMLS.NE.F32", |
| 10047 arm_VMLS_CS_F32: "VMLS.CS.F32", |
| 10048 arm_VMLS_CC_F32: "VMLS.CC.F32", |
| 10049 arm_VMLS_MI_F32: "VMLS.MI.F32", |
| 10050 arm_VMLS_PL_F32: "VMLS.PL.F32", |
| 10051 arm_VMLS_VS_F32: "VMLS.VS.F32", |
| 10052 arm_VMLS_VC_F32: "VMLS.VC.F32", |
| 10053 arm_VMLS_HI_F32: "VMLS.HI.F32", |
| 10054 arm_VMLS_LS_F32: "VMLS.LS.F32", |
| 10055 arm_VMLS_GE_F32: "VMLS.GE.F32", |
| 10056 arm_VMLS_LT_F32: "VMLS.LT.F32", |
| 10057 arm_VMLS_GT_F32: "VMLS.GT.F32", |
| 10058 arm_VMLS_LE_F32: "VMLS.LE.F32", |
| 10059 arm_VMLS_F32: "VMLS.F32", |
| 10060 arm_VMLS_ZZ_F32: "VMLS.ZZ.F32", |
| 10061 arm_VMLS_EQ_F64: "VMLS.EQ.F64", |
| 10062 arm_VMLS_NE_F64: "VMLS.NE.F64", |
| 10063 arm_VMLS_CS_F64: "VMLS.CS.F64", |
| 10064 arm_VMLS_CC_F64: "VMLS.CC.F64", |
| 10065 arm_VMLS_MI_F64: "VMLS.MI.F64", |
| 10066 arm_VMLS_PL_F64: "VMLS.PL.F64", |
| 10067 arm_VMLS_VS_F64: "VMLS.VS.F64", |
| 10068 arm_VMLS_VC_F64: "VMLS.VC.F64", |
| 10069 arm_VMLS_HI_F64: "VMLS.HI.F64", |
| 10070 arm_VMLS_LS_F64: "VMLS.LS.F64", |
| 10071 arm_VMLS_GE_F64: "VMLS.GE.F64", |
| 10072 arm_VMLS_LT_F64: "VMLS.LT.F64", |
| 10073 arm_VMLS_GT_F64: "VMLS.GT.F64", |
| 10074 arm_VMLS_LE_F64: "VMLS.LE.F64", |
| 10075 arm_VMLS_F64: "VMLS.F64", |
| 10076 arm_VMLS_ZZ_F64: "VMLS.ZZ.F64", |
| 10077 arm_VMOV_EQ: "VMOV.EQ", |
| 10078 arm_VMOV_NE: "VMOV.NE", |
| 10079 arm_VMOV_CS: "VMOV.CS", |
| 10080 arm_VMOV_CC: "VMOV.CC", |
| 10081 arm_VMOV_MI: "VMOV.MI", |
| 10082 arm_VMOV_PL: "VMOV.PL", |
| 10083 arm_VMOV_VS: "VMOV.VS", |
| 10084 arm_VMOV_VC: "VMOV.VC", |
| 10085 arm_VMOV_HI: "VMOV.HI", |
| 10086 arm_VMOV_LS: "VMOV.LS", |
| 10087 arm_VMOV_GE: "VMOV.GE", |
| 10088 arm_VMOV_LT: "VMOV.LT", |
| 10089 arm_VMOV_GT: "VMOV.GT", |
| 10090 arm_VMOV_LE: "VMOV.LE", |
| 10091 arm_VMOV: "VMOV", |
| 10092 arm_VMOV_ZZ: "VMOV.ZZ", |
| 10093 arm_VMOV_EQ_32: "VMOV.EQ.32", |
| 10094 arm_VMOV_NE_32: "VMOV.NE.32", |
| 10095 arm_VMOV_CS_32: "VMOV.CS.32", |
| 10096 arm_VMOV_CC_32: "VMOV.CC.32", |
| 10097 arm_VMOV_MI_32: "VMOV.MI.32", |
| 10098 arm_VMOV_PL_32: "VMOV.PL.32", |
| 10099 arm_VMOV_VS_32: "VMOV.VS.32", |
| 10100 arm_VMOV_VC_32: "VMOV.VC.32", |
| 10101 arm_VMOV_HI_32: "VMOV.HI.32", |
| 10102 arm_VMOV_LS_32: "VMOV.LS.32", |
| 10103 arm_VMOV_GE_32: "VMOV.GE.32", |
| 10104 arm_VMOV_LT_32: "VMOV.LT.32", |
| 10105 arm_VMOV_GT_32: "VMOV.GT.32", |
| 10106 arm_VMOV_LE_32: "VMOV.LE.32", |
| 10107 arm_VMOV_32: "VMOV.32", |
| 10108 arm_VMOV_ZZ_32: "VMOV.ZZ.32", |
| 10109 arm_VMOV_EQ_F32: "VMOV.EQ.F32", |
| 10110 arm_VMOV_NE_F32: "VMOV.NE.F32", |
| 10111 arm_VMOV_CS_F32: "VMOV.CS.F32", |
| 10112 arm_VMOV_CC_F32: "VMOV.CC.F32", |
| 10113 arm_VMOV_MI_F32: "VMOV.MI.F32", |
| 10114 arm_VMOV_PL_F32: "VMOV.PL.F32", |
| 10115 arm_VMOV_VS_F32: "VMOV.VS.F32", |
| 10116 arm_VMOV_VC_F32: "VMOV.VC.F32", |
| 10117 arm_VMOV_HI_F32: "VMOV.HI.F32", |
| 10118 arm_VMOV_LS_F32: "VMOV.LS.F32", |
| 10119 arm_VMOV_GE_F32: "VMOV.GE.F32", |
| 10120 arm_VMOV_LT_F32: "VMOV.LT.F32", |
| 10121 arm_VMOV_GT_F32: "VMOV.GT.F32", |
| 10122 arm_VMOV_LE_F32: "VMOV.LE.F32", |
| 10123 arm_VMOV_F32: "VMOV.F32", |
| 10124 arm_VMOV_ZZ_F32: "VMOV.ZZ.F32", |
| 10125 arm_VMOV_EQ_F64: "VMOV.EQ.F64", |
| 10126 arm_VMOV_NE_F64: "VMOV.NE.F64", |
| 10127 arm_VMOV_CS_F64: "VMOV.CS.F64", |
| 10128 arm_VMOV_CC_F64: "VMOV.CC.F64", |
| 10129 arm_VMOV_MI_F64: "VMOV.MI.F64", |
| 10130 arm_VMOV_PL_F64: "VMOV.PL.F64", |
| 10131 arm_VMOV_VS_F64: "VMOV.VS.F64", |
| 10132 arm_VMOV_VC_F64: "VMOV.VC.F64", |
| 10133 arm_VMOV_HI_F64: "VMOV.HI.F64", |
| 10134 arm_VMOV_LS_F64: "VMOV.LS.F64", |
| 10135 arm_VMOV_GE_F64: "VMOV.GE.F64", |
| 10136 arm_VMOV_LT_F64: "VMOV.LT.F64", |
| 10137 arm_VMOV_GT_F64: "VMOV.GT.F64", |
| 10138 arm_VMOV_LE_F64: "VMOV.LE.F64", |
| 10139 arm_VMOV_F64: "VMOV.F64", |
| 10140 arm_VMOV_ZZ_F64: "VMOV.ZZ.F64", |
| 10141 arm_VMRS_EQ: "VMRS.EQ", |
| 10142 arm_VMRS_NE: "VMRS.NE", |
| 10143 arm_VMRS_CS: "VMRS.CS", |
| 10144 arm_VMRS_CC: "VMRS.CC", |
| 10145 arm_VMRS_MI: "VMRS.MI", |
| 10146 arm_VMRS_PL: "VMRS.PL", |
| 10147 arm_VMRS_VS: "VMRS.VS", |
| 10148 arm_VMRS_VC: "VMRS.VC", |
| 10149 arm_VMRS_HI: "VMRS.HI", |
| 10150 arm_VMRS_LS: "VMRS.LS", |
| 10151 arm_VMRS_GE: "VMRS.GE", |
| 10152 arm_VMRS_LT: "VMRS.LT", |
| 10153 arm_VMRS_GT: "VMRS.GT", |
| 10154 arm_VMRS_LE: "VMRS.LE", |
| 10155 arm_VMRS: "VMRS", |
| 10156 arm_VMRS_ZZ: "VMRS.ZZ", |
| 10157 arm_VMSR_EQ: "VMSR.EQ", |
| 10158 arm_VMSR_NE: "VMSR.NE", |
| 10159 arm_VMSR_CS: "VMSR.CS", |
| 10160 arm_VMSR_CC: "VMSR.CC", |
| 10161 arm_VMSR_MI: "VMSR.MI", |
| 10162 arm_VMSR_PL: "VMSR.PL", |
| 10163 arm_VMSR_VS: "VMSR.VS", |
| 10164 arm_VMSR_VC: "VMSR.VC", |
| 10165 arm_VMSR_HI: "VMSR.HI", |
| 10166 arm_VMSR_LS: "VMSR.LS", |
| 10167 arm_VMSR_GE: "VMSR.GE", |
| 10168 arm_VMSR_LT: "VMSR.LT", |
| 10169 arm_VMSR_GT: "VMSR.GT", |
| 10170 arm_VMSR_LE: "VMSR.LE", |
| 10171 arm_VMSR: "VMSR", |
| 10172 arm_VMSR_ZZ: "VMSR.ZZ", |
| 10173 arm_VMUL_EQ_F32: "VMUL.EQ.F32", |
| 10174 arm_VMUL_NE_F32: "VMUL.NE.F32", |
| 10175 arm_VMUL_CS_F32: "VMUL.CS.F32", |
| 10176 arm_VMUL_CC_F32: "VMUL.CC.F32", |
| 10177 arm_VMUL_MI_F32: "VMUL.MI.F32", |
| 10178 arm_VMUL_PL_F32: "VMUL.PL.F32", |
| 10179 arm_VMUL_VS_F32: "VMUL.VS.F32", |
| 10180 arm_VMUL_VC_F32: "VMUL.VC.F32", |
| 10181 arm_VMUL_HI_F32: "VMUL.HI.F32", |
| 10182 arm_VMUL_LS_F32: "VMUL.LS.F32", |
| 10183 arm_VMUL_GE_F32: "VMUL.GE.F32", |
| 10184 arm_VMUL_LT_F32: "VMUL.LT.F32", |
| 10185 arm_VMUL_GT_F32: "VMUL.GT.F32", |
| 10186 arm_VMUL_LE_F32: "VMUL.LE.F32", |
| 10187 arm_VMUL_F32: "VMUL.F32", |
| 10188 arm_VMUL_ZZ_F32: "VMUL.ZZ.F32", |
| 10189 arm_VMUL_EQ_F64: "VMUL.EQ.F64", |
| 10190 arm_VMUL_NE_F64: "VMUL.NE.F64", |
| 10191 arm_VMUL_CS_F64: "VMUL.CS.F64", |
| 10192 arm_VMUL_CC_F64: "VMUL.CC.F64", |
| 10193 arm_VMUL_MI_F64: "VMUL.MI.F64", |
| 10194 arm_VMUL_PL_F64: "VMUL.PL.F64", |
| 10195 arm_VMUL_VS_F64: "VMUL.VS.F64", |
| 10196 arm_VMUL_VC_F64: "VMUL.VC.F64", |
| 10197 arm_VMUL_HI_F64: "VMUL.HI.F64", |
| 10198 arm_VMUL_LS_F64: "VMUL.LS.F64", |
| 10199 arm_VMUL_GE_F64: "VMUL.GE.F64", |
| 10200 arm_VMUL_LT_F64: "VMUL.LT.F64", |
| 10201 arm_VMUL_GT_F64: "VMUL.GT.F64", |
| 10202 arm_VMUL_LE_F64: "VMUL.LE.F64", |
| 10203 arm_VMUL_F64: "VMUL.F64", |
| 10204 arm_VMUL_ZZ_F64: "VMUL.ZZ.F64", |
| 10205 arm_VNEG_EQ_F32: "VNEG.EQ.F32", |
| 10206 arm_VNEG_NE_F32: "VNEG.NE.F32", |
| 10207 arm_VNEG_CS_F32: "VNEG.CS.F32", |
| 10208 arm_VNEG_CC_F32: "VNEG.CC.F32", |
| 10209 arm_VNEG_MI_F32: "VNEG.MI.F32", |
| 10210 arm_VNEG_PL_F32: "VNEG.PL.F32", |
| 10211 arm_VNEG_VS_F32: "VNEG.VS.F32", |
| 10212 arm_VNEG_VC_F32: "VNEG.VC.F32", |
| 10213 arm_VNEG_HI_F32: "VNEG.HI.F32", |
| 10214 arm_VNEG_LS_F32: "VNEG.LS.F32", |
| 10215 arm_VNEG_GE_F32: "VNEG.GE.F32", |
| 10216 arm_VNEG_LT_F32: "VNEG.LT.F32", |
| 10217 arm_VNEG_GT_F32: "VNEG.GT.F32", |
| 10218 arm_VNEG_LE_F32: "VNEG.LE.F32", |
| 10219 arm_VNEG_F32: "VNEG.F32", |
| 10220 arm_VNEG_ZZ_F32: "VNEG.ZZ.F32", |
| 10221 arm_VNEG_EQ_F64: "VNEG.EQ.F64", |
| 10222 arm_VNEG_NE_F64: "VNEG.NE.F64", |
| 10223 arm_VNEG_CS_F64: "VNEG.CS.F64", |
| 10224 arm_VNEG_CC_F64: "VNEG.CC.F64", |
| 10225 arm_VNEG_MI_F64: "VNEG.MI.F64", |
| 10226 arm_VNEG_PL_F64: "VNEG.PL.F64", |
| 10227 arm_VNEG_VS_F64: "VNEG.VS.F64", |
| 10228 arm_VNEG_VC_F64: "VNEG.VC.F64", |
| 10229 arm_VNEG_HI_F64: "VNEG.HI.F64", |
| 10230 arm_VNEG_LS_F64: "VNEG.LS.F64", |
| 10231 arm_VNEG_GE_F64: "VNEG.GE.F64", |
| 10232 arm_VNEG_LT_F64: "VNEG.LT.F64", |
| 10233 arm_VNEG_GT_F64: "VNEG.GT.F64", |
| 10234 arm_VNEG_LE_F64: "VNEG.LE.F64", |
| 10235 arm_VNEG_F64: "VNEG.F64", |
| 10236 arm_VNEG_ZZ_F64: "VNEG.ZZ.F64", |
| 10237 arm_VNMLS_EQ_F32: "VNMLS.EQ.F32", |
| 10238 arm_VNMLS_NE_F32: "VNMLS.NE.F32", |
| 10239 arm_VNMLS_CS_F32: "VNMLS.CS.F32", |
| 10240 arm_VNMLS_CC_F32: "VNMLS.CC.F32", |
| 10241 arm_VNMLS_MI_F32: "VNMLS.MI.F32", |
| 10242 arm_VNMLS_PL_F32: "VNMLS.PL.F32", |
| 10243 arm_VNMLS_VS_F32: "VNMLS.VS.F32", |
| 10244 arm_VNMLS_VC_F32: "VNMLS.VC.F32", |
| 10245 arm_VNMLS_HI_F32: "VNMLS.HI.F32", |
| 10246 arm_VNMLS_LS_F32: "VNMLS.LS.F32", |
| 10247 arm_VNMLS_GE_F32: "VNMLS.GE.F32", |
| 10248 arm_VNMLS_LT_F32: "VNMLS.LT.F32", |
| 10249 arm_VNMLS_GT_F32: "VNMLS.GT.F32", |
| 10250 arm_VNMLS_LE_F32: "VNMLS.LE.F32", |
| 10251 arm_VNMLS_F32: "VNMLS.F32", |
| 10252 arm_VNMLS_ZZ_F32: "VNMLS.ZZ.F32", |
| 10253 arm_VNMLS_EQ_F64: "VNMLS.EQ.F64", |
| 10254 arm_VNMLS_NE_F64: "VNMLS.NE.F64", |
| 10255 arm_VNMLS_CS_F64: "VNMLS.CS.F64", |
| 10256 arm_VNMLS_CC_F64: "VNMLS.CC.F64", |
| 10257 arm_VNMLS_MI_F64: "VNMLS.MI.F64", |
| 10258 arm_VNMLS_PL_F64: "VNMLS.PL.F64", |
| 10259 arm_VNMLS_VS_F64: "VNMLS.VS.F64", |
| 10260 arm_VNMLS_VC_F64: "VNMLS.VC.F64", |
| 10261 arm_VNMLS_HI_F64: "VNMLS.HI.F64", |
| 10262 arm_VNMLS_LS_F64: "VNMLS.LS.F64", |
| 10263 arm_VNMLS_GE_F64: "VNMLS.GE.F64", |
| 10264 arm_VNMLS_LT_F64: "VNMLS.LT.F64", |
| 10265 arm_VNMLS_GT_F64: "VNMLS.GT.F64", |
| 10266 arm_VNMLS_LE_F64: "VNMLS.LE.F64", |
| 10267 arm_VNMLS_F64: "VNMLS.F64", |
| 10268 arm_VNMLS_ZZ_F64: "VNMLS.ZZ.F64", |
| 10269 arm_VNMLA_EQ_F32: "VNMLA.EQ.F32", |
| 10270 arm_VNMLA_NE_F32: "VNMLA.NE.F32", |
| 10271 arm_VNMLA_CS_F32: "VNMLA.CS.F32", |
| 10272 arm_VNMLA_CC_F32: "VNMLA.CC.F32", |
| 10273 arm_VNMLA_MI_F32: "VNMLA.MI.F32", |
| 10274 arm_VNMLA_PL_F32: "VNMLA.PL.F32", |
| 10275 arm_VNMLA_VS_F32: "VNMLA.VS.F32", |
| 10276 arm_VNMLA_VC_F32: "VNMLA.VC.F32", |
| 10277 arm_VNMLA_HI_F32: "VNMLA.HI.F32", |
| 10278 arm_VNMLA_LS_F32: "VNMLA.LS.F32", |
| 10279 arm_VNMLA_GE_F32: "VNMLA.GE.F32", |
| 10280 arm_VNMLA_LT_F32: "VNMLA.LT.F32", |
| 10281 arm_VNMLA_GT_F32: "VNMLA.GT.F32", |
| 10282 arm_VNMLA_LE_F32: "VNMLA.LE.F32", |
| 10283 arm_VNMLA_F32: "VNMLA.F32", |
| 10284 arm_VNMLA_ZZ_F32: "VNMLA.ZZ.F32", |
| 10285 arm_VNMLA_EQ_F64: "VNMLA.EQ.F64", |
| 10286 arm_VNMLA_NE_F64: "VNMLA.NE.F64", |
| 10287 arm_VNMLA_CS_F64: "VNMLA.CS.F64", |
| 10288 arm_VNMLA_CC_F64: "VNMLA.CC.F64", |
| 10289 arm_VNMLA_MI_F64: "VNMLA.MI.F64", |
| 10290 arm_VNMLA_PL_F64: "VNMLA.PL.F64", |
| 10291 arm_VNMLA_VS_F64: "VNMLA.VS.F64", |
| 10292 arm_VNMLA_VC_F64: "VNMLA.VC.F64", |
| 10293 arm_VNMLA_HI_F64: "VNMLA.HI.F64", |
| 10294 arm_VNMLA_LS_F64: "VNMLA.LS.F64", |
| 10295 arm_VNMLA_GE_F64: "VNMLA.GE.F64", |
| 10296 arm_VNMLA_LT_F64: "VNMLA.LT.F64", |
| 10297 arm_VNMLA_GT_F64: "VNMLA.GT.F64", |
| 10298 arm_VNMLA_LE_F64: "VNMLA.LE.F64", |
| 10299 arm_VNMLA_F64: "VNMLA.F64", |
| 10300 arm_VNMLA_ZZ_F64: "VNMLA.ZZ.F64", |
| 10301 arm_VNMUL_EQ_F32: "VNMUL.EQ.F32", |
| 10302 arm_VNMUL_NE_F32: "VNMUL.NE.F32", |
| 10303 arm_VNMUL_CS_F32: "VNMUL.CS.F32", |
| 10304 arm_VNMUL_CC_F32: "VNMUL.CC.F32", |
| 10305 arm_VNMUL_MI_F32: "VNMUL.MI.F32", |
| 10306 arm_VNMUL_PL_F32: "VNMUL.PL.F32", |
| 10307 arm_VNMUL_VS_F32: "VNMUL.VS.F32", |
| 10308 arm_VNMUL_VC_F32: "VNMUL.VC.F32", |
| 10309 arm_VNMUL_HI_F32: "VNMUL.HI.F32", |
| 10310 arm_VNMUL_LS_F32: "VNMUL.LS.F32", |
| 10311 arm_VNMUL_GE_F32: "VNMUL.GE.F32", |
| 10312 arm_VNMUL_LT_F32: "VNMUL.LT.F32", |
| 10313 arm_VNMUL_GT_F32: "VNMUL.GT.F32", |
| 10314 arm_VNMUL_LE_F32: "VNMUL.LE.F32", |
| 10315 arm_VNMUL_F32: "VNMUL.F32", |
| 10316 arm_VNMUL_ZZ_F32: "VNMUL.ZZ.F32", |
| 10317 arm_VNMUL_EQ_F64: "VNMUL.EQ.F64", |
| 10318 arm_VNMUL_NE_F64: "VNMUL.NE.F64", |
| 10319 arm_VNMUL_CS_F64: "VNMUL.CS.F64", |
| 10320 arm_VNMUL_CC_F64: "VNMUL.CC.F64", |
| 10321 arm_VNMUL_MI_F64: "VNMUL.MI.F64", |
| 10322 arm_VNMUL_PL_F64: "VNMUL.PL.F64", |
| 10323 arm_VNMUL_VS_F64: "VNMUL.VS.F64", |
| 10324 arm_VNMUL_VC_F64: "VNMUL.VC.F64", |
| 10325 arm_VNMUL_HI_F64: "VNMUL.HI.F64", |
| 10326 arm_VNMUL_LS_F64: "VNMUL.LS.F64", |
| 10327 arm_VNMUL_GE_F64: "VNMUL.GE.F64", |
| 10328 arm_VNMUL_LT_F64: "VNMUL.LT.F64", |
| 10329 arm_VNMUL_GT_F64: "VNMUL.GT.F64", |
| 10330 arm_VNMUL_LE_F64: "VNMUL.LE.F64", |
| 10331 arm_VNMUL_F64: "VNMUL.F64", |
| 10332 arm_VNMUL_ZZ_F64: "VNMUL.ZZ.F64", |
| 10333 arm_VSQRT_EQ_F32: "VSQRT.EQ.F32", |
| 10334 arm_VSQRT_NE_F32: "VSQRT.NE.F32", |
| 10335 arm_VSQRT_CS_F32: "VSQRT.CS.F32", |
| 10336 arm_VSQRT_CC_F32: "VSQRT.CC.F32", |
| 10337 arm_VSQRT_MI_F32: "VSQRT.MI.F32", |
| 10338 arm_VSQRT_PL_F32: "VSQRT.PL.F32", |
| 10339 arm_VSQRT_VS_F32: "VSQRT.VS.F32", |
| 10340 arm_VSQRT_VC_F32: "VSQRT.VC.F32", |
| 10341 arm_VSQRT_HI_F32: "VSQRT.HI.F32", |
| 10342 arm_VSQRT_LS_F32: "VSQRT.LS.F32", |
| 10343 arm_VSQRT_GE_F32: "VSQRT.GE.F32", |
| 10344 arm_VSQRT_LT_F32: "VSQRT.LT.F32", |
| 10345 arm_VSQRT_GT_F32: "VSQRT.GT.F32", |
| 10346 arm_VSQRT_LE_F32: "VSQRT.LE.F32", |
| 10347 arm_VSQRT_F32: "VSQRT.F32", |
| 10348 arm_VSQRT_ZZ_F32: "VSQRT.ZZ.F32", |
| 10349 arm_VSQRT_EQ_F64: "VSQRT.EQ.F64", |
| 10350 arm_VSQRT_NE_F64: "VSQRT.NE.F64", |
| 10351 arm_VSQRT_CS_F64: "VSQRT.CS.F64", |
| 10352 arm_VSQRT_CC_F64: "VSQRT.CC.F64", |
| 10353 arm_VSQRT_MI_F64: "VSQRT.MI.F64", |
| 10354 arm_VSQRT_PL_F64: "VSQRT.PL.F64", |
| 10355 arm_VSQRT_VS_F64: "VSQRT.VS.F64", |
| 10356 arm_VSQRT_VC_F64: "VSQRT.VC.F64", |
| 10357 arm_VSQRT_HI_F64: "VSQRT.HI.F64", |
| 10358 arm_VSQRT_LS_F64: "VSQRT.LS.F64", |
| 10359 arm_VSQRT_GE_F64: "VSQRT.GE.F64", |
| 10360 arm_VSQRT_LT_F64: "VSQRT.LT.F64", |
| 10361 arm_VSQRT_GT_F64: "VSQRT.GT.F64", |
| 10362 arm_VSQRT_LE_F64: "VSQRT.LE.F64", |
| 10363 arm_VSQRT_F64: "VSQRT.F64", |
| 10364 arm_VSQRT_ZZ_F64: "VSQRT.ZZ.F64", |
| 10365 arm_VSTR_EQ: "VSTR.EQ", |
| 10366 arm_VSTR_NE: "VSTR.NE", |
| 10367 arm_VSTR_CS: "VSTR.CS", |
| 10368 arm_VSTR_CC: "VSTR.CC", |
| 10369 arm_VSTR_MI: "VSTR.MI", |
| 10370 arm_VSTR_PL: "VSTR.PL", |
| 10371 arm_VSTR_VS: "VSTR.VS", |
| 10372 arm_VSTR_VC: "VSTR.VC", |
| 10373 arm_VSTR_HI: "VSTR.HI", |
| 10374 arm_VSTR_LS: "VSTR.LS", |
| 10375 arm_VSTR_GE: "VSTR.GE", |
| 10376 arm_VSTR_LT: "VSTR.LT", |
| 10377 arm_VSTR_GT: "VSTR.GT", |
| 10378 arm_VSTR_LE: "VSTR.LE", |
| 10379 arm_VSTR: "VSTR", |
| 10380 arm_VSTR_ZZ: "VSTR.ZZ", |
| 10381 arm_VSUB_EQ_F32: "VSUB.EQ.F32", |
| 10382 arm_VSUB_NE_F32: "VSUB.NE.F32", |
| 10383 arm_VSUB_CS_F32: "VSUB.CS.F32", |
| 10384 arm_VSUB_CC_F32: "VSUB.CC.F32", |
| 10385 arm_VSUB_MI_F32: "VSUB.MI.F32", |
| 10386 arm_VSUB_PL_F32: "VSUB.PL.F32", |
| 10387 arm_VSUB_VS_F32: "VSUB.VS.F32", |
| 10388 arm_VSUB_VC_F32: "VSUB.VC.F32", |
| 10389 arm_VSUB_HI_F32: "VSUB.HI.F32", |
| 10390 arm_VSUB_LS_F32: "VSUB.LS.F32", |
| 10391 arm_VSUB_GE_F32: "VSUB.GE.F32", |
| 10392 arm_VSUB_LT_F32: "VSUB.LT.F32", |
| 10393 arm_VSUB_GT_F32: "VSUB.GT.F32", |
| 10394 arm_VSUB_LE_F32: "VSUB.LE.F32", |
| 10395 arm_VSUB_F32: "VSUB.F32", |
| 10396 arm_VSUB_ZZ_F32: "VSUB.ZZ.F32", |
| 10397 arm_VSUB_EQ_F64: "VSUB.EQ.F64", |
| 10398 arm_VSUB_NE_F64: "VSUB.NE.F64", |
| 10399 arm_VSUB_CS_F64: "VSUB.CS.F64", |
| 10400 arm_VSUB_CC_F64: "VSUB.CC.F64", |
| 10401 arm_VSUB_MI_F64: "VSUB.MI.F64", |
| 10402 arm_VSUB_PL_F64: "VSUB.PL.F64", |
| 10403 arm_VSUB_VS_F64: "VSUB.VS.F64", |
| 10404 arm_VSUB_VC_F64: "VSUB.VC.F64", |
| 10405 arm_VSUB_HI_F64: "VSUB.HI.F64", |
| 10406 arm_VSUB_LS_F64: "VSUB.LS.F64", |
| 10407 arm_VSUB_GE_F64: "VSUB.GE.F64", |
| 10408 arm_VSUB_LT_F64: "VSUB.LT.F64", |
| 10409 arm_VSUB_GT_F64: "VSUB.GT.F64", |
| 10410 arm_VSUB_LE_F64: "VSUB.LE.F64", |
| 10411 arm_VSUB_F64: "VSUB.F64", |
| 10412 arm_VSUB_ZZ_F64: "VSUB.ZZ.F64", |
| 10413 arm_WFE_EQ: "WFE.EQ", |
| 10414 arm_WFE_NE: "WFE.NE", |
| 10415 arm_WFE_CS: "WFE.CS", |
| 10416 arm_WFE_CC: "WFE.CC", |
| 10417 arm_WFE_MI: "WFE.MI", |
| 10418 arm_WFE_PL: "WFE.PL", |
| 10419 arm_WFE_VS: "WFE.VS", |
| 10420 arm_WFE_VC: "WFE.VC", |
| 10421 arm_WFE_HI: "WFE.HI", |
| 10422 arm_WFE_LS: "WFE.LS", |
| 10423 arm_WFE_GE: "WFE.GE", |
| 10424 arm_WFE_LT: "WFE.LT", |
| 10425 arm_WFE_GT: "WFE.GT", |
| 10426 arm_WFE_LE: "WFE.LE", |
| 10427 arm_WFE: "WFE", |
| 10428 arm_WFE_ZZ: "WFE.ZZ", |
| 10429 arm_WFI_EQ: "WFI.EQ", |
| 10430 arm_WFI_NE: "WFI.NE", |
| 10431 arm_WFI_CS: "WFI.CS", |
| 10432 arm_WFI_CC: "WFI.CC", |
| 10433 arm_WFI_MI: "WFI.MI", |
| 10434 arm_WFI_PL: "WFI.PL", |
| 10435 arm_WFI_VS: "WFI.VS", |
| 10436 arm_WFI_VC: "WFI.VC", |
| 10437 arm_WFI_HI: "WFI.HI", |
| 10438 arm_WFI_LS: "WFI.LS", |
| 10439 arm_WFI_GE: "WFI.GE", |
| 10440 arm_WFI_LT: "WFI.LT", |
| 10441 arm_WFI_GT: "WFI.GT", |
| 10442 arm_WFI_LE: "WFI.LE", |
| 10443 arm_WFI: "WFI", |
| 10444 arm_WFI_ZZ: "WFI.ZZ", |
| 10445 arm_YIELD_EQ: "YIELD.EQ", |
| 10446 arm_YIELD_NE: "YIELD.NE", |
| 10447 arm_YIELD_CS: "YIELD.CS", |
| 10448 arm_YIELD_CC: "YIELD.CC", |
| 10449 arm_YIELD_MI: "YIELD.MI", |
| 10450 arm_YIELD_PL: "YIELD.PL", |
| 10451 arm_YIELD_VS: "YIELD.VS", |
| 10452 arm_YIELD_VC: "YIELD.VC", |
| 10453 arm_YIELD_HI: "YIELD.HI", |
| 10454 arm_YIELD_LS: "YIELD.LS", |
| 10455 arm_YIELD_GE: "YIELD.GE", |
| 10456 arm_YIELD_LT: "YIELD.LT", |
| 10457 arm_YIELD_GT: "YIELD.GT", |
| 10458 arm_YIELD_LE: "YIELD.LE", |
| 10459 arm_YIELD: "YIELD", |
| 10460 arm_YIELD_ZZ: "YIELD.ZZ", |
7983 } | 10461 } |
7984 | 10462 |
7985 var arm_instFormats = [...]arm_instFormat{ | 10463 var arm_instFormats = [...]arm_instFormat{ |
7986 {0x0fe00000, 0x02a00000, 2, arm_ADC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_const}}, // ADC{S}<c> <Rd>,<Rn>,#
<const> cond:4|0|0|1|0|1|0|1|S|Rn:4|Rd:4|imm12:12 | 10464 {0x0fe00000, 0x02a00000, 2, arm_ADC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_const}}, // ADC{S}<c> <Rd>,<Rn
>,#<const> cond:4|0|0|1|0|1|0|1|S|Rn:4|Rd:4|imm12:12 |
7987 {0x0fe00090, 0x00a00010, 4, arm_ADC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // ADC{S}<c> <Rd>,<Rn>,<
Rm>,<type> <Rs> cond:4|0|0|0|0|1|0|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 | 10465 {0x0fe00090, 0x00a00010, 4, arm_ADC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // ADC{S}<c> <Rd>,<Rn
>,<Rm>,<type> <Rs> cond:4|0|0|0|0|1|0|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 |
7988 {0x0fe00010, 0x00a00000, 2, arm_ADC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // ADC{S}<c> <Rd>,<Rn>,<
Rm>{,<shift>} cond:4|0|0|0|0|1|0|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 | 10466 {0x0fe00010, 0x00a00000, 2, arm_ADC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // ADC{S}<c> <Rd>,<Rn
>,<Rm>{,<shift>} cond:4|0|0|0|0|1|0|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 |
7989 {0x0fe00000, 0x02800000, 2, arm_ADD_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_const}}, // ADD{S}<c> <Rd>,<Rn>,#
<const> cond:4|0|0|1|0|1|0|0|S|Rn:4|Rd:4|imm12:12 | 10467 {0x0fe00000, 0x02800000, 2, arm_ADD_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_const}}, // ADD{S}<c> <Rd>,<Rn
>,#<const> cond:4|0|0|1|0|1|0|0|S|Rn:4|Rd:4|imm12:12 |
7990 {0x0fe00090, 0x00800010, 4, arm_ADD_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // ADD{S}<c> <Rd>,<Rn>,<
Rm>,<type> <Rs> cond:4|0|0|0|0|1|0|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 | 10468 {0x0fe00090, 0x00800010, 4, arm_ADD_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // ADD{S}<c> <Rd>,<Rn
>,<Rm>,<type> <Rs> cond:4|0|0|0|0|1|0|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 |
7991 {0x0fe00010, 0x00800000, 2, arm_ADD_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // ADD{S}<c> <Rd>,<Rn>,<
Rm>{,<shift>} cond:4|0|0|0|0|1|0|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 | 10469 {0x0fe00010, 0x00800000, 2, arm_ADD_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // ADD{S}<c> <Rd>,<Rn
>,<Rm>{,<shift>} cond:4|0|0|0|0|1|0|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 |
7992 {0x0fef0000, 0x028d0000, 2, arm_ADD_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_SP, arm_arg_const}}, // ADD{S}<c> <Rd>,SP,#<c
onst> cond:4|0|0|1|0|1|0|0|S|1|1|0|1|Rd:4|imm12:12 | 10470 {0x0fef0000, 0x028d0000, 2, arm_ADD_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_SP, arm_arg_const}}, // ADD{S}<c> <Rd>,SP,
#<const> cond:4|0|0|1|0|1|0|0|S|1|1|0|1|Rd:4|imm12:12 |
7993 {0x0fef0010, 0x008d0000, 2, arm_ADD_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_SP, arm_arg_R_shift_imm}}, // ADD{S}<c> <Rd>,SP,<Rm
>{,<shift>} cond:4|0|0|0|0|1|0|0|S|1|1|0|1|Rd:4|imm5:5|type:2|0|Rm:4 | 10471 {0x0fef0010, 0x008d0000, 2, arm_ADD_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_SP, arm_arg_R_shift_imm}}, // ADD{S}<c> <Rd>,SP,
<Rm>{,<shift>} cond:4|0|0|0|0|1|0|0|S|1|1|0|1|Rd:4|imm5:5|type:2|0|Rm:4 |
7994 {0x0fe00000, 0x02000000, 2, arm_AND_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_const}}, // AND{S}<c> <Rd>,<Rn>,#
<const> cond:4|0|0|1|0|0|0|0|S|Rn:4|Rd:4|imm12:12 | 10472 {0x0fe00000, 0x02000000, 2, arm_AND_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_const}}, // AND{S}<c> <Rd>,<Rn
>,#<const> cond:4|0|0|1|0|0|0|0|S|Rn:4|Rd:4|imm12:12 |
7995 {0x0fe00090, 0x00000010, 4, arm_AND_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // AND{S}<c> <Rd>,<Rn>,<
Rm>,<type> <Rs> cond:4|0|0|0|0|0|0|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 | 10473 {0x0fe00090, 0x00000010, 4, arm_AND_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // AND{S}<c> <Rd>,<Rn
>,<Rm>,<type> <Rs> cond:4|0|0|0|0|0|0|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 |
7996 {0x0fe00010, 0x00000000, 2, arm_AND_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // AND{S}<c> <Rd>,<Rn>,<
Rm>{,<shift>} cond:4|0|0|0|0|0|0|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 | 10474 {0x0fe00010, 0x00000000, 2, arm_AND_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // AND{S}<c> <Rd>,<Rn
>,<Rm>{,<shift>} cond:4|0|0|0|0|0|0|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 |
7997 {0x0fef0070, 0x01a00040, 4, arm_ASR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_0, arm_arg_imm5_32}}, // ASR{S}<c> <Rd>,<Rm>,#
<imm5_32> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|1|0|0|Rm:4 | 10475 {0x0fef0070, 0x01a00040, 4, arm_ASR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_0, arm_arg_imm5_32}}, // ASR{S}<c> <Rd>,<Rm
>,#<imm5_32> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|1|0|0|Rm:4 |
7998 {0x0fef00f0, 0x01a00050, 4, arm_ASR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_0, arm_arg_R_8}}, // ASR{S}<c> <Rd>,<Rn>,<
Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|1|0|1|Rn:4 | 10476 {0x0fef00f0, 0x01a00050, 4, arm_ASR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_0, arm_arg_R_8}}, // ASR{S}<c> <Rd>,<Rn
>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|1|0|1|Rn:4 |
7999 {0x0f000000, 0x0a000000, 4, arm_B_EQ, 0x1c04, arm_instArgs{arm_arg_label
24}}, // B<c> <label24> cond:4
|1|0|1|0|imm24:24 | 10477 {0x0f000000, 0x0a000000, 4, arm_B_EQ, 0x1c04, arm_instArgs{arm_arg_label
24}}, // B<c> <label24> con
d:4|1|0|1|0|imm24:24 |
8000 {0x0fe0007f, 0x07c0001f, 4, arm_BFC_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_imm5, arm_arg_lsb_width}}, // BFC<c> <Rd>,#<lsb>,#<
width> cond:4|0|1|1|1|1|1|0|msb:5|Rd:4|lsb:5|0|0|1|1|1|1|1 | 10478 {0x0fe0007f, 0x07c0001f, 4, arm_BFC_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_imm5, arm_arg_lsb_width}}, // BFC<c> <Rd>,#<lsb>
,#<width> cond:4|0|1|1|1|1|1|0|msb:5|Rd:4|lsb:5|0|0|1|1|1|1|1 |
8001 {0x0fe00070, 0x07c00010, 2, arm_BFI_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_R_0, arm_arg_imm5, arm_arg_lsb_width}}, // BFI<c> <Rd>,<Rn>,#<ls
b>,#<width> cond:4|0|1|1|1|1|1|0|msb:5|Rd:4|lsb:5|0|0|1|Rn:4 | 10479 {0x0fe00070, 0x07c00010, 2, arm_BFI_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_R_0, arm_arg_imm5, arm_arg_lsb_width}}, // BFI<c> <Rd>,<Rn>,#
<lsb>,#<width> cond:4|0|1|1|1|1|1|0|msb:5|Rd:4|lsb:5|0|0|1|Rn:4 |
8002 {0x0fe00000, 0x03c00000, 2, arm_BIC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_const}}, // BIC{S}<c> <Rd>,<Rn>,#
<const> cond:4|0|0|1|1|1|1|0|S|Rn:4|Rd:4|imm12:12 | 10480 {0x0fe00000, 0x03c00000, 2, arm_BIC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_const}}, // BIC{S}<c> <Rd>,<Rn
>,#<const> cond:4|0|0|1|1|1|1|0|S|Rn:4|Rd:4|imm12:12 |
8003 {0x0fe00090, 0x01c00010, 4, arm_BIC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // BIC{S}<c> <Rd>,<Rn>,<
Rm>,<type> <Rs> cond:4|0|0|0|1|1|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 | 10481 {0x0fe00090, 0x01c00010, 4, arm_BIC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // BIC{S}<c> <Rd>,<Rn
>,<Rm>,<type> <Rs> cond:4|0|0|0|1|1|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 |
8004 {0x0fe00010, 0x01c00000, 2, arm_BIC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // BIC{S}<c> <Rd>,<Rn>,<
Rm>{,<shift>} cond:4|0|0|0|1|1|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 | 10482 {0x0fe00010, 0x01c00000, 2, arm_BIC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // BIC{S}<c> <Rd>,<Rn
>,<Rm>{,<shift>} cond:4|0|0|0|1|1|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 |
8005 {0x0ff000f0, 0x01200070, 4, arm_BKPT_EQ, 0x1c04, arm_instArgs{arm_arg_im
m_12at8_4at0}}, // BKPT<c> #<imm12+4> co
nd:4|0|0|0|1|0|0|1|0|imm12:12|0|1|1|1|imm4:4 | 10483 {0x0ff000f0, 0x01200070, 4, arm_BKPT_EQ, 0x1c04, arm_instArgs{arm_arg_im
m_12at8_4at0}}, // BKPT<c> #<imm12+4>
cond:4|0|0|0|1|0|0|1|0|imm12:12|0|1|1|1|imm4:4 |
8006 {0x0f000000, 0x0b000000, 4, arm_BL_EQ, 0x1c04, arm_instArgs{arm_arg_labe
l24}}, // BL<c> <label24> cond:
4|1|0|1|1|imm24:24 | 10484 {0x0f000000, 0x0b000000, 4, arm_BL_EQ, 0x1c04, arm_instArgs{arm_arg_labe
l24}}, // BL<c> <label24> co
nd:4|1|0|1|1|imm24:24 |
8007 {0xfe000000, 0xfa000000, 4, arm_BLX, 0x0, arm_instArgs{arm_arg_label24H}
}, // BLX <label24H> 1|1|1|
1|1|0|1|H|imm24:24 | 10485 {0xfe000000, 0xfa000000, 4, arm_BLX, 0x0, arm_instArgs{arm_arg_label24H}
}, // BLX <label24H> 1|1
|1|1|1|0|1|H|imm24:24 |
8008 {0x0ffffff0, 0x012fff30, 4, arm_BLX_EQ, 0x1c04, arm_instArgs{arm_arg_R_0
}}, // BLX<c> <Rm> cond:4|0|
0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 | 10486 {0x0ffffff0, 0x012fff30, 4, arm_BLX_EQ, 0x1c04, arm_instArgs{arm_arg_R_0
}}, // BLX<c> <Rm> cond:4
|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 |
8009 {0x0ff000f0, 0x012fff30, 3, arm_BLX_EQ, 0x1c04, arm_instArgs{arm_arg_R_0
}}, // BLX<c> <Rm> cond:4|0|
0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 | 10487 {0x0ff000f0, 0x012fff30, 3, arm_BLX_EQ, 0x1c04, arm_instArgs{arm_arg_R_0
}}, // BLX<c> <Rm> cond:4
|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 |
8010 {0x0ffffff0, 0x012fff10, 4, arm_BX_EQ, 0x1c04, arm_instArgs{arm_arg_R_0}
}, // BX<c> <Rm> cond:4|0|0
|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 | 10488 {0x0ffffff0, 0x012fff10, 4, arm_BX_EQ, 0x1c04, arm_instArgs{arm_arg_R_0}
}, // BX<c> <Rm> cond:4|
0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 |
8011 {0x0ff000f0, 0x012fff10, 3, arm_BX_EQ, 0x1c04, arm_instArgs{arm_arg_R_0}
}, // BX<c> <Rm> cond:4|0|0
|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 | 10489 {0x0ff000f0, 0x012fff10, 3, arm_BX_EQ, 0x1c04, arm_instArgs{arm_arg_R_0}
}, // BX<c> <Rm> cond:4|
0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 |
8012 {0x0ffffff0, 0x012fff20, 4, arm_BXJ_EQ, 0x1c04, arm_instArgs{arm_arg_R_0
}}, // BXJ<c> <Rm> cond:4|0|
0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|0|Rm:4 | 10490 {0x0ffffff0, 0x012fff20, 4, arm_BXJ_EQ, 0x1c04, arm_instArgs{arm_arg_R_0
}}, // BXJ<c> <Rm> cond:4
|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|0|Rm:4 |
8013 {0x0ff000f0, 0x012fff20, 3, arm_BXJ_EQ, 0x1c04, arm_instArgs{arm_arg_R_0
}}, // BXJ<c> <Rm> cond:4|0|
0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|0|Rm:4 | 10491 {0x0ff000f0, 0x012fff20, 3, arm_BXJ_EQ, 0x1c04, arm_instArgs{arm_arg_R_0
}}, // BXJ<c> <Rm> cond:4
|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|0|Rm:4 |
8014 {0xffffffff, 0xf57ff01f, 4, arm_CLREX, 0x0, arm_instArgs{}},
// CLREX 1|1|1|1|0|1|0|1
|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|1|(1)|(1)|(1)|(1) | 10492 {0xffffffff, 0xf57ff01f, 4, arm_CLREX, 0x0, arm_instArgs{}},
// CLREX 1|1|1|1|0|1|
0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|1|(1)|(1)|(1)|
(1) |
8015 {0xfff000f0, 0xf57ff01f, 3, arm_CLREX, 0x0, arm_instArgs{}},
// CLREX 1|1|1|1|0|1|0|1
|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|1|(1)|(1)|(1)|(1) | 10493 {0xfff000f0, 0xf57ff01f, 3, arm_CLREX, 0x0, arm_instArgs{}},
// CLREX 1|1|1|1|0|1|
0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|1|(1)|(1)|(1)|
(1) |
8016 {0x0fff0ff0, 0x016f0f10, 4, arm_CLZ_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_R_0}}, // CLZ<c> <Rd>,<Rm> cond
:4|0|0|0|1|0|1|1|0|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 | 10494 {0x0fff0ff0, 0x016f0f10, 4, arm_CLZ_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_R_0}}, // CLZ<c> <Rd>,<Rm> c
ond:4|0|0|0|1|0|1|1|0|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 |
8017 {0x0ff000f0, 0x016f0f10, 3, arm_CLZ_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_R_0}}, // CLZ<c> <Rd>,<Rm> cond
:4|0|0|0|1|0|1|1|0|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 | 10495 {0x0ff000f0, 0x016f0f10, 3, arm_CLZ_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_R_0}}, // CLZ<c> <Rd>,<Rm> c
ond:4|0|0|0|1|0|1|1|0|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 |
8018 {0x0ff0f000, 0x03700000, 4, arm_CMN_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_const}}, // CMN<c> <Rn>,#<const>
cond:4|0|0|1|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 | 10496 {0x0ff0f000, 0x03700000, 4, arm_CMN_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_const}}, // CMN<c> <Rn>,#<cons
t> cond:4|0|0|1|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 |
8019 {0x0ff00000, 0x03700000, 3, arm_CMN_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_const}}, // CMN<c> <Rn>,#<const>
cond:4|0|0|1|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 | 10497 {0x0ff00000, 0x03700000, 3, arm_CMN_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_const}}, // CMN<c> <Rn>,#<cons
t> cond:4|0|0|1|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 |
8020 {0x0ff0f090, 0x01700010, 4, arm_CMN_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_R}}, // CMN<c> <Rn>,<Rm>,<typ
e> <Rs> cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 | 10498 {0x0ff0f090, 0x01700010, 4, arm_CMN_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_R}}, // CMN<c> <Rn>,<Rm>,<
type> <Rs> cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 |
8021 {0x0ff00090, 0x01700010, 3, arm_CMN_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_R}}, // CMN<c> <Rn>,<Rm>,<typ
e> <Rs> cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 | 10499 {0x0ff00090, 0x01700010, 3, arm_CMN_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_R}}, // CMN<c> <Rn>,<Rm>,<
type> <Rs> cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 |
8022 {0x0ff0f010, 0x01700000, 4, arm_CMN_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_imm}}, // CMN<c> <Rn>,<Rm>{,<sh
ift>} cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 | 10500 {0x0ff0f010, 0x01700000, 4, arm_CMN_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_imm}}, // CMN<c> <Rn>,<Rm>{,
<shift>} cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 |
8023 {0x0ff00010, 0x01700000, 3, arm_CMN_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_imm}}, // CMN<c> <Rn>,<Rm>{,<sh
ift>} cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 | 10501 {0x0ff00010, 0x01700000, 3, arm_CMN_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_imm}}, // CMN<c> <Rn>,<Rm>{,
<shift>} cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 |
8024 {0x0ff0f000, 0x03500000, 4, arm_CMP_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_const}}, // CMP<c> <Rn>,#<const>
cond:4|0|0|1|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 | 10502 {0x0ff0f000, 0x03500000, 4, arm_CMP_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_const}}, // CMP<c> <Rn>,#<cons
t> cond:4|0|0|1|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 |
8025 {0x0ff00000, 0x03500000, 3, arm_CMP_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_const}}, // CMP<c> <Rn>,#<const>
cond:4|0|0|1|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 | 10503 {0x0ff00000, 0x03500000, 3, arm_CMP_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_const}}, // CMP<c> <Rn>,#<cons
t> cond:4|0|0|1|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 |
8026 {0x0ff0f090, 0x01500010, 4, arm_CMP_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_R}}, // CMP<c> <Rn>,<Rm>,<typ
e> <Rs> cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 | 10504 {0x0ff0f090, 0x01500010, 4, arm_CMP_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_R}}, // CMP<c> <Rn>,<Rm>,<
type> <Rs> cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 |
8027 {0x0ff00090, 0x01500010, 3, arm_CMP_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_R}}, // CMP<c> <Rn>,<Rm>,<typ
e> <Rs> cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 | 10505 {0x0ff00090, 0x01500010, 3, arm_CMP_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_R}}, // CMP<c> <Rn>,<Rm>,<
type> <Rs> cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 |
8028 {0x0ff0f010, 0x01500000, 4, arm_CMP_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_imm}}, // CMP<c> <Rn>,<Rm>{,<sh
ift>} cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 | 10506 {0x0ff0f010, 0x01500000, 4, arm_CMP_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_imm}}, // CMP<c> <Rn>,<Rm>{,
<shift>} cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 |
8029 {0x0ff00010, 0x01500000, 3, arm_CMP_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_imm}}, // CMP<c> <Rn>,<Rm>{,<sh
ift>} cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 | 10507 {0x0ff00010, 0x01500000, 3, arm_CMP_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_imm}}, // CMP<c> <Rn>,<Rm>{,
<shift>} cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 |
8030 {0x0ffffff0, 0x0320f0f0, 4, arm_DBG_EQ, 0x1c04, arm_instArgs{arm_arg_opt
ion}}, // DBG<c> #<option> cond
:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|1|1|1|1|option:4 | 10508 {0x0ffffff0, 0x0320f0f0, 4, arm_DBG_EQ, 0x1c04, arm_instArgs{arm_arg_opt
ion}}, // DBG<c> #<option> c
ond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|1|1|1|1|option:4 |
8031 {0x0fff00f0, 0x0320f0f0, 3, arm_DBG_EQ, 0x1c04, arm_instArgs{arm_arg_opt
ion}}, // DBG<c> #<option> cond
:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|1|1|1|1|option:4 | 10509 {0x0fff00f0, 0x0320f0f0, 3, arm_DBG_EQ, 0x1c04, arm_instArgs{arm_arg_opt
ion}}, // DBG<c> #<option> c
ond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|1|1|1|1|option:4 |
8032 {0xfffffff0, 0xf57ff050, 4, arm_DMB, 0x0, arm_instArgs{arm_arg_option}},
// DMB #<option> 1|1|1|1
|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|1|option:
4 | 10510 {0xfffffff0, 0xf57ff050, 4, arm_DMB, 0x0, arm_instArgs{arm_arg_option}},
// DMB #<option> 1|1|
1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|1|opti
on:4 |
8033 {0xfff000f0, 0xf57ff050, 3, arm_DMB, 0x0, arm_instArgs{arm_arg_option}},
// DMB #<option> 1|1|1|1
|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|1|option:
4 | 10511 {0xfff000f0, 0xf57ff050, 3, arm_DMB, 0x0, arm_instArgs{arm_arg_option}},
// DMB #<option> 1|1|
1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|1|opti
on:4 |
8034 {0xfffffff0, 0xf57ff040, 4, arm_DSB, 0x0, arm_instArgs{arm_arg_option}},
// DSB #<option> 1|1|1|1
|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|0|option:
4 | 10512 {0xfffffff0, 0xf57ff040, 4, arm_DSB, 0x0, arm_instArgs{arm_arg_option}},
// DSB #<option> 1|1|
1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|0|opti
on:4 |
8035 {0xfff000f0, 0xf57ff040, 3, arm_DSB, 0x0, arm_instArgs{arm_arg_option}},
// DSB #<option> 1|1|1|1
|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|0|option:
4 | 10513 {0xfff000f0, 0xf57ff040, 3, arm_DSB, 0x0, arm_instArgs{arm_arg_option}},
// DSB #<option> 1|1|
1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|0|opti
on:4 |
8036 {0x0fe00000, 0x02200000, 2, arm_EOR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_const}}, // EOR{S}<c> <Rd>,<Rn>,#
<const> cond:4|0|0|1|0|0|0|1|S|Rn:4|Rd:4|imm12:12 | 10514 {0x0fe00000, 0x02200000, 2, arm_EOR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_const}}, // EOR{S}<c> <Rd>,<Rn
>,#<const> cond:4|0|0|1|0|0|0|1|S|Rn:4|Rd:4|imm12:12 |
8037 {0x0fe00090, 0x00200010, 4, arm_EOR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // EOR{S}<c> <Rd>,<Rn>,<
Rm>,<type> <Rs> cond:4|0|0|0|0|0|0|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 | 10515 {0x0fe00090, 0x00200010, 4, arm_EOR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // EOR{S}<c> <Rd>,<Rn
>,<Rm>,<type> <Rs> cond:4|0|0|0|0|0|0|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 |
8038 {0x0fe00010, 0x00200000, 2, arm_EOR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // EOR{S}<c> <Rd>,<Rn>,<
Rm>{,<shift>} cond:4|0|0|0|0|0|0|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 | 10516 {0x0fe00010, 0x00200000, 2, arm_EOR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // EOR{S}<c> <Rd>,<Rn
>,<Rm>{,<shift>} cond:4|0|0|0|0|0|0|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 |
8039 {0xfffffff0, 0xf57ff060, 4, arm_ISB, 0x0, arm_instArgs{arm_arg_option}},
// ISB #<option> 1|1|1|1
|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|1|0|option:
4 | 10517 {0xfffffff0, 0xf57ff060, 4, arm_ISB, 0x0, arm_instArgs{arm_arg_option}},
// ISB #<option> 1|1|
1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|1|0|opti
on:4 |
8040 {0xfff000f0, 0xf57ff060, 3, arm_ISB, 0x0, arm_instArgs{arm_arg_option}},
// ISB #<option> 1|1|1|1
|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|1|0|option:
4 | 10518 {0xfff000f0, 0xf57ff060, 3, arm_ISB, 0x0, arm_instArgs{arm_arg_option}},
// ISB #<option> 1|1|
1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|1|0|opti
on:4 |
8041 {0x0fd00000, 0x08900000, 2, arm_LDM_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6_WB, arm_arg_registers}}, // LDM<c> <Rn>{!},<regis
ters> cond:4|1|0|0|0|1|0|W|1|Rn:4|register_list:16 | 10519 {0x0fd00000, 0x08900000, 2, arm_LDM_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6_WB, arm_arg_registers}}, // LDM<c> <Rn>{!},<re
gisters> cond:4|1|0|0|0|1|0|W|1|Rn:4|register_list:16 |
8042 {0x0fd00000, 0x08100000, 4, arm_LDMDA_EQ, 0x1c04, arm_instArgs{arm_arg_R
_16_WB, arm_arg_registers}}, // LDMDA<c> <Rn>{!},<reg
isters> cond:4|1|0|0|0|0|0|W|1|Rn:4|register_list:16 | 10520 {0x0fd00000, 0x08100000, 4, arm_LDMDA_EQ, 0x1c04, arm_instArgs{arm_arg_R
_16_WB, arm_arg_registers}}, // LDMDA<c> <Rn>{!},<
registers> cond:4|1|0|0|0|0|0|W|1|Rn:4|register_list:16 |
8043 {0x0fd00000, 0x09100000, 4, arm_LDMDB_EQ, 0x1c04, arm_instArgs{arm_arg_R
_16_WB, arm_arg_registers}}, // LDMDB<c> <Rn>{!},<reg
isters> cond:4|1|0|0|1|0|0|W|1|Rn:4|register_list:16 | 10521 {0x0fd00000, 0x09100000, 4, arm_LDMDB_EQ, 0x1c04, arm_instArgs{arm_arg_R
_16_WB, arm_arg_registers}}, // LDMDB<c> <Rn>{!},<
registers> cond:4|1|0|0|1|0|0|W|1|Rn:4|register_list:16 |
8044 {0x0fd00000, 0x09900000, 4, arm_LDMIB_EQ, 0x1c04, arm_instArgs{arm_arg_R
_16_WB, arm_arg_registers}}, // LDMIB<c> <Rn>{!},<reg
isters> cond:4|1|0|0|1|1|0|W|1|Rn:4|register_list:16 | 10522 {0x0fd00000, 0x09900000, 4, arm_LDMIB_EQ, 0x1c04, arm_instArgs{arm_arg_R
_16_WB, arm_arg_registers}}, // LDMIB<c> <Rn>{!},<
registers> cond:4|1|0|0|1|1|0|W|1|Rn:4|register_list:16 |
8045 {0x0f7f0000, 0x051f0000, 4, arm_LDR_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_label_pm_12}}, // LDR<c> <Rt>,<label+/-
12> cond:4|0|1|0|(1)|U|0|(0)|1|1|1|1|1|Rt:4|imm12:12 | 10523 {0x0f7f0000, 0x051f0000, 4, arm_LDR_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_label_pm_12}}, // LDR<c> <Rt>,<label
+/-12> cond:4|0|1|0|(1)|U|0|(0)|1|1|1|1|1|Rt:4|imm12:12 |
8046 {0x0e5f0000, 0x051f0000, 3, arm_LDR_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_label_pm_12}}, // LDR<c> <Rt>,<label+/-
12> cond:4|0|1|0|(1)|U|0|(0)|1|1|1|1|1|Rt:4|imm12:12 | 10524 {0x0e5f0000, 0x051f0000, 3, arm_LDR_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_label_pm_12}}, // LDR<c> <Rt>,<label
+/-12> cond:4|0|1|0|(1)|U|0|(0)|1|1|1|1|1|Rt:4|imm12:12 |
8047 {0x0e500010, 0x06100000, 2, arm_LDR_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_mem_R_pm_R_shift_imm_W}}, // LDR<c> <Rt>,[<Rn>,+/-
<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|0|W|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 | 10525 {0x0e500010, 0x06100000, 2, arm_LDR_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_mem_R_pm_R_shift_imm_W}}, // LDR<c> <Rt>,[<Rn>,
+/-<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|0|W|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 |
8048 {0x0e500000, 0x04100000, 2, arm_LDR_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_mem_R_pm_imm12_W}}, // LDR<c> <Rt>,[<Rn>{,#+
/-<imm12>}]{!} cond:4|0|1|0|P|U|0|W|1|Rn:4|Rt:4|imm12:12 | 10526 {0x0e500000, 0x04100000, 2, arm_LDR_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_mem_R_pm_imm12_W}}, // LDR<c> <Rt>,[<Rn>{
,#+/-<imm12>}]{!} cond:4|0|1|0|P|U|0|W|1|Rn:4|Rt:4|imm12:12 |
8049 {0x0f7f0000, 0x055f0000, 4, arm_LDRB_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_label_pm_12}}, // LDRB<c> <Rt>,<label+/
-12> cond:4|0|1|0|(1)|U|1|(0)|1|1|1|1|1|Rt:4|imm12:12 | 10527 {0x0f7f0000, 0x055f0000, 4, arm_LDRB_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_label_pm_12}}, // LDRB<c> <Rt>,<labe
l+/-12> cond:4|0|1|0|(1)|U|1|(0)|1|1|1|1|1|Rt:4|imm12:12 |
8050 {0x0e5f0000, 0x055f0000, 3, arm_LDRB_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_label_pm_12}}, // LDRB<c> <Rt>,<label+/
-12> cond:4|0|1|0|(1)|U|1|(0)|1|1|1|1|1|Rt:4|imm12:12 | 10528 {0x0e5f0000, 0x055f0000, 3, arm_LDRB_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_label_pm_12}}, // LDRB<c> <Rt>,<labe
l+/-12> cond:4|0|1|0|(1)|U|1|(0)|1|1|1|1|1|Rt:4|imm12:12 |
8051 {0x0e500010, 0x06500000, 2, arm_LDRB_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_R_shift_imm_W}}, // LDRB<c> <Rt>,[<Rn>,+/
-<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|1|W|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 | 10529 {0x0e500010, 0x06500000, 2, arm_LDRB_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_R_shift_imm_W}}, // LDRB<c> <Rt>,[<Rn>
,+/-<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|1|W|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 |
8052 {0x0e500000, 0x04500000, 2, arm_LDRB_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_imm12_W}}, // LDRB<c> <Rt>,[<Rn>{,#
+/-<imm12>}]{!} cond:4|0|1|0|P|U|1|W|1|Rn:4|Rt:4|imm12:12 | 10530 {0x0e500000, 0x04500000, 2, arm_LDRB_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_imm12_W}}, // LDRB<c> <Rt>,[<Rn>
{,#+/-<imm12>}]{!} cond:4|0|1|0|P|U|1|W|1|Rn:4|Rt:4|imm12:12 |
8053 {0x0f700000, 0x04700000, 4, arm_LDRBT_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_imm12_postindex}}, // LDRBT<c> <Rt>,[<Rn>],
#+/-<imm12> cond:4|0|1|0|0|U|1|1|1|Rn:4|Rt:4|imm12:12 | 10531 {0x0f700000, 0x04700000, 4, arm_LDRBT_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_imm12_postindex}}, // LDRBT<c> <Rt>,[<Rn
>],#+/-<imm12> cond:4|0|1|0|0|U|1|1|1|Rn:4|Rt:4|imm12:12 |
8054 {0x0f700010, 0x06700000, 4, arm_LDRBT_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_R_shift_imm_postindex}}, // LDRBT<c> <Rt>,[<Rn>],
+/-<Rm>{, <shift>} cond:4|0|1|1|0|U|1|1|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 | 10532 {0x0f700010, 0x06700000, 4, arm_LDRBT_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_R_shift_imm_postindex}}, // LDRBT<c> <Rt>,[<Rn
>],+/-<Rm>{, <shift>} cond:4|0|1|1|0|U|1|1|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 |
8055 {0x0e500ff0, 0x000000d0, 4, arm_LDRD_EQ, 0x1c04, arm_instArgs{arm_arg_R1
_12, arm_arg_R2_12, arm_arg_mem_R_pm_R_W}}, // LDRD<c> <Rt1>,<Rt2>,[
<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|0|1|Rm:4 | 10533 {0x0e500ff0, 0x000000d0, 4, arm_LDRD_EQ, 0x1c04, arm_instArgs{arm_arg_R1
_12, arm_arg_R2_12, arm_arg_mem_R_pm_R_W}}, // LDRD<c> <Rt1>,<Rt2
>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|0|1|Rm:
4 |
8056 {0x0e5000f0, 0x000000d0, 3, arm_LDRD_EQ, 0x1c04, arm_instArgs{arm_arg_R1
_12, arm_arg_R2_12, arm_arg_mem_R_pm_R_W}}, // LDRD<c> <Rt1>,<Rt2>,[
<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|0|1|Rm:4 | 10534 {0x0e5000f0, 0x000000d0, 3, arm_LDRD_EQ, 0x1c04, arm_instArgs{arm_arg_R1
_12, arm_arg_R2_12, arm_arg_mem_R_pm_R_W}}, // LDRD<c> <Rt1>,<Rt2
>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|0|1|Rm:
4 |
8057 {0x0e5000f0, 0x004000d0, 2, arm_LDRD_EQ, 0x1c04, arm_instArgs{arm_arg_R1
_12, arm_arg_R2_12, arm_arg_mem_R_pm_imm8_W}}, // LDRD<c> <Rt1>,<Rt2>,[
<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|0|Rn:4|Rt:4|imm4H:4|1|1|0|1|imm4L:4 | 10535 {0x0e5000f0, 0x004000d0, 2, arm_LDRD_EQ, 0x1c04, arm_instArgs{arm_arg_R1
_12, arm_arg_R2_12, arm_arg_mem_R_pm_imm8_W}}, // LDRD<c> <Rt1>,<Rt2
>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|0|Rn:4|Rt:4|imm4H:4|1|1|0|1|imm4L:
4 |
8058 {0x0ff00fff, 0x01900f9f, 4, arm_LDREX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R}}, // LDREX<c> <Rt>,[<Rn>]
cond:4|0|0|0|1|1|0|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) | 10536 {0x0ff00fff, 0x01900f9f, 4, arm_LDREX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R}}, // LDREX<c> <Rt>,[<Rn
>] cond:4|0|0|0|1|1|0|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) |
8059 {0x0ff000f0, 0x01900f9f, 3, arm_LDREX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R}}, // LDREX<c> <Rt>,[<Rn>]
cond:4|0|0|0|1|1|0|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) | 10537 {0x0ff000f0, 0x01900f9f, 3, arm_LDREX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R}}, // LDREX<c> <Rt>,[<Rn
>] cond:4|0|0|0|1|1|0|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) |
8060 {0x0ff00fff, 0x01d00f9f, 4, arm_LDREXB_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_mem_R}}, // LDREXB<c> <Rt>, [<Rn>
] cond:4|0|0|0|1|1|1|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) | 10538 {0x0ff00fff, 0x01d00f9f, 4, arm_LDREXB_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_mem_R}}, // LDREXB<c> <Rt>, [<
Rn>] cond:4|0|0|0|1|1|1|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) |
8061 {0x0ff000f0, 0x01d00f9f, 3, arm_LDREXB_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_mem_R}}, // LDREXB<c> <Rt>, [<Rn>
] cond:4|0|0|0|1|1|1|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) | 10539 {0x0ff000f0, 0x01d00f9f, 3, arm_LDREXB_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_mem_R}}, // LDREXB<c> <Rt>, [<
Rn>] cond:4|0|0|0|1|1|1|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) |
8062 {0x0ff00fff, 0x01b00f9f, 4, arm_LDREXD_EQ, 0x1c04, arm_instArgs{arm_arg_
R1_12, arm_arg_R2_12, arm_arg_mem_R}}, // LDREXD<c> <Rt1>,<Rt2>
,[<Rn>] cond:4|0|0|0|1|1|0|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) | 10540 {0x0ff00fff, 0x01b00f9f, 4, arm_LDREXD_EQ, 0x1c04, arm_instArgs{arm_arg_
R1_12, arm_arg_R2_12, arm_arg_mem_R}}, // LDREXD<c> <Rt1>,<R
t2>,[<Rn>] cond:4|0|0|0|1|1|0|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|
(1) |
8063 {0x0ff000f0, 0x01b00f9f, 3, arm_LDREXD_EQ, 0x1c04, arm_instArgs{arm_arg_
R1_12, arm_arg_R2_12, arm_arg_mem_R}}, // LDREXD<c> <Rt1>,<Rt2>
,[<Rn>] cond:4|0|0|0|1|1|0|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) | 10541 {0x0ff000f0, 0x01b00f9f, 3, arm_LDREXD_EQ, 0x1c04, arm_instArgs{arm_arg_
R1_12, arm_arg_R2_12, arm_arg_mem_R}}, // LDREXD<c> <Rt1>,<R
t2>,[<Rn>] cond:4|0|0|0|1|1|0|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|
(1) |
8064 {0x0ff00fff, 0x01f00f9f, 4, arm_LDREXH_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_mem_R}}, // LDREXH<c> <Rt>, [<Rn>
] cond:4|0|0|0|1|1|1|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) | 10542 {0x0ff00fff, 0x01f00f9f, 4, arm_LDREXH_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_mem_R}}, // LDREXH<c> <Rt>, [<
Rn>] cond:4|0|0|0|1|1|1|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) |
8065 {0x0ff000f0, 0x01f00f9f, 3, arm_LDREXH_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_mem_R}}, // LDREXH<c> <Rt>, [<Rn>
] cond:4|0|0|0|1|1|1|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) | 10543 {0x0ff000f0, 0x01f00f9f, 3, arm_LDREXH_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_mem_R}}, // LDREXH<c> <Rt>, [<
Rn>] cond:4|0|0|0|1|1|1|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) |
8066 {0x0e500ff0, 0x001000b0, 2, arm_LDRH_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_R_W}}, // LDRH<c> <Rt>,[<Rn>,+/
-<Rm>]{!} cond:4|0|0|0|P|U|0|W|1|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4 | 10544 {0x0e500ff0, 0x001000b0, 2, arm_LDRH_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_R_W}}, // LDRH<c> <Rt>,[<Rn>
,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|1|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4 |
8067 {0x0e5000f0, 0x005000b0, 2, arm_LDRH_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_imm8_W}}, // LDRH<c> <Rt>,[<Rn>{,#
+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|1|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4 | 10545 {0x0e5000f0, 0x005000b0, 2, arm_LDRH_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_imm8_W}}, // LDRH<c> <Rt>,[<Rn>
{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|1|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4 |
8068 {0x0f7000f0, 0x007000b0, 4, arm_LDRHT_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_imm8_postindex}}, // LDRHT<c> <Rt>, [<Rn>]
{,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|1|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4 | 10546 {0x0f7000f0, 0x007000b0, 4, arm_LDRHT_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_imm8_postindex}}, // LDRHT<c> <Rt>, [<R
n>] {,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|1|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4 |
8069 {0x0f700ff0, 0x003000b0, 4, arm_LDRHT_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_R_postindex}}, // LDRHT<c> <Rt>, [<Rn>]
, +/-<Rm> cond:4|0|0|0|0|U|0|1|1|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4 | 10547 {0x0f700ff0, 0x003000b0, 4, arm_LDRHT_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_R_postindex}}, // LDRHT<c> <Rt>, [<R
n>], +/-<Rm> cond:4|0|0|0|0|U|0|1|1|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4 |
8070 {0x0e500ff0, 0x001000d0, 2, arm_LDRSB_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_R_W}}, // LDRSB<c> <Rt>,[<Rn>,+
/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|1|Rn:4|Rt:4|0|0|0|0|1|1|0|1|Rm:4 | 10548 {0x0e500ff0, 0x001000d0, 2, arm_LDRSB_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_R_W}}, // LDRSB<c> <Rt>,[<Rn
>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|1|Rn:4|Rt:4|0|0|0|0|1|1|0|1|Rm:4 |
8071 {0x0e5000f0, 0x005000d0, 2, arm_LDRSB_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_imm8_W}}, // LDRSB<c> <Rt>,[<Rn>{,
#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|1|Rn:4|Rt:4|imm4H:4|1|1|0|1|imm4L:4 | 10549 {0x0e5000f0, 0x005000d0, 2, arm_LDRSB_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_imm8_W}}, // LDRSB<c> <Rt>,[<Rn
>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|1|Rn:4|Rt:4|imm4H:4|1|1|0|1|imm4L:4 |
8072 {0x0f7000f0, 0x007000d0, 4, arm_LDRSBT_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_mem_R_pm_imm8_postindex}}, // LDRSBT<c> <Rt>, [<Rn>
] {,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|1|Rn:4|Rt:4|imm4H:4|1|1|0|1|imm4L:4 | 10550 {0x0f7000f0, 0x007000d0, 4, arm_LDRSBT_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_mem_R_pm_imm8_postindex}}, // LDRSBT<c> <Rt>, [<
Rn>] {,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|1|Rn:4|Rt:4|imm4H:4|1|1|0|1|imm4L:4 |
8073 {0x0f700ff0, 0x003000d0, 4, arm_LDRSBT_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_mem_R_pm_R_postindex}}, // LDRSBT<c> <Rt>, [<Rn>
], +/-<Rm> cond:4|0|0|0|0|U|0|1|1|Rn:4|Rt:4|0|0|0|0|1|1|0|1|Rm:4 | 10551 {0x0f700ff0, 0x003000d0, 4, arm_LDRSBT_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_mem_R_pm_R_postindex}}, // LDRSBT<c> <Rt>, [<
Rn>], +/-<Rm> cond:4|0|0|0|0|U|0|1|1|Rn:4|Rt:4|0|0|0|0|1|1|0|1|Rm:4 |
8074 {0x0e500ff0, 0x001000f0, 2, arm_LDRSH_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_R_W}}, // LDRSH<c> <Rt>,[<Rn>,+
/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|1|Rn:4|Rt:4|0|0|0|0|1|1|1|1|Rm:4 | 10552 {0x0e500ff0, 0x001000f0, 2, arm_LDRSH_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_R_W}}, // LDRSH<c> <Rt>,[<Rn
>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|1|Rn:4|Rt:4|0|0|0|0|1|1|1|1|Rm:4 |
8075 {0x0e5000f0, 0x005000f0, 2, arm_LDRSH_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_imm8_W}}, // LDRSH<c> <Rt>,[<Rn>{,
#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|1|Rn:4|Rt:4|imm4H:4|1|1|1|1|imm4L:4 | 10553 {0x0e5000f0, 0x005000f0, 2, arm_LDRSH_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_imm8_W}}, // LDRSH<c> <Rt>,[<Rn
>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|1|Rn:4|Rt:4|imm4H:4|1|1|1|1|imm4L:4 |
8076 {0x0f7000f0, 0x007000f0, 4, arm_LDRSHT_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_mem_R_pm_imm8_postindex}}, // LDRSHT<c> <Rt>, [<Rn>
] {,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|1|Rn:4|Rt:4|imm4H:4|1|1|1|1|imm4L:4 | 10554 {0x0f7000f0, 0x007000f0, 4, arm_LDRSHT_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_mem_R_pm_imm8_postindex}}, // LDRSHT<c> <Rt>, [<
Rn>] {,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|1|Rn:4|Rt:4|imm4H:4|1|1|1|1|imm4L:4 |
8077 {0x0f700ff0, 0x003000f0, 4, arm_LDRSHT_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_mem_R_pm_R_postindex}}, // LDRSHT<c> <Rt>, [<Rn>
], +/-<Rm> cond:4|0|0|0|0|U|0|1|1|Rn:4|Rt:4|0|0|0|0|1|1|1|1|Rm:4 | 10555 {0x0f700ff0, 0x003000f0, 4, arm_LDRSHT_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_mem_R_pm_R_postindex}}, // LDRSHT<c> <Rt>, [<
Rn>], +/-<Rm> cond:4|0|0|0|0|U|0|1|1|Rn:4|Rt:4|0|0|0|0|1|1|1|1|Rm:4 |
8078 {0x0f700000, 0x04300000, 4, arm_LDRT_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_imm12_postindex}}, // LDRT<c> <Rt>, [<Rn>]
{,#+/-<imm12>} cond:4|0|1|0|0|U|0|1|1|Rn:4|Rt:4|imm12:12 | 10556 {0x0f700000, 0x04300000, 4, arm_LDRT_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_imm12_postindex}}, // LDRT<c> <Rt>, [<Rn
>] {,#+/-<imm12>} cond:4|0|1|0|0|U|0|1|1|Rn:4|Rt:4|imm12:12 |
8079 {0x0f700010, 0x06300000, 4, arm_LDRT_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_R_shift_imm_postindex}}, // LDRT<c> <Rt>,[<Rn>],+
/-<Rm>{, <shift>} cond:4|0|1|1|0|U|0|1|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 | 10557 {0x0f700010, 0x06300000, 4, arm_LDRT_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_R_shift_imm_postindex}}, // LDRT<c> <Rt>,[<Rn>
],+/-<Rm>{, <shift>} cond:4|0|1|1|0|U|0|1|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 |
8080 {0x0fef0070, 0x01a00000, 2, arm_LSL_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_0, arm_arg_imm5_nz}}, // LSL{S}<c> <Rd>,<Rm>,#
<imm5_nz> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|0|0|0|Rm:4 | 10558 {0x0fef0070, 0x01a00000, 2, arm_LSL_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_0, arm_arg_imm5_nz}}, // LSL{S}<c> <Rd>,<Rm
>,#<imm5_nz> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|0|0|0|Rm:4 |
8081 {0x0fef00f0, 0x01a00010, 4, arm_LSL_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_0, arm_arg_R_8}}, // LSL{S}<c> <Rd>,<Rn>,<
Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|0|0|1|Rn:4 | 10559 {0x0fef00f0, 0x01a00010, 4, arm_LSL_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_0, arm_arg_R_8}}, // LSL{S}<c> <Rd>,<Rn
>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|0|0|1|Rn:4 |
8082 {0x0fef0070, 0x01a00020, 4, arm_LSR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_0, arm_arg_imm5_32}}, // LSR{S}<c> <Rd>,<Rm>,#
<imm5_32> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|0|1|0|Rm:4 | 10560 {0x0fef0070, 0x01a00020, 4, arm_LSR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_0, arm_arg_imm5_32}}, // LSR{S}<c> <Rd>,<Rm
>,#<imm5_32> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|0|1|0|Rm:4 |
8083 {0x0fef00f0, 0x01a00030, 4, arm_LSR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_0, arm_arg_R_8}}, // LSR{S}<c> <Rd>,<Rn>,<
Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|0|1|1|Rn:4 | 10561 {0x0fef00f0, 0x01a00030, 4, arm_LSR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_0, arm_arg_R_8}}, // LSR{S}<c> <Rd>,<Rn
>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|0|1|1|Rn:4 |
8084 {0x0fe000f0, 0x00200090, 4, arm_MLA_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // MLA{S}<c> <Rd>,<Rn>,<
Rm>,<Ra> cond:4|0|0|0|0|0|0|1|S|Rd:4|Ra:4|Rm:4|1|0|0|1|Rn:4 | 10562 {0x0fe000f0, 0x00200090, 4, arm_MLA_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // MLA{S}<c> <Rd>,<Rn
>,<Rm>,<Ra> cond:4|0|0|0|0|0|0|1|S|Rd:4|Ra:4|Rm:4|1|0|0|1|Rn:4 |
8085 {0x0ff000f0, 0x00600090, 4, arm_MLS_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // MLS<c> <Rd>,<Rn>,<Rm>
,<Ra> cond:4|0|0|0|0|0|1|1|0|Rd:4|Ra:4|Rm:4|1|0|0|1|Rn:4 | 10563 {0x0ff000f0, 0x00600090, 4, arm_MLS_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // MLS<c> <Rd>,<Rn>,<
Rm>,<Ra> cond:4|0|0|0|0|0|1|1|0|Rd:4|Ra:4|Rm:4|1|0|0|1|Rn:4 |
8086 {0x0ff00000, 0x03400000, 4, arm_MOVT_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_imm_4at16_12at0}}, // MOVT<c> <Rd>,#<imm12+
4> cond:4|0|0|1|1|0|1|0|0|imm4:4|Rd:4|imm12:12 | 10564 {0x0ff00000, 0x03400000, 4, arm_MOVT_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_imm_4at16_12at0}}, // MOVT<c> <Rd>,#<imm
12+4> cond:4|0|0|1|1|0|1|0|0|imm4:4|Rd:4|imm12:12 |
8087 {0x0ff00000, 0x03000000, 4, arm_MOVW_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_imm_4at16_12at0}}, // MOVW<c> <Rd>,#<imm12+
4> cond:4|0|0|1|1|0|0|0|0|imm4:4|Rd:4|imm12:12 | 10565 {0x0ff00000, 0x03000000, 4, arm_MOVW_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_imm_4at16_12at0}}, // MOVW<c> <Rd>,#<imm
12+4> cond:4|0|0|1|1|0|0|0|0|imm4:4|Rd:4|imm12:12 |
8088 {0x0fef0000, 0x03a00000, 2, arm_MOV_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_const}}, // MOV{S}<c> <Rd>,#<cons
t> cond:4|0|0|1|1|1|0|1|S|0|0|0|0|Rd:4|imm12:12 | 10566 {0x0fef0000, 0x03a00000, 2, arm_MOV_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_const}}, // MOV{S}<c> <Rd>,#<c
onst> cond:4|0|0|1|1|1|0|1|S|0|0|0|0|Rd:4|imm12:12 |
8089 {0x0fef0ff0, 0x01a00000, 2, arm_MOV_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_0}}, // MOV{S}<c> <Rd>,<Rm> c
ond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|0|0|0|0|0|0|0|0|Rm:4 | 10567 {0x0fef0ff0, 0x01a00000, 2, arm_MOV_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_0}}, // MOV{S}<c> <Rd>,<Rm
> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|0|0|0|0|0|0|0|0|Rm:4 |
8090 {0x0fff0fff, 0x010f0000, 4, arm_MRS_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_APSR}}, // MRS<c> <Rd>,APSR cond
:4|0|0|0|1|0|0|0|0|(1)|(1)|(1)|(1)|Rd:4|(0)|(0)|(0)|(0)|0|0|0|0|(0)|(0)|(0)|(0) | 10568 {0x0fff0fff, 0x010f0000, 4, arm_MRS_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_APSR}}, // MRS<c> <Rd>,APSR c
ond:4|0|0|0|1|0|0|0|0|(1)|(1)|(1)|(1)|Rd:4|(0)|(0)|(0)|(0)|0|0|0|0|(0)|(0)|(0)|(
0) |
8091 {0x0ff000f0, 0x010f0000, 3, arm_MRS_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_APSR}}, // MRS<c> <Rd>,APSR cond
:4|0|0|0|1|0|0|0|0|(1)|(1)|(1)|(1)|Rd:4|(0)|(0)|(0)|(0)|0|0|0|0|(0)|(0)|(0)|(0) | 10569 {0x0ff000f0, 0x010f0000, 3, arm_MRS_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_APSR}}, // MRS<c> <Rd>,APSR c
ond:4|0|0|0|1|0|0|0|0|(1)|(1)|(1)|(1)|Rd:4|(0)|(0)|(0)|(0)|0|0|0|0|(0)|(0)|(0)|(
0) |
8092 {0x0fe0f0f0, 0x00000090, 4, arm_MUL_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_16, arm_arg_R_0, arm_arg_R_8}}, // MUL{S}<c> <Rd>,<Rn>,<
Rm> cond:4|0|0|0|0|0|0|0|S|Rd:4|(0)|(0)|(0)|(0)|Rm:4|1|0|0|1|Rn:4 | 10570 {0x0fe0f0f0, 0x00000090, 4, arm_MUL_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_16, arm_arg_R_0, arm_arg_R_8}}, // MUL{S}<c> <Rd>,<Rn
>,<Rm> cond:4|0|0|0|0|0|0|0|S|Rd:4|(0)|(0)|(0)|(0)|Rm:4|1|0|0|1|Rn:4 |
8093 {0x0fe000f0, 0x00000090, 3, arm_MUL_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_16, arm_arg_R_0, arm_arg_R_8}}, // MUL{S}<c> <Rd>,<Rn>,<
Rm> cond:4|0|0|0|0|0|0|0|S|Rd:4|(0)|(0)|(0)|(0)|Rm:4|1|0|0|1|Rn:4 | 10571 {0x0fe000f0, 0x00000090, 3, arm_MUL_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_16, arm_arg_R_0, arm_arg_R_8}}, // MUL{S}<c> <Rd>,<Rn
>,<Rm> cond:4|0|0|0|0|0|0|0|S|Rd:4|(0)|(0)|(0)|(0)|Rm:4|1|0|0|1|Rn:4 |
8094 {0x0fef0000, 0x03e00000, 2, arm_MVN_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_const}}, // MVN{S}<c> <Rd>,#<cons
t> cond:4|0|0|1|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm12:12 | 10572 {0x0fef0000, 0x03e00000, 2, arm_MVN_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_const}}, // MVN{S}<c> <Rd>,#<c
onst> cond:4|0|0|1|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm12:12 |
8095 {0x0fe00000, 0x03e00000, 1, arm_MVN_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_const}}, // MVN{S}<c> <Rd>,#<cons
t> cond:4|0|0|1|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm12:12 | 10573 {0x0fe00000, 0x03e00000, 1, arm_MVN_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_const}}, // MVN{S}<c> <Rd>,#<c
onst> cond:4|0|0|1|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm12:12 |
8096 {0x0fef0090, 0x01e00010, 4, arm_MVN_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_shift_R}}, // MVN{S}<c> <Rd>,<Rm>,<
type> <Rs> cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|Rs:4|0|type:2|1|Rm:4 | 10574 {0x0fef0090, 0x01e00010, 4, arm_MVN_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_shift_R}}, // MVN{S}<c> <Rd>,<Rm
>,<type> <Rs> cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|Rs:4|0|type:2|1|Rm:4 |
8097 {0x0fe00090, 0x01e00010, 3, arm_MVN_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_shift_R}}, // MVN{S}<c> <Rd>,<Rm>,<
type> <Rs> cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|Rs:4|0|type:2|1|Rm:4 | 10575 {0x0fe00090, 0x01e00010, 3, arm_MVN_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_shift_R}}, // MVN{S}<c> <Rd>,<Rm
>,<type> <Rs> cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|Rs:4|0|type:2|1|Rm:4 |
8098 {0x0fef0010, 0x01e00000, 2, arm_MVN_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_shift_imm}}, // MVN{S}<c> <Rd>,<Rm>{,
<shift>} cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm5:5|type:2|0|Rm:4 | 10576 {0x0fef0010, 0x01e00000, 2, arm_MVN_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_shift_imm}}, // MVN{S}<c> <Rd>,<Rm
>{,<shift>} cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm5:5|type:2|0|Rm:4 |
8099 {0x0fe00010, 0x01e00000, 1, arm_MVN_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_shift_imm}}, // MVN{S}<c> <Rd>,<Rm>{,
<shift>} cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm5:5|type:2|0|Rm:4 | 10577 {0x0fe00010, 0x01e00000, 1, arm_MVN_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_shift_imm}}, // MVN{S}<c> <Rd>,<Rm
>{,<shift>} cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm5:5|type:2|0|Rm:4 |
8100 {0x0fffffff, 0x0320f000, 4, arm_NOP_EQ, 0x1c04, arm_instArgs{}},
// NOP<c> cond:4|0|0|1|1
|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|0 | 10578 {0x0fffffff, 0x0320f000, 4, arm_NOP_EQ, 0x1c04, arm_instArgs{}},
// NOP<c> cond:4|0|0|
1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|0 |
8101 {0x0fff00ff, 0x0320f000, 3, arm_NOP_EQ, 0x1c04, arm_instArgs{}},
// NOP<c> cond:4|0|0|1|1
|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|0 | 10579 {0x0fff00ff, 0x0320f000, 3, arm_NOP_EQ, 0x1c04, arm_instArgs{}},
// NOP<c> cond:4|0|0|
1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|0 |
8102 {0x0fe00000, 0x03800000, 2, arm_ORR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_const}}, // ORR{S}<c> <Rd>,<Rn>,#
<const> cond:4|0|0|1|1|1|0|0|S|Rn:4|Rd:4|imm12:12 | 10580 {0x0fe00000, 0x03800000, 2, arm_ORR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_const}}, // ORR{S}<c> <Rd>,<Rn
>,#<const> cond:4|0|0|1|1|1|0|0|S|Rn:4|Rd:4|imm12:12 |
8103 {0x0fe00090, 0x01800010, 4, arm_ORR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // ORR{S}<c> <Rd>,<Rn>,<
Rm>,<type> <Rs> cond:4|0|0|0|1|1|0|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 | 10581 {0x0fe00090, 0x01800010, 4, arm_ORR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // ORR{S}<c> <Rd>,<Rn
>,<Rm>,<type> <Rs> cond:4|0|0|0|1|1|0|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 |
8104 {0x0fe00010, 0x01800000, 2, arm_ORR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // ORR{S}<c> <Rd>,<Rn>,<
Rm>{,<shift>} cond:4|0|0|0|1|1|0|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 | 10582 {0x0fe00010, 0x01800000, 2, arm_ORR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // ORR{S}<c> <Rd>,<Rn
>,<Rm>{,<shift>} cond:4|0|0|0|1|1|0|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 |
8105 {0x0ff00030, 0x06800010, 4, arm_PKHBT_EQ, 0x6011c04, arm_instArgs{arm_ar
g_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // PKH<BT,TB><c> <Rd>,<R
n>,<Rm>{,LSL #<imm5>} cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|imm5:5|tb|0|1|Rm:4 | 10583 {0x0ff00030, 0x06800010, 4, arm_PKHBT_EQ, 0x6011c04, arm_instArgs{arm_ar
g_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // PKH<BT,TB><c> <Rd>
,<Rn>,<Rm>{,LSL #<imm5>} cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|imm5:5|tb|0|1|Rm:4 |
8106 {0xff7ff000, 0xf55ff000, 4, arm_PLD, 0x0, arm_instArgs{arm_arg_label_pm_
12}}, // PLD <label+/-12> 1|1|
1|1|0|1|0|1|U|(1)|0|1|1|1|1|1|(1)|(1)|(1)|(1)|imm12:12 | 10584 {0xff7ff000, 0xf55ff000, 4, arm_PLD, 0x0, arm_instArgs{arm_arg_label_pm_
12}}, // PLD <label+/-12> 1
|1|1|1|0|1|0|1|U|(1)|0|1|1|1|1|1|(1)|(1)|(1)|(1)|imm12:12 |
8107 {0xff3f0000, 0xf55ff000, 3, arm_PLD, 0x0, arm_instArgs{arm_arg_label_pm_
12}}, // PLD <label+/-12> 1|1|
1|1|0|1|0|1|U|(1)|0|1|1|1|1|1|(1)|(1)|(1)|(1)|imm12:12 | 10585 {0xff3f0000, 0xf55ff000, 3, arm_PLD, 0x0, arm_instArgs{arm_arg_label_pm_
12}}, // PLD <label+/-12> 1
|1|1|1|0|1|0|1|U|(1)|0|1|1|1|1|1|(1)|(1)|(1)|(1)|imm12:12 |
8108 {0xff30f000, 0xf510f000, 2, arm_PLD_W, 0x1601, arm_instArgs{arm_arg_mem_
R_pm_imm12_offset}}, // PLD{W} [<Rn>,#+/-<imm
12>] 1|1|1|1|0|1|0|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12 | 10586 {0xff30f000, 0xf510f000, 2, arm_PLD_W, 0x1601, arm_instArgs{arm_arg_mem_
R_pm_imm12_offset}}, // PLD{W} [<Rn>,#+/-<
imm12>] 1|1|1|1|0|1|0|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12 |
8109 {0xff300000, 0xf510f000, 1, arm_PLD_W, 0x1601, arm_instArgs{arm_arg_mem_
R_pm_imm12_offset}}, // PLD{W} [<Rn>,#+/-<imm
12>] 1|1|1|1|0|1|0|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12 | 10587 {0xff300000, 0xf510f000, 1, arm_PLD_W, 0x1601, arm_instArgs{arm_arg_mem_
R_pm_imm12_offset}}, // PLD{W} [<Rn>,#+/-<
imm12>] 1|1|1|1|0|1|0|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12 |
8110 {0xff30f010, 0xf710f000, 4, arm_PLD_W, 0x1601, arm_instArgs{arm_arg_mem_
R_pm_R_shift_imm_offset}}, // PLD{W} [<Rn>,+/-<Rm>{
, <shift>}] 1|1|1|1|0|1|1|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4 | 10588 {0xff30f010, 0xf710f000, 4, arm_PLD_W, 0x1601, arm_instArgs{arm_arg_mem_
R_pm_R_shift_imm_offset}}, // PLD{W} [<Rn>,+/-<R
m>{, <shift>}] 1|1|1|1|0|1|1|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4 |
8111 {0xff300010, 0xf710f000, 3, arm_PLD_W, 0x1601, arm_instArgs{arm_arg_mem_
R_pm_R_shift_imm_offset}}, // PLD{W} [<Rn>,+/-<Rm>{
, <shift>}] 1|1|1|1|0|1|1|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4 | 10589 {0xff300010, 0xf710f000, 3, arm_PLD_W, 0x1601, arm_instArgs{arm_arg_mem_
R_pm_R_shift_imm_offset}}, // PLD{W} [<Rn>,+/-<R
m>{, <shift>}] 1|1|1|1|0|1|1|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4 |
8112 {0xff70f000, 0xf450f000, 4, arm_PLI, 0x0, arm_instArgs{arm_arg_mem_R_pm_
imm12_offset}}, // PLI [<Rn>,#+/-<imm12>
] 1|1|1|1|0|1|0|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12 | 10590 {0xff70f000, 0xf450f000, 4, arm_PLI, 0x0, arm_instArgs{arm_arg_mem_R_pm_
imm12_offset}}, // PLI [<Rn>,#+/-<imm
12>] 1|1|1|1|0|1|0|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12 |
8113 {0xff700000, 0xf450f000, 3, arm_PLI, 0x0, arm_instArgs{arm_arg_mem_R_pm_
imm12_offset}}, // PLI [<Rn>,#+/-<imm12>
] 1|1|1|1|0|1|0|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12 | 10591 {0xff700000, 0xf450f000, 3, arm_PLI, 0x0, arm_instArgs{arm_arg_mem_R_pm_
imm12_offset}}, // PLI [<Rn>,#+/-<imm
12>] 1|1|1|1|0|1|0|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12 |
8114 {0xff70f010, 0xf650f000, 4, arm_PLI, 0x0, arm_instArgs{arm_arg_mem_R_pm_
R_shift_imm_offset}}, // PLI [<Rn>,+/-<Rm>{, <
shift>}] 1|1|1|1|0|1|1|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4 | 10592 {0xff70f010, 0xf650f000, 4, arm_PLI, 0x0, arm_instArgs{arm_arg_mem_R_pm_
R_shift_imm_offset}}, // PLI [<Rn>,+/-<Rm>{
, <shift>}] 1|1|1|1|0|1|1|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4 |
8115 {0xff700010, 0xf650f000, 3, arm_PLI, 0x0, arm_instArgs{arm_arg_mem_R_pm_
R_shift_imm_offset}}, // PLI [<Rn>,+/-<Rm>{, <
shift>}] 1|1|1|1|0|1|1|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4 | 10593 {0xff700010, 0xf650f000, 3, arm_PLI, 0x0, arm_instArgs{arm_arg_mem_R_pm_
R_shift_imm_offset}}, // PLI [<Rn>,+/-<Rm>{
, <shift>}] 1|1|1|1|0|1|1|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4 |
8116 {0x0fff0000, 0x08bd0000, 4, arm_POP_EQ, 0x1c04, arm_instArgs{arm_arg_reg
isters2}}, // POP<c> <registers2> c
ond:4|1|0|0|0|1|0|1|1|1|1|0|1|register_list:16 | 10594 {0x0fff0000, 0x08bd0000, 4, arm_POP_EQ, 0x1c04, arm_instArgs{arm_arg_reg
isters2}}, // POP<c> <registers2
> cond:4|1|0|0|0|1|0|1|1|1|1|0|1|register_list:16 |
8117 {0x0fff0fff, 0x049d0004, 4, arm_POP_EQ, 0x1c04, arm_instArgs{arm_arg_reg
isters1}}, // POP<c> <registers1> c
ond:4|0|1|0|0|1|0|0|1|1|1|0|1|Rt:4|0|0|0|0|0|0|0|0|0|1|0|0 | 10595 {0x0fff0fff, 0x049d0004, 4, arm_POP_EQ, 0x1c04, arm_instArgs{arm_arg_reg
isters1}}, // POP<c> <registers1
> cond:4|0|1|0|0|1|0|0|1|1|1|0|1|Rt:4|0|0|0|0|0|0|0|0|0|1|0|0 |
8118 {0x0fff0000, 0x092d0000, 4, arm_PUSH_EQ, 0x1c04, arm_instArgs{arm_arg_re
gisters2}}, // PUSH<c> <registers2>
cond:4|1|0|0|1|0|0|1|0|1|1|0|1|register_list:16 | 10596 {0x0fff0000, 0x092d0000, 4, arm_PUSH_EQ, 0x1c04, arm_instArgs{arm_arg_re
gisters2}}, // PUSH<c> <registers
2> cond:4|1|0|0|1|0|0|1|0|1|1|0|1|register_list:16 |
8119 {0x0fff0fff, 0x052d0004, 4, arm_PUSH_EQ, 0x1c04, arm_instArgs{arm_arg_re
gisters1}}, // PUSH<c> <registers1>
cond:4|0|1|0|1|0|0|1|0|1|1|0|1|Rt:4|0|0|0|0|0|0|0|0|0|1|0|0 | 10597 {0x0fff0fff, 0x052d0004, 4, arm_PUSH_EQ, 0x1c04, arm_instArgs{arm_arg_re
gisters1}}, // PUSH<c> <registers
1> cond:4|0|1|0|1|0|0|1|0|1|1|0|1|Rt:4|0|0|0|0|0|0|0|0|0|1|0|0 |
8120 {0x0ff00ff0, 0x06200f10, 4, arm_QADD16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // QADD16<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 | 10598 {0x0ff00ff0, 0x06200f10, 4, arm_QADD16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // QADD16<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 |
8121 {0x0ff000f0, 0x06200f10, 3, arm_QADD16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // QADD16<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 | 10599 {0x0ff000f0, 0x06200f10, 3, arm_QADD16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // QADD16<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 |
8122 {0x0ff00ff0, 0x06200f90, 4, arm_QADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // QADD8<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 | 10600 {0x0ff00ff0, 0x06200f90, 4, arm_QADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // QADD8<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 |
8123 {0x0ff000f0, 0x06200f90, 3, arm_QADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // QADD8<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 | 10601 {0x0ff000f0, 0x06200f90, 3, arm_QADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // QADD8<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 |
8124 {0x0ff00ff0, 0x01000050, 4, arm_QADD_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_0, arm_arg_R_16}}, // QADD<c> <Rd>,<Rm>,<Rn
> cond:4|0|0|0|1|0|0|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4 | 10602 {0x0ff00ff0, 0x01000050, 4, arm_QADD_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_0, arm_arg_R_16}}, // QADD<c> <Rd>,<Rm>,
<Rn> cond:4|0|0|0|1|0|0|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4 |
8125 {0x0ff000f0, 0x01000050, 3, arm_QADD_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_0, arm_arg_R_16}}, // QADD<c> <Rd>,<Rm>,<Rn
> cond:4|0|0|0|1|0|0|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4 | 10603 {0x0ff000f0, 0x01000050, 3, arm_QADD_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_0, arm_arg_R_16}}, // QADD<c> <Rd>,<Rm>,
<Rn> cond:4|0|0|0|1|0|0|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4 |
8126 {0x0ff00ff0, 0x06200f30, 4, arm_QASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // QASX<c> <Rd>,<Rn>,<Rm
> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 | 10604 {0x0ff00ff0, 0x06200f30, 4, arm_QASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // QASX<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 |
8127 {0x0ff000f0, 0x06200f30, 3, arm_QASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // QASX<c> <Rd>,<Rn>,<Rm
> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 | 10605 {0x0ff000f0, 0x06200f30, 3, arm_QASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // QASX<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 |
8128 {0x0ff00ff0, 0x01400050, 4, arm_QDADD_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_0, arm_arg_R_16}}, // QDADD<c> <Rd>,<Rm>,<R
n> cond:4|0|0|0|1|0|1|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4 | 10606 {0x0ff00ff0, 0x01400050, 4, arm_QDADD_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_0, arm_arg_R_16}}, // QDADD<c> <Rd>,<Rm>
,<Rn> cond:4|0|0|0|1|0|1|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4 |
8129 {0x0ff000f0, 0x01400050, 3, arm_QDADD_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_0, arm_arg_R_16}}, // QDADD<c> <Rd>,<Rm>,<R
n> cond:4|0|0|0|1|0|1|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4 | 10607 {0x0ff000f0, 0x01400050, 3, arm_QDADD_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_0, arm_arg_R_16}}, // QDADD<c> <Rd>,<Rm>
,<Rn> cond:4|0|0|0|1|0|1|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4 |
8130 {0x0ff00ff0, 0x01600050, 4, arm_QDSUB_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_0, arm_arg_R_16}}, // QDSUB<c> <Rd>,<Rm>,<R
n> cond:4|0|0|0|1|0|1|1|0|Rn:4|Rd:4|0|0|0|0|0|1|0|1|Rm:4 | 10608 {0x0ff00ff0, 0x01600050, 4, arm_QDSUB_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_0, arm_arg_R_16}}, // QDSUB<c> <Rd>,<Rm>
,<Rn> cond:4|0|0|0|1|0|1|1|0|Rn:4|Rd:4|0|0|0|0|0|1|0|1|Rm:4 |
8131 {0x0ff00ff0, 0x06200f50, 4, arm_QSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // QSAX<c> <Rd>,<Rn>,<Rm
> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 | 10609 {0x0ff00ff0, 0x06200f50, 4, arm_QSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // QSAX<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 |
8132 {0x0ff000f0, 0x06200f50, 3, arm_QSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // QSAX<c> <Rd>,<Rn>,<Rm
> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 | 10610 {0x0ff000f0, 0x06200f50, 3, arm_QSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // QSAX<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 |
8133 {0x0ff00ff0, 0x06200f70, 4, arm_QSUB16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // QSUB16<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 | 10611 {0x0ff00ff0, 0x06200f70, 4, arm_QSUB16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // QSUB16<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 |
8134 {0x0ff000f0, 0x06200f70, 3, arm_QSUB16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // QSUB16<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 | 10612 {0x0ff000f0, 0x06200f70, 3, arm_QSUB16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // QSUB16<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 |
8135 {0x0ff00ff0, 0x06200ff0, 4, arm_QSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // QSUB8<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 | 10613 {0x0ff00ff0, 0x06200ff0, 4, arm_QSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // QSUB8<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 |
8136 {0x0ff000f0, 0x06200ff0, 3, arm_QSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // QSUB8<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 | 10614 {0x0ff000f0, 0x06200ff0, 3, arm_QSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // QSUB8<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 |
8137 {0x0ff00ff0, 0x01200050, 4, arm_QSUB_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_0, arm_arg_R_16}}, // QSUB<c> <Rd>,<Rm>,<Rn
> cond:4|0|0|0|1|0|0|1|0|Rn:4|Rd:4|0|0|0|0|0|1|0|1|Rm:4 | 10615 {0x0ff00ff0, 0x01200050, 4, arm_QSUB_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_0, arm_arg_R_16}}, // QSUB<c> <Rd>,<Rm>,
<Rn> cond:4|0|0|0|1|0|0|1|0|Rn:4|Rd:4|0|0|0|0|0|1|0|1|Rm:4 |
8138 {0x0fff0ff0, 0x06ff0f30, 4, arm_RBIT_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_0}}, // RBIT<c> <Rd>,<Rm> con
d:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 | 10616 {0x0fff0ff0, 0x06ff0f30, 4, arm_RBIT_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_0}}, // RBIT<c> <Rd>,<Rm>
cond:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 |
8139 {0x0ff000f0, 0x06ff0f30, 3, arm_RBIT_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_0}}, // RBIT<c> <Rd>,<Rm> con
d:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 | 10617 {0x0ff000f0, 0x06ff0f30, 3, arm_RBIT_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_0}}, // RBIT<c> <Rd>,<Rm>
cond:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 |
8140 {0x0fff0ff0, 0x06bf0fb0, 4, arm_REV16_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_0}}, // REV16<c> <Rd>,<Rm> co
nd:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 | 10618 {0x0fff0ff0, 0x06bf0fb0, 4, arm_REV16_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_0}}, // REV16<c> <Rd>,<Rm>
cond:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 |
8141 {0x0ff000f0, 0x06bf0fb0, 3, arm_REV16_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_0}}, // REV16<c> <Rd>,<Rm> co
nd:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 | 10619 {0x0ff000f0, 0x06bf0fb0, 3, arm_REV16_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_0}}, // REV16<c> <Rd>,<Rm>
cond:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 |
8142 {0x0fff0ff0, 0x06bf0f30, 4, arm_REV_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_R_0}}, // REV<c> <Rd>,<Rm> cond
:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 | 10620 {0x0fff0ff0, 0x06bf0f30, 4, arm_REV_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_R_0}}, // REV<c> <Rd>,<Rm> c
ond:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 |
8143 {0x0ff000f0, 0x06bf0f30, 3, arm_REV_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_R_0}}, // REV<c> <Rd>,<Rm> cond
:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 | 10621 {0x0ff000f0, 0x06bf0f30, 3, arm_REV_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_R_0}}, // REV<c> <Rd>,<Rm> c
ond:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 |
8144 {0x0fff0ff0, 0x06ff0fb0, 4, arm_REVSH_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_0}}, // REVSH<c> <Rd>,<Rm> co
nd:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 | 10622 {0x0fff0ff0, 0x06ff0fb0, 4, arm_REVSH_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_0}}, // REVSH<c> <Rd>,<Rm>
cond:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 |
8145 {0x0ff000f0, 0x06ff0fb0, 3, arm_REVSH_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_0}}, // REVSH<c> <Rd>,<Rm> co
nd:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 | 10623 {0x0ff000f0, 0x06ff0fb0, 3, arm_REVSH_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_0}}, // REVSH<c> <Rd>,<Rm>
cond:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 |
8146 {0x0fef0070, 0x01a00060, 2, arm_ROR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_0, arm_arg_imm5}}, // ROR{S}<c> <Rd>,<Rm>,#
<imm5> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|1|1|0|Rm:4 | 10624 {0x0fef0070, 0x01a00060, 2, arm_ROR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_0, arm_arg_imm5}}, // ROR{S}<c> <Rd>,<Rm
>,#<imm5> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|1|1|0|Rm:4 |
8147 {0x0fef00f0, 0x01a00070, 4, arm_ROR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_0, arm_arg_R_8}}, // ROR{S}<c> <Rd>,<Rn>,<
Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|1|1|1|Rn:4 | 10625 {0x0fef00f0, 0x01a00070, 4, arm_ROR_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_0, arm_arg_R_8}}, // ROR{S}<c> <Rd>,<Rn
>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|1|1|1|Rn:4 |
8148 {0x0fef0ff0, 0x01a00060, 4, arm_RRX_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_0}}, // RRX{S}<c> <Rd>,<Rm> c
ond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|0|0|0|0|0|1|1|0|Rm:4 | 10626 {0x0fef0ff0, 0x01a00060, 4, arm_RRX_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_0}}, // RRX{S}<c> <Rd>,<Rm
> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|0|0|0|0|0|1|1|0|Rm:4 |
8149 {0x0fe00000, 0x02600000, 2, arm_RSB_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_const}}, // RSB{S}<c> <Rd>,<Rn>,#
<const> cond:4|0|0|1|0|0|1|1|S|Rn:4|Rd:4|imm12:12 | 10627 {0x0fe00000, 0x02600000, 2, arm_RSB_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_const}}, // RSB{S}<c> <Rd>,<Rn
>,#<const> cond:4|0|0|1|0|0|1|1|S|Rn:4|Rd:4|imm12:12 |
8150 {0x0fe00090, 0x00600010, 4, arm_RSB_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // RSB{S}<c> <Rd>,<Rn>,<
Rm>,<type> <Rs> cond:4|0|0|0|0|0|1|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 | 10628 {0x0fe00090, 0x00600010, 4, arm_RSB_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // RSB{S}<c> <Rd>,<Rn
>,<Rm>,<type> <Rs> cond:4|0|0|0|0|0|1|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 |
8151 {0x0fe00010, 0x00600000, 2, arm_RSB_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // RSB{S}<c> <Rd>,<Rn>,<
Rm>{,<shift>} cond:4|0|0|0|0|0|1|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 | 10629 {0x0fe00010, 0x00600000, 2, arm_RSB_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // RSB{S}<c> <Rd>,<Rn
>,<Rm>{,<shift>} cond:4|0|0|0|0|0|1|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 |
8152 {0x0fe00000, 0x02e00000, 2, arm_RSC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_const}}, // RSC{S}<c> <Rd>,<Rn>,#
<const> cond:4|0|0|1|0|1|1|1|S|Rn:4|Rd:4|imm12:12 | 10630 {0x0fe00000, 0x02e00000, 2, arm_RSC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_const}}, // RSC{S}<c> <Rd>,<Rn
>,#<const> cond:4|0|0|1|0|1|1|1|S|Rn:4|Rd:4|imm12:12 |
8153 {0x0fe00090, 0x00e00010, 4, arm_RSC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // RSC{S}<c> <Rd>,<Rn>,<
Rm>,<type> <Rs> cond:4|0|0|0|0|1|1|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 | 10631 {0x0fe00090, 0x00e00010, 4, arm_RSC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // RSC{S}<c> <Rd>,<Rn
>,<Rm>,<type> <Rs> cond:4|0|0|0|0|1|1|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 |
8154 {0x0fe00010, 0x00e00000, 2, arm_RSC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // RSC{S}<c> <Rd>,<Rn>,<
Rm>{,<shift>} cond:4|0|0|0|0|1|1|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 | 10632 {0x0fe00010, 0x00e00000, 2, arm_RSC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // RSC{S}<c> <Rd>,<Rn
>,<Rm>{,<shift>} cond:4|0|0|0|0|1|1|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 |
8155 {0x0ff00ff0, 0x06100f10, 4, arm_SADD16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // SADD16<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 | 10633 {0x0ff00ff0, 0x06100f10, 4, arm_SADD16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // SADD16<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 |
8156 {0x0ff000f0, 0x06100f10, 3, arm_SADD16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // SADD16<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 | 10634 {0x0ff000f0, 0x06100f10, 3, arm_SADD16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // SADD16<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 |
8157 {0x0ff00ff0, 0x06100f90, 4, arm_SADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // SADD8<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 | 10635 {0x0ff00ff0, 0x06100f90, 4, arm_SADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // SADD8<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 |
8158 {0x0ff000f0, 0x06100f90, 3, arm_SADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // SADD8<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 | 10636 {0x0ff000f0, 0x06100f90, 3, arm_SADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // SADD8<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 |
8159 {0x0ff00ff0, 0x06100f30, 4, arm_SASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // SASX<c> <Rd>,<Rn>,<Rm
> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 | 10637 {0x0ff00ff0, 0x06100f30, 4, arm_SASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // SASX<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 |
8160 {0x0ff000f0, 0x06100f30, 3, arm_SASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // SASX<c> <Rd>,<Rn>,<Rm
> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 | 10638 {0x0ff000f0, 0x06100f30, 3, arm_SASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // SASX<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 |
8161 {0x0fe00000, 0x02c00000, 2, arm_SBC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_const}}, // SBC{S}<c> <Rd>,<Rn>,#
<const> cond:4|0|0|1|0|1|1|0|S|Rn:4|Rd:4|imm12:12 | 10639 {0x0fe00000, 0x02c00000, 2, arm_SBC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_const}}, // SBC{S}<c> <Rd>,<Rn
>,#<const> cond:4|0|0|1|0|1|1|0|S|Rn:4|Rd:4|imm12:12 |
8162 {0x0fe00090, 0x00c00010, 4, arm_SBC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // SBC{S}<c> <Rd>,<Rn>,<
Rm>,<type> <Rs> cond:4|0|0|0|0|1|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 | 10640 {0x0fe00090, 0x00c00010, 4, arm_SBC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // SBC{S}<c> <Rd>,<Rn
>,<Rm>,<type> <Rs> cond:4|0|0|0|0|1|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 |
8163 {0x0fe00010, 0x00c00000, 2, arm_SBC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // SBC{S}<c> <Rd>,<Rn>,<
Rm>{,<shift>} cond:4|0|0|0|0|1|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 | 10641 {0x0fe00010, 0x00c00000, 2, arm_SBC_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // SBC{S}<c> <Rd>,<Rn
>,<Rm>{,<shift>} cond:4|0|0|0|0|1|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 |
8164 {0x0fe00070, 0x07a00050, 4, arm_SBFX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_0, arm_arg_imm5, arm_arg_widthm1}}, // SBFX<c> <Rd>,<Rn>,#<l
sb>,#<widthm1> cond:4|0|1|1|1|1|0|1|widthm1:5|Rd:4|lsb:5|1|0|1|Rn:4 | 10642 {0x0fe00070, 0x07a00050, 4, arm_SBFX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_0, arm_arg_imm5, arm_arg_widthm1}}, // SBFX<c> <Rd>,<Rn>,
#<lsb>,#<widthm1> cond:4|0|1|1|1|1|0|1|widthm1:5|Rd:4|lsb:5|1|0|1|Rn:4 |
8165 {0x0ff00ff0, 0x06800fb0, 4, arm_SEL_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_R_16, arm_arg_R_0}}, // SEL<c> <Rd>,<Rn>,<Rm>
cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 | 10643 {0x0ff00ff0, 0x06800fb0, 4, arm_SEL_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_R_16, arm_arg_R_0}}, // SEL<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 |
8166 {0x0ff000f0, 0x06800fb0, 3, arm_SEL_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_R_16, arm_arg_R_0}}, // SEL<c> <Rd>,<Rn>,<Rm>
cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 | 10644 {0x0ff000f0, 0x06800fb0, 3, arm_SEL_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_R_16, arm_arg_R_0}}, // SEL<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 |
8167 {0xfffffdff, 0xf1010000, 4, arm_SETEND, 0x0, arm_instArgs{arm_arg_endian
}}, // SETEND <endian_specif
ier> 1|1|1|1|0|0|0|1|0|0|0|0|0|0|0|1|0|0|0|0|0|0|E|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(
0)|(0) | 10645 {0xfffffdff, 0xf1010000, 4, arm_SETEND, 0x0, arm_instArgs{arm_arg_endian
}}, // SETEND <endian_spe
cifier> 1|1|1|1|0|0|0|1|0|0|0|0|0|0|0|1|0|0|0|0|0|0|E|(0)|(0)|(0)|(0)|(0)|(0)|(0
)|(0)|(0) |
8168 {0xfffffc00, 0xf1010000, 3, arm_SETEND, 0x0, arm_instArgs{arm_arg_endian
}}, // SETEND <endian_specif
ier> 1|1|1|1|0|0|0|1|0|0|0|0|0|0|0|1|0|0|0|0|0|0|E|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(
0)|(0) | 10646 {0xfffffc00, 0xf1010000, 3, arm_SETEND, 0x0, arm_instArgs{arm_arg_endian
}}, // SETEND <endian_spe
cifier> 1|1|1|1|0|0|0|1|0|0|0|0|0|0|0|1|0|0|0|0|0|0|E|(0)|(0)|(0)|(0)|(0)|(0)|(0
)|(0)|(0) |
8169 {0x0fffffff, 0x0320f004, 4, arm_SEV_EQ, 0x1c04, arm_instArgs{}},
// SEV<c> cond:4|0|0|1|1
|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|1|0|0 | 10647 {0x0fffffff, 0x0320f004, 4, arm_SEV_EQ, 0x1c04, arm_instArgs{}},
// SEV<c> cond:4|0|0|
1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|1|0|0 |
8170 {0x0fff00ff, 0x0320f004, 3, arm_SEV_EQ, 0x1c04, arm_instArgs{}},
// SEV<c> cond:4|0|0|1|1
|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|1|0|0 | 10648 {0x0fff00ff, 0x0320f004, 3, arm_SEV_EQ, 0x1c04, arm_instArgs{}},
// SEV<c> cond:4|0|0|
1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|1|0|0 |
8171 {0x0ff00ff0, 0x06300f10, 4, arm_SHADD16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // SHADD16<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 | 10649 {0x0ff00ff0, 0x06300f10, 4, arm_SHADD16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // SHADD16<c> <Rd>,<R
n>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 |
8172 {0x0ff000f0, 0x06300f10, 3, arm_SHADD16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // SHADD16<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 | 10650 {0x0ff000f0, 0x06300f10, 3, arm_SHADD16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // SHADD16<c> <Rd>,<R
n>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 |
8173 {0x0ff00ff0, 0x06300f90, 4, arm_SHADD8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // SHADD8<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 | 10651 {0x0ff00ff0, 0x06300f90, 4, arm_SHADD8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // SHADD8<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 |
8174 {0x0ff000f0, 0x06300f90, 3, arm_SHADD8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // SHADD8<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 | 10652 {0x0ff000f0, 0x06300f90, 3, arm_SHADD8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // SHADD8<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 |
8175 {0x0ff00ff0, 0x06300f30, 4, arm_SHASX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // SHASX<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 | 10653 {0x0ff00ff0, 0x06300f30, 4, arm_SHASX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // SHASX<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 |
8176 {0x0ff000f0, 0x06300f30, 3, arm_SHASX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // SHASX<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 | 10654 {0x0ff000f0, 0x06300f30, 3, arm_SHASX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // SHASX<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 |
8177 {0x0ff00ff0, 0x06300f50, 4, arm_SHSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // SHSAX<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 | 10655 {0x0ff00ff0, 0x06300f50, 4, arm_SHSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // SHSAX<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 |
8178 {0x0ff000f0, 0x06300f50, 3, arm_SHSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // SHSAX<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 | 10656 {0x0ff000f0, 0x06300f50, 3, arm_SHSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // SHSAX<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 |
8179 {0x0ff00ff0, 0x06300f70, 4, arm_SHSUB16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // SHSUB16<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 | 10657 {0x0ff00ff0, 0x06300f70, 4, arm_SHSUB16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // SHSUB16<c> <Rd>,<R
n>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 |
8180 {0x0ff000f0, 0x06300f70, 3, arm_SHSUB16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // SHSUB16<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 | 10658 {0x0ff000f0, 0x06300f70, 3, arm_SHSUB16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // SHSUB16<c> <Rd>,<R
n>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 |
8181 {0x0ff00ff0, 0x06300ff0, 4, arm_SHSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // SHSUB8<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 | 10659 {0x0ff00ff0, 0x06300ff0, 4, arm_SHSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // SHSUB8<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 |
8182 {0x0ff000f0, 0x06300ff0, 3, arm_SHSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // SHSUB8<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 | 10660 {0x0ff000f0, 0x06300ff0, 3, arm_SHSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // SHSUB8<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 |
8183 {0x0ff00090, 0x01000080, 4, arm_SMLABB_EQ, 0x50106011c04, arm_instArgs{a
rm_arg_R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // SMLA<x><y><c> <Rd>,<R
n>,<Rm>,<Ra> cond:4|0|0|0|1|0|0|0|0|Rd:4|Ra:4|Rm:4|1|M|N|0|Rn:4 | 10661 {0x0ff00090, 0x01000080, 4, arm_SMLABB_EQ, 0x50106011c04, arm_instArgs{a
rm_arg_R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // SMLA<x><y><c> <Rd>
,<Rn>,<Rm>,<Ra> cond:4|0|0|0|1|0|0|0|0|Rd:4|Ra:4|Rm:4|1|M|N|0|Rn:4 |
8184 {0x0ff000d0, 0x07000010, 2, arm_SMLAD_EQ, 0x5011c04, arm_instArgs{arm_ar
g_R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // SMLAD{X}<c> <Rd>,<Rn>
,<Rm>,<Ra> cond:4|0|1|1|1|0|0|0|0|Rd:4|Ra:4|Rm:4|0|0|M|1|Rn:4 | 10662 {0x0ff000d0, 0x07000010, 2, arm_SMLAD_EQ, 0x5011c04, arm_instArgs{arm_ar
g_R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // SMLAD{X}<c> <Rd>,<
Rn>,<Rm>,<Ra> cond:4|0|1|1|1|0|0|0|0|Rd:4|Ra:4|Rm:4|0|0|M|1|Rn:4 |
8185 {0x0ff00090, 0x01400080, 4, arm_SMLALBB_EQ, 0x50106011c04, arm_instArgs{
arm_arg_R_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMLAL<x><y><c> <RdLo>
,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|1|0|1|0|0|RdHi:4|RdLo:4|Rm:4|1|M|N|0|Rn:4 | 10663 {0x0ff00090, 0x01400080, 4, arm_SMLALBB_EQ, 0x50106011c04, arm_instArgs{
arm_arg_R_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMLAL<x><y><c> <Rd
Lo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|1|0|1|0|0|RdHi:4|RdLo:4|Rm:4|1|M|N|0|Rn:4 |
8186 {0x0ff000d0, 0x07400010, 4, arm_SMLALD_EQ, 0x5011c04, arm_instArgs{arm_a
rg_R_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMLALD{X}<c> <RdLo>,<
RdHi>,<Rn>,<Rm> cond:4|0|1|1|1|0|1|0|0|RdHi:4|RdLo:4|Rm:4|0|0|M|1|Rn:4 | 10664 {0x0ff000d0, 0x07400010, 4, arm_SMLALD_EQ, 0x5011c04, arm_instArgs{arm_a
rg_R_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMLALD{X}<c> <RdLo
>,<RdHi>,<Rn>,<Rm> cond:4|0|1|1|1|0|1|0|0|RdHi:4|RdLo:4|Rm:4|0|0|M|1|Rn:4 |
8187 {0x0fe000f0, 0x00e00090, 4, arm_SMLAL_EQ, 0x14011c04, arm_instArgs{arm_a
rg_R_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMLAL{S}<c> <RdLo>,<R
dHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|1|1|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4 | 10665 {0x0fe000f0, 0x00e00090, 4, arm_SMLAL_EQ, 0x14011c04, arm_instArgs{arm_a
rg_R_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMLAL{S}<c> <RdLo>
,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|1|1|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4 |
8188 {0x0ff000b0, 0x01200080, 4, arm_SMLAWB_EQ, 0x6011c04, arm_instArgs{arm_a
rg_R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // SMLAW<y><c> <Rd>,<Rn>
,<Rm>,<Ra> cond:4|0|0|0|1|0|0|1|0|Rd:4|Ra:4|Rm:4|1|M|0|0|Rn:4 | 10666 {0x0ff000b0, 0x01200080, 4, arm_SMLAWB_EQ, 0x6011c04, arm_instArgs{arm_a
rg_R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // SMLAW<y><c> <Rd>,<
Rn>,<Rm>,<Ra> cond:4|0|0|0|1|0|0|1|0|Rd:4|Ra:4|Rm:4|1|M|0|0|Rn:4 |
8189 {0x0ff000d0, 0x07000050, 2, arm_SMLSD_EQ, 0x5011c04, arm_instArgs{arm_ar
g_R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // SMLSD{X}<c> <Rd>,<Rn>
,<Rm>,<Ra> cond:4|0|1|1|1|0|0|0|0|Rd:4|Ra:4|Rm:4|0|1|M|1|Rn:4 | 10667 {0x0ff000d0, 0x07000050, 2, arm_SMLSD_EQ, 0x5011c04, arm_instArgs{arm_ar
g_R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // SMLSD{X}<c> <Rd>,<
Rn>,<Rm>,<Ra> cond:4|0|1|1|1|0|0|0|0|Rd:4|Ra:4|Rm:4|0|1|M|1|Rn:4 |
8190 {0x0ff000d0, 0x07400050, 4, arm_SMLSLD_EQ, 0x5011c04, arm_instArgs{arm_a
rg_R_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMLSLD{X}<c> <RdLo>,<
RdHi>,<Rn>,<Rm> cond:4|0|1|1|1|0|1|0|0|RdHi:4|RdLo:4|Rm:4|0|1|M|1|Rn:4 | 10668 {0x0ff000d0, 0x07400050, 4, arm_SMLSLD_EQ, 0x5011c04, arm_instArgs{arm_a
rg_R_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMLSLD{X}<c> <RdLo
>,<RdHi>,<Rn>,<Rm> cond:4|0|1|1|1|0|1|0|0|RdHi:4|RdLo:4|Rm:4|0|1|M|1|Rn:4 |
8191 {0x0ff000d0, 0x07500010, 2, arm_SMMLA_EQ, 0x5011c04, arm_instArgs{arm_ar
g_R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // SMMLA{R}<c> <Rd>,<Rn>
,<Rm>,<Ra> cond:4|0|1|1|1|0|1|0|1|Rd:4|Ra:4|Rm:4|0|0|R|1|Rn:4 | 10669 {0x0ff000d0, 0x07500010, 2, arm_SMMLA_EQ, 0x5011c04, arm_instArgs{arm_ar
g_R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // SMMLA{R}<c> <Rd>,<
Rn>,<Rm>,<Ra> cond:4|0|1|1|1|0|1|0|1|Rd:4|Ra:4|Rm:4|0|0|R|1|Rn:4 |
8192 {0x0ff000d0, 0x075000d0, 4, arm_SMMLS_EQ, 0x5011c04, arm_instArgs{arm_ar
g_R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // SMMLS{R}<c> <Rd>,<Rn>
,<Rm>,<Ra> cond:4|0|1|1|1|0|1|0|1|Rd:4|Ra:4|Rm:4|1|1|R|1|Rn:4 | 10670 {0x0ff000d0, 0x075000d0, 4, arm_SMMLS_EQ, 0x5011c04, arm_instArgs{arm_ar
g_R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // SMMLS{R}<c> <Rd>,<
Rn>,<Rm>,<Ra> cond:4|0|1|1|1|0|1|0|1|Rd:4|Ra:4|Rm:4|1|1|R|1|Rn:4 |
8193 {0x0ff0f0d0, 0x0750f010, 4, arm_SMMUL_EQ, 0x5011c04, arm_instArgs{arm_ar
g_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMMUL{R}<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|1|0|1|0|1|Rd:4|1|1|1|1|Rm:4|0|0|R|1|Rn:4 | 10671 {0x0ff0f0d0, 0x0750f010, 4, arm_SMMUL_EQ, 0x5011c04, arm_instArgs{arm_ar
g_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMMUL{R}<c> <Rd>,<
Rn>,<Rm> cond:4|0|1|1|1|0|1|0|1|Rd:4|1|1|1|1|Rm:4|0|0|R|1|Rn:4 |
8194 {0x0ff0f0d0, 0x0700f010, 4, arm_SMUAD_EQ, 0x5011c04, arm_instArgs{arm_ar
g_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMUAD{X}<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|1|0|0|0|0|Rd:4|1|1|1|1|Rm:4|0|0|M|1|Rn:4 | 10672 {0x0ff0f0d0, 0x0700f010, 4, arm_SMUAD_EQ, 0x5011c04, arm_instArgs{arm_ar
g_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMUAD{X}<c> <Rd>,<
Rn>,<Rm> cond:4|0|1|1|1|0|0|0|0|Rd:4|1|1|1|1|Rm:4|0|0|M|1|Rn:4 |
8195 {0x0ff0f090, 0x01600080, 4, arm_SMULBB_EQ, 0x50106011c04, arm_instArgs{a
rm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMUL<x><y><c> <Rd>,<R
n>,<Rm> cond:4|0|0|0|1|0|1|1|0|Rd:4|0|0|0|0|Rm:4|1|M|N|0|Rn:4 | 10673 {0x0ff0f090, 0x01600080, 4, arm_SMULBB_EQ, 0x50106011c04, arm_instArgs{a
rm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMUL<x><y><c> <Rd>
,<Rn>,<Rm> cond:4|0|0|0|1|0|1|1|0|Rd:4|0|0|0|0|Rm:4|1|M|N|0|Rn:4 |
8196 {0x0fe000f0, 0x00c00090, 4, arm_SMULL_EQ, 0x14011c04, arm_instArgs{arm_a
rg_R_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMULL{S}<c> <RdLo>,<R
dHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|1|0|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4 | 10674 {0x0fe000f0, 0x00c00090, 4, arm_SMULL_EQ, 0x14011c04, arm_instArgs{arm_a
rg_R_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMULL{S}<c> <RdLo>
,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|1|0|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4 |
8197 {0x0ff0f0b0, 0x012000a0, 4, arm_SMULWB_EQ, 0x6011c04, arm_instArgs{arm_a
rg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMULW<y><c> <Rd>,<Rn>
,<Rm> cond:4|0|0|0|1|0|0|1|0|Rd:4|0|0|0|0|Rm:4|1|M|1|0|Rn:4 | 10675 {0x0ff0f0b0, 0x012000a0, 4, arm_SMULWB_EQ, 0x6011c04, arm_instArgs{arm_a
rg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMULW<y><c> <Rd>,<
Rn>,<Rm> cond:4|0|0|0|1|0|0|1|0|Rd:4|0|0|0|0|Rm:4|1|M|1|0|Rn:4 |
8198 {0x0ff0f0d0, 0x0700f050, 4, arm_SMUSD_EQ, 0x5011c04, arm_instArgs{arm_ar
g_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMUSD{X}<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|1|0|0|0|0|Rd:4|1|1|1|1|Rm:4|0|1|M|1|Rn:4 | 10676 {0x0ff0f0d0, 0x0700f050, 4, arm_SMUSD_EQ, 0x5011c04, arm_instArgs{arm_ar
g_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMUSD{X}<c> <Rd>,<
Rn>,<Rm> cond:4|0|1|1|1|0|0|0|0|Rd:4|1|1|1|1|Rm:4|0|1|M|1|Rn:4 |
8199 {0x0ff00ff0, 0x06a00f30, 4, arm_SSAT16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_satimm4m1, arm_arg_R_0}}, // SSAT16<c> <Rd>,#<sat_
imm4m1>,<Rn> cond:4|0|1|1|0|1|0|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4 | 10677 {0x0ff00ff0, 0x06a00f30, 4, arm_SSAT16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_satimm4m1, arm_arg_R_0}}, // SSAT16<c> <Rd>,#<s
at_imm4m1>,<Rn> cond:4|0|1|1|0|1|0|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn
:4 |
8200 {0x0ff000f0, 0x06a00f30, 3, arm_SSAT16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_satimm4m1, arm_arg_R_0}}, // SSAT16<c> <Rd>,#<sat_
imm4m1>,<Rn> cond:4|0|1|1|0|1|0|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4 | 10678 {0x0ff000f0, 0x06a00f30, 3, arm_SSAT16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_satimm4m1, arm_arg_R_0}}, // SSAT16<c> <Rd>,#<s
at_imm4m1>,<Rn> cond:4|0|1|1|0|1|0|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn
:4 |
8201 {0x0fe00030, 0x06a00010, 4, arm_SSAT_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_satimm5m1, arm_arg_R_shift_imm}}, // SSAT<c> <Rd>,#<sat_im
m5m1>,<Rn>{,<shift>} cond:4|0|1|1|0|1|0|1|sat_imm:5|Rd:4|imm5:5|sh|0|1|Rn:4 | 10679 {0x0fe00030, 0x06a00010, 4, arm_SSAT_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_satimm5m1, arm_arg_R_shift_imm}}, // SSAT<c> <Rd>,#<sat
_imm5m1>,<Rn>{,<shift>} cond:4|0|1|1|0|1|0|1|sat_imm:5|Rd:4|imm5:5|sh|0|1|Rn:4 |
8202 {0x0ff00ff0, 0x06100f50, 4, arm_SSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // SSAX<c> <Rd>,<Rn>,<Rm
> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 | 10680 {0x0ff00ff0, 0x06100f50, 4, arm_SSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // SSAX<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 |
8203 {0x0ff000f0, 0x06100f50, 3, arm_SSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // SSAX<c> <Rd>,<Rn>,<Rm
> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 | 10681 {0x0ff000f0, 0x06100f50, 3, arm_SSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // SSAX<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 |
8204 {0x0ff00ff0, 0x06100f70, 4, arm_SSUB16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // SSUB16<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 | 10682 {0x0ff00ff0, 0x06100f70, 4, arm_SSUB16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // SSUB16<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 |
8205 {0x0ff000f0, 0x06100f70, 3, arm_SSUB16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // SSUB16<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 | 10683 {0x0ff000f0, 0x06100f70, 3, arm_SSUB16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // SSUB16<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 |
8206 {0x0ff00ff0, 0x06100ff0, 4, arm_SSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // SSUB8<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 | 10684 {0x0ff00ff0, 0x06100ff0, 4, arm_SSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // SSUB8<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 |
8207 {0x0ff000f0, 0x06100ff0, 3, arm_SSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // SSUB8<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 | 10685 {0x0ff000f0, 0x06100ff0, 3, arm_SSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // SSUB8<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 |
8208 {0x0fd00000, 0x08800000, 4, arm_STM_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6_WB, arm_arg_registers}}, // STM<c> <Rn>{!},<regis
ters> cond:4|1|0|0|0|1|0|W|0|Rn:4|register_list:16 | 10686 {0x0fd00000, 0x08800000, 4, arm_STM_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6_WB, arm_arg_registers}}, // STM<c> <Rn>{!},<re
gisters> cond:4|1|0|0|0|1|0|W|0|Rn:4|register_list:16 |
8209 {0x0fd00000, 0x08000000, 4, arm_STMDA_EQ, 0x1c04, arm_instArgs{arm_arg_R
_16_WB, arm_arg_registers}}, // STMDA<c> <Rn>{!},<reg
isters> cond:4|1|0|0|0|0|0|W|0|Rn:4|register_list:16 | 10687 {0x0fd00000, 0x08000000, 4, arm_STMDA_EQ, 0x1c04, arm_instArgs{arm_arg_R
_16_WB, arm_arg_registers}}, // STMDA<c> <Rn>{!},<
registers> cond:4|1|0|0|0|0|0|W|0|Rn:4|register_list:16 |
8210 {0x0fd00000, 0x09000000, 2, arm_STMDB_EQ, 0x1c04, arm_instArgs{arm_arg_R
_16_WB, arm_arg_registers}}, // STMDB<c> <Rn>{!},<reg
isters> cond:4|1|0|0|1|0|0|W|0|Rn:4|register_list:16 | 10688 {0x0fd00000, 0x09000000, 2, arm_STMDB_EQ, 0x1c04, arm_instArgs{arm_arg_R
_16_WB, arm_arg_registers}}, // STMDB<c> <Rn>{!},<
registers> cond:4|1|0|0|1|0|0|W|0|Rn:4|register_list:16 |
8211 {0x0fd00000, 0x09800000, 4, arm_STMIB_EQ, 0x1c04, arm_instArgs{arm_arg_R
_16_WB, arm_arg_registers}}, // STMIB<c> <Rn>{!},<reg
isters> cond:4|1|0|0|1|1|0|W|0|Rn:4|register_list:16 | 10689 {0x0fd00000, 0x09800000, 4, arm_STMIB_EQ, 0x1c04, arm_instArgs{arm_arg_R
_16_WB, arm_arg_registers}}, // STMIB<c> <Rn>{!},<
registers> cond:4|1|0|0|1|1|0|W|0|Rn:4|register_list:16 |
8212 {0x0e500018, 0x06000000, 2, arm_STR_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_mem_R_pm_R_shift_imm_W}}, // STR<c> <Rt>,[<Rn>,+/-
<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|0|W|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 | 10690 {0x0e500018, 0x06000000, 2, arm_STR_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_mem_R_pm_R_shift_imm_W}}, // STR<c> <Rt>,[<Rn>,
+/-<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|0|W|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 |
8213 {0x0e500000, 0x04000000, 2, arm_STR_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_mem_R_pm_imm12_W}}, // STR<c> <Rt>,[<Rn>{,#+
/-<imm12>}]{!} cond:4|0|1|0|P|U|0|W|0|Rn:4|Rt:4|imm12:12 | 10691 {0x0e500000, 0x04000000, 2, arm_STR_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
2, arm_arg_mem_R_pm_imm12_W}}, // STR<c> <Rt>,[<Rn>{
,#+/-<imm12>}]{!} cond:4|0|1|0|P|U|0|W|0|Rn:4|Rt:4|imm12:12 |
8214 {0x0e500010, 0x06400000, 2, arm_STRB_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_R_shift_imm_W}}, // STRB<c> <Rt>,[<Rn>,+/
-<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|1|W|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 | 10692 {0x0e500010, 0x06400000, 2, arm_STRB_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_R_shift_imm_W}}, // STRB<c> <Rt>,[<Rn>
,+/-<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|1|W|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 |
8215 {0x0e500000, 0x04400000, 2, arm_STRB_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_imm12_W}}, // STRB<c> <Rt>,[<Rn>{,#
+/-<imm12>}]{!} cond:4|0|1|0|P|U|1|W|0|Rn:4|Rt:4|imm12:12 | 10693 {0x0e500000, 0x04400000, 2, arm_STRB_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_imm12_W}}, // STRB<c> <Rt>,[<Rn>
{,#+/-<imm12>}]{!} cond:4|0|1|0|P|U|1|W|0|Rn:4|Rt:4|imm12:12 |
8216 {0x0f700000, 0x04600000, 4, arm_STRBT_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_imm12_postindex}}, // STRBT<c> <Rt>,[<Rn>],
#+/-<imm12> cond:4|0|1|0|0|U|1|1|0|Rn:4|Rt:4|imm12:12 | 10694 {0x0f700000, 0x04600000, 4, arm_STRBT_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_imm12_postindex}}, // STRBT<c> <Rt>,[<Rn
>],#+/-<imm12> cond:4|0|1|0|0|U|1|1|0|Rn:4|Rt:4|imm12:12 |
8217 {0x0f700010, 0x06600000, 4, arm_STRBT_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_R_shift_imm_postindex}}, // STRBT<c> <Rt>,[<Rn>],
+/-<Rm>{, <shift>} cond:4|0|1|1|0|U|1|1|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 | 10695 {0x0f700010, 0x06600000, 4, arm_STRBT_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_R_shift_imm_postindex}}, // STRBT<c> <Rt>,[<Rn
>],+/-<Rm>{, <shift>} cond:4|0|1|1|0|U|1|1|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 |
8218 {0x0e500ff0, 0x000000f0, 4, arm_STRD_EQ, 0x1c04, arm_instArgs{arm_arg_R1
_12, arm_arg_R2_12, arm_arg_mem_R_pm_R_W}}, // STRD<c> <Rt1>,<Rt2>,[
<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|1|1|Rm:4 | 10696 {0x0e500ff0, 0x000000f0, 4, arm_STRD_EQ, 0x1c04, arm_instArgs{arm_arg_R1
_12, arm_arg_R2_12, arm_arg_mem_R_pm_R_W}}, // STRD<c> <Rt1>,<Rt2
>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|1|1|Rm:
4 |
8219 {0x0e5000f0, 0x000000f0, 3, arm_STRD_EQ, 0x1c04, arm_instArgs{arm_arg_R1
_12, arm_arg_R2_12, arm_arg_mem_R_pm_R_W}}, // STRD<c> <Rt1>,<Rt2>,[
<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|1|1|Rm:4 | 10697 {0x0e5000f0, 0x000000f0, 3, arm_STRD_EQ, 0x1c04, arm_instArgs{arm_arg_R1
_12, arm_arg_R2_12, arm_arg_mem_R_pm_R_W}}, // STRD<c> <Rt1>,<Rt2
>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|1|1|Rm:
4 |
8220 {0x0e5000f0, 0x004000f0, 4, arm_STRD_EQ, 0x1c04, arm_instArgs{arm_arg_R1
_12, arm_arg_R2_12, arm_arg_mem_R_pm_imm8_W}}, // STRD<c> <Rt1>,<Rt2>,[
<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|0|Rn:4|Rt:4|imm4H:4|1|1|1|1|imm4L:4 | 10698 {0x0e5000f0, 0x004000f0, 4, arm_STRD_EQ, 0x1c04, arm_instArgs{arm_arg_R1
_12, arm_arg_R2_12, arm_arg_mem_R_pm_imm8_W}}, // STRD<c> <Rt1>,<Rt2
>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|0|Rn:4|Rt:4|imm4H:4|1|1|1|1|imm4L:
4 |
8221 {0x0ff00ff0, 0x01800f90, 4, arm_STREX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_0, arm_arg_mem_R}}, // STREX<c> <Rd>,<Rt>,[<
Rn>] cond:4|0|0|0|1|1|0|0|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4 | 10699 {0x0ff00ff0, 0x01800f90, 4, arm_STREX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_0, arm_arg_mem_R}}, // STREX<c> <Rd>,<Rt>
,[<Rn>] cond:4|0|0|0|1|1|0|0|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4 |
8222 {0x0ff00ff0, 0x01c00f90, 4, arm_STREXB_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_0, arm_arg_mem_R}}, // STREXB<c> <Rd>,<Rt>,[
<Rn>] cond:4|0|0|0|1|1|1|0|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4 | 10700 {0x0ff00ff0, 0x01c00f90, 4, arm_STREXB_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_0, arm_arg_mem_R}}, // STREXB<c> <Rd>,<Rt
>,[<Rn>] cond:4|0|0|0|1|1|1|0|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4 |
8223 {0x0ff00ff0, 0x01a00f90, 4, arm_STREXD_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R1_0, arm_arg_R2_0, arm_arg_mem_R}}, // STREXD<c> <Rd>,<Rt1>,
<Rt2>,[<Rn>] cond:4|0|0|0|1|1|0|1|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4 | 10701 {0x0ff00ff0, 0x01a00f90, 4, arm_STREXD_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R1_0, arm_arg_R2_0, arm_arg_mem_R}}, // STREXD<c> <Rd>,<Rt
1>,<Rt2>,[<Rn>] cond:4|0|0|0|1|1|0|1|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4 |
8224 {0x0ff00ff0, 0x01e00f90, 4, arm_STREXH_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_0, arm_arg_mem_R}}, // STREXH<c> <Rd>,<Rt>,[
<Rn>] cond:4|0|0|0|1|1|1|1|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4 | 10702 {0x0ff00ff0, 0x01e00f90, 4, arm_STREXH_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_0, arm_arg_mem_R}}, // STREXH<c> <Rd>,<Rt
>,[<Rn>] cond:4|0|0|0|1|1|1|1|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4 |
8225 {0x0e500ff0, 0x000000b0, 2, arm_STRH_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_R_W}}, // STRH<c> <Rt>,[<Rn>,+/
-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4 | 10703 {0x0e500ff0, 0x000000b0, 2, arm_STRH_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_R_W}}, // STRH<c> <Rt>,[<Rn>
,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4 |
8226 {0x0e5000f0, 0x004000b0, 2, arm_STRH_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_imm8_W}}, // STRH<c> <Rt>,[<Rn>{,#
+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|0|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4 | 10704 {0x0e5000f0, 0x004000b0, 2, arm_STRH_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_imm8_W}}, // STRH<c> <Rt>,[<Rn>
{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|0|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4 |
8227 {0x0f7000f0, 0x006000b0, 4, arm_STRHT_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_imm8_postindex}}, // STRHT<c> <Rt>, [<Rn>]
{,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|0|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4 | 10705 {0x0f7000f0, 0x006000b0, 4, arm_STRHT_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_imm8_postindex}}, // STRHT<c> <Rt>, [<R
n>] {,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|0|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4 |
8228 {0x0f700ff0, 0x002000b0, 4, arm_STRHT_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_R_postindex}}, // STRHT<c> <Rt>, [<Rn>]
, +/-<Rm> cond:4|0|0|0|0|U|0|1|0|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4 | 10706 {0x0f700ff0, 0x002000b0, 4, arm_STRHT_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_mem_R_pm_R_postindex}}, // STRHT<c> <Rt>, [<R
n>], +/-<Rm> cond:4|0|0|0|0|U|0|1|0|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4 |
8229 {0x0f700000, 0x04200000, 4, arm_STRT_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_imm12_postindex}}, // STRT<c> <Rt>, [<Rn>]
{,#+/-<imm12>} cond:4|0|1|0|0|U|0|1|0|Rn:4|Rt:4|imm12:12 | 10707 {0x0f700000, 0x04200000, 4, arm_STRT_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_imm12_postindex}}, // STRT<c> <Rt>, [<Rn
>] {,#+/-<imm12>} cond:4|0|1|0|0|U|0|1|0|Rn:4|Rt:4|imm12:12 |
8230 {0x0f700010, 0x06200000, 4, arm_STRT_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_R_shift_imm_postindex}}, // STRT<c> <Rt>,[<Rn>],+
/-<Rm>{, <shift>} cond:4|0|1|1|0|U|0|1|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 | 10708 {0x0f700010, 0x06200000, 4, arm_STRT_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_mem_R_pm_R_shift_imm_postindex}}, // STRT<c> <Rt>,[<Rn>
],+/-<Rm>{, <shift>} cond:4|0|1|1|0|U|0|1|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 |
8231 {0x0fe00000, 0x02400000, 2, arm_SUB_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_const}}, // SUB{S}<c> <Rd>,<Rn>,#
<const> cond:4|0|0|1|0|0|1|0|S|Rn:4|Rd:4|imm12:12 | 10709 {0x0fe00000, 0x02400000, 2, arm_SUB_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_const}}, // SUB{S}<c> <Rd>,<Rn
>,#<const> cond:4|0|0|1|0|0|1|0|S|Rn:4|Rd:4|imm12:12 |
8232 {0x0fe00090, 0x00400010, 4, arm_SUB_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // SUB{S}<c> <Rd>,<Rn>,<
Rm>,<type> <Rs> cond:4|0|0|0|0|0|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 | 10710 {0x0fe00090, 0x00400010, 4, arm_SUB_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // SUB{S}<c> <Rd>,<Rn
>,<Rm>,<type> <Rs> cond:4|0|0|0|0|0|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 |
8233 {0x0fe00010, 0x00400000, 2, arm_SUB_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // SUB{S}<c> <Rd>,<Rn>,<
Rm>{,<shift>} cond:4|0|0|0|0|0|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 | 10711 {0x0fe00010, 0x00400000, 2, arm_SUB_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // SUB{S}<c> <Rd>,<Rn
>,<Rm>{,<shift>} cond:4|0|0|0|0|0|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 |
8234 {0x0fef0000, 0x024d0000, 2, arm_SUB_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_SP, arm_arg_const}}, // SUB{S}<c> <Rd>,SP,#<c
onst> cond:4|0|0|1|0|0|1|0|S|1|1|0|1|Rd:4|imm12:12 | 10712 {0x0fef0000, 0x024d0000, 2, arm_SUB_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_SP, arm_arg_const}}, // SUB{S}<c> <Rd>,SP,
#<const> cond:4|0|0|1|0|0|1|0|S|1|1|0|1|Rd:4|imm12:12 |
8235 {0x0fef0010, 0x004d0000, 2, arm_SUB_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_SP, arm_arg_R_shift_imm}}, // SUB{S}<c> <Rd>,SP,<Rm
>{,<shift>} cond:4|0|0|0|0|0|1|0|S|1|1|0|1|Rd:4|imm5:5|type:2|0|Rm:4 | 10713 {0x0fef0010, 0x004d0000, 2, arm_SUB_EQ, 0x14011c04, arm_instArgs{arm_arg
_R_12, arm_arg_SP, arm_arg_R_shift_imm}}, // SUB{S}<c> <Rd>,SP,
<Rm>{,<shift>} cond:4|0|0|0|0|0|1|0|S|1|1|0|1|Rd:4|imm5:5|type:2|0|Rm:4 |
8236 {0x0f000000, 0x0f000000, 4, arm_SVC_EQ, 0x1c04, arm_instArgs{arm_arg_imm
24}}, // SVC<c> #<imm24> cond:
4|1|1|1|1|imm24:24 | 10714 {0x0f000000, 0x0f000000, 4, arm_SVC_EQ, 0x1c04, arm_instArgs{arm_arg_imm
24}}, // SVC<c> #<imm24> co
nd:4|1|1|1|1|imm24:24 |
8237 {0x0fb00ff0, 0x01000090, 4, arm_SWP_EQ, 0x16011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_0, arm_arg_mem_R}}, // SWP{B}<c> <Rt>,<Rm>,[
<Rn>] cond:4|0|0|0|1|0|B|0|0|Rn:4|Rt:4|0|0|0|0|1|0|0|1|Rm:4 | 10715 {0x0fb00ff0, 0x01000090, 4, arm_SWP_EQ, 0x16011c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_0, arm_arg_mem_R}}, // SWP{B}<c> <Rt>,<Rm
>,[<Rn>] cond:4|0|0|0|1|0|B|0|0|Rn:4|Rt:4|0|0|0|0|1|0|0|1|Rm:4 |
8238 {0x0ff003f0, 0x06800070, 2, arm_SXTAB16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_rotate}}, // SXTAB16<c> <Rd>,<Rn>,
<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 | 10716 {0x0ff003f0, 0x06800070, 2, arm_SXTAB16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_rotate}}, // SXTAB16<c> <Rd>,<R
n>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 |
8239 {0x0ff003f0, 0x06a00070, 2, arm_SXTAB_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_rotate}}, // SXTAB<c> <Rd>,<Rn>,<R
m>{,<rotation>} cond:4|0|1|1|0|1|0|1|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 | 10717 {0x0ff003f0, 0x06a00070, 2, arm_SXTAB_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_rotate}}, // SXTAB<c> <Rd>,<Rn>
,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|1|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 |
8240 {0x0ff003f0, 0x06b00070, 2, arm_SXTAH_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_rotate}}, // SXTAH<c> <Rd>,<Rn>,<R
m>{,<rotation>} cond:4|0|1|1|0|1|0|1|1|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 | 10718 {0x0ff003f0, 0x06b00070, 2, arm_SXTAH_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_rotate}}, // SXTAH<c> <Rd>,<Rn>
,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|1|1|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 |
8241 {0x0fff03f0, 0x068f0070, 4, arm_SXTB16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_rotate}}, // SXTB16<c> <Rd>,<Rm>{,
<rotation>} cond:4|0|1|1|0|1|0|0|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 | 10719 {0x0fff03f0, 0x068f0070, 4, arm_SXTB16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_rotate}}, // SXTB16<c> <Rd>,<Rm
>{,<rotation>} cond:4|0|1|1|0|1|0|0|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 |
8242 {0x0fff03f0, 0x06af0070, 4, arm_SXTB_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_rotate}}, // SXTB<c> <Rd>,<Rm>{,<r
otation>} cond:4|0|1|1|0|1|0|1|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 | 10720 {0x0fff03f0, 0x06af0070, 4, arm_SXTB_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_rotate}}, // SXTB<c> <Rd>,<Rm>{
,<rotation>} cond:4|0|1|1|0|1|0|1|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 |
8243 {0x0fff03f0, 0x06bf0070, 4, arm_SXTH_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_rotate}}, // SXTH<c> <Rd>,<Rm>{,<r
otation>} cond:4|0|1|1|0|1|0|1|1|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 | 10721 {0x0fff03f0, 0x06bf0070, 4, arm_SXTH_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_rotate}}, // SXTH<c> <Rd>,<Rm>{
,<rotation>} cond:4|0|1|1|0|1|0|1|1|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 |
8244 {0x0ff0f000, 0x03300000, 4, arm_TEQ_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_const}}, // TEQ<c> <Rn>,#<const>
cond:4|0|0|1|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 | 10722 {0x0ff0f000, 0x03300000, 4, arm_TEQ_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_const}}, // TEQ<c> <Rn>,#<cons
t> cond:4|0|0|1|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 |
8245 {0x0ff00000, 0x03300000, 3, arm_TEQ_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_const}}, // TEQ<c> <Rn>,#<const>
cond:4|0|0|1|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 | 10723 {0x0ff00000, 0x03300000, 3, arm_TEQ_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_const}}, // TEQ<c> <Rn>,#<cons
t> cond:4|0|0|1|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 |
8246 {0x0ff0f090, 0x01300010, 4, arm_TEQ_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_R}}, // TEQ<c> <Rn>,<Rm>,<typ
e> <Rs> cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 | 10724 {0x0ff0f090, 0x01300010, 4, arm_TEQ_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_R}}, // TEQ<c> <Rn>,<Rm>,<
type> <Rs> cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 |
8247 {0x0ff00090, 0x01300010, 3, arm_TEQ_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_R}}, // TEQ<c> <Rn>,<Rm>,<typ
e> <Rs> cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 | 10725 {0x0ff00090, 0x01300010, 3, arm_TEQ_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_R}}, // TEQ<c> <Rn>,<Rm>,<
type> <Rs> cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 |
8248 {0x0ff0f010, 0x01300000, 4, arm_TEQ_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_imm}}, // TEQ<c> <Rn>,<Rm>{,<sh
ift>} cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 | 10726 {0x0ff0f010, 0x01300000, 4, arm_TEQ_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_imm}}, // TEQ<c> <Rn>,<Rm>{,
<shift>} cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 |
8249 {0x0ff00010, 0x01300000, 3, arm_TEQ_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_imm}}, // TEQ<c> <Rn>,<Rm>{,<sh
ift>} cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 | 10727 {0x0ff00010, 0x01300000, 3, arm_TEQ_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_imm}}, // TEQ<c> <Rn>,<Rm>{,
<shift>} cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 |
8250 {0x0ff0f000, 0x03100000, 4, arm_TST_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_const}}, // TST<c> <Rn>,#<const>
cond:4|0|0|1|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 | 10728 {0x0ff0f000, 0x03100000, 4, arm_TST_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_const}}, // TST<c> <Rn>,#<cons
t> cond:4|0|0|1|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 |
8251 {0x0ff00000, 0x03100000, 3, arm_TST_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_const}}, // TST<c> <Rn>,#<const>
cond:4|0|0|1|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 | 10729 {0x0ff00000, 0x03100000, 3, arm_TST_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_const}}, // TST<c> <Rn>,#<cons
t> cond:4|0|0|1|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 |
8252 {0x0ff0f090, 0x01100010, 4, arm_TST_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_R}}, // TST<c> <Rn>,<Rm>,<typ
e> <Rs> cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 | 10730 {0x0ff0f090, 0x01100010, 4, arm_TST_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_R}}, // TST<c> <Rn>,<Rm>,<
type> <Rs> cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 |
8253 {0x0ff00090, 0x01100010, 3, arm_TST_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_R}}, // TST<c> <Rn>,<Rm>,<typ
e> <Rs> cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 | 10731 {0x0ff00090, 0x01100010, 3, arm_TST_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_R}}, // TST<c> <Rn>,<Rm>,<
type> <Rs> cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 |
8254 {0x0ff0f010, 0x01100000, 4, arm_TST_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_imm}}, // TST<c> <Rn>,<Rm>{,<sh
ift>} cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 | 10732 {0x0ff0f010, 0x01100000, 4, arm_TST_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_imm}}, // TST<c> <Rn>,<Rm>{,
<shift>} cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 |
8255 {0x0ff00010, 0x01100000, 3, arm_TST_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_imm}}, // TST<c> <Rn>,<Rm>{,<sh
ift>} cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 | 10733 {0x0ff00010, 0x01100000, 3, arm_TST_EQ, 0x1c04, arm_instArgs{arm_arg_R_1
6, arm_arg_R_shift_imm}}, // TST<c> <Rn>,<Rm>{,
<shift>} cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 |
8256 {0x0ff00ff0, 0x06500f10, 4, arm_UADD16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // UADD16<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 | 10734 {0x0ff00ff0, 0x06500f10, 4, arm_UADD16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // UADD16<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 |
8257 {0x0ff000f0, 0x06500f10, 3, arm_UADD16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // UADD16<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 | 10735 {0x0ff000f0, 0x06500f10, 3, arm_UADD16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // UADD16<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 |
8258 {0x0ff00ff0, 0x06500f90, 4, arm_UADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // UADD8<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 | 10736 {0x0ff00ff0, 0x06500f90, 4, arm_UADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // UADD8<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 |
8259 {0x0ff000f0, 0x06500f90, 3, arm_UADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // UADD8<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 | 10737 {0x0ff000f0, 0x06500f90, 3, arm_UADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // UADD8<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 |
8260 {0x0ff00ff0, 0x06500f30, 4, arm_UASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // UASX<c> <Rd>,<Rn>,<Rm
> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 | 10738 {0x0ff00ff0, 0x06500f30, 4, arm_UASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // UASX<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 |
8261 {0x0ff000f0, 0x06500f30, 3, arm_UASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // UASX<c> <Rd>,<Rn>,<Rm
> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 | 10739 {0x0ff000f0, 0x06500f30, 3, arm_UASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // UASX<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 |
8262 {0x0fe00070, 0x07e00050, 4, arm_UBFX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_0, arm_arg_imm5, arm_arg_widthm1}}, // UBFX<c> <Rd>,<Rn>,#<l
sb>,#<widthm1> cond:4|0|1|1|1|1|1|1|widthm1:5|Rd:4|lsb:5|1|0|1|Rn:4 | 10740 {0x0fe00070, 0x07e00050, 4, arm_UBFX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_0, arm_arg_imm5, arm_arg_widthm1}}, // UBFX<c> <Rd>,<Rn>,
#<lsb>,#<widthm1> cond:4|0|1|1|1|1|1|1|widthm1:5|Rd:4|lsb:5|1|0|1|Rn:4 |
8263 {0x0ff00ff0, 0x06700f10, 4, arm_UHADD16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // UHADD16<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 | 10741 {0x0ff00ff0, 0x06700f10, 4, arm_UHADD16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // UHADD16<c> <Rd>,<R
n>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 |
8264 {0x0ff000f0, 0x06700f10, 3, arm_UHADD16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // UHADD16<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 | 10742 {0x0ff000f0, 0x06700f10, 3, arm_UHADD16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // UHADD16<c> <Rd>,<R
n>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 |
8265 {0x0ff00ff0, 0x06700f90, 4, arm_UHADD8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // UHADD8<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 | 10743 {0x0ff00ff0, 0x06700f90, 4, arm_UHADD8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // UHADD8<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 |
8266 {0x0ff000f0, 0x06700f90, 3, arm_UHADD8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // UHADD8<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 | 10744 {0x0ff000f0, 0x06700f90, 3, arm_UHADD8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // UHADD8<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 |
8267 {0x0ff00ff0, 0x06700f30, 4, arm_UHASX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // UHASX<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 | 10745 {0x0ff00ff0, 0x06700f30, 4, arm_UHASX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // UHASX<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 |
8268 {0x0ff000f0, 0x06700f30, 3, arm_UHASX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // UHASX<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 | 10746 {0x0ff000f0, 0x06700f30, 3, arm_UHASX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // UHASX<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 |
8269 {0x0ff00ff0, 0x06700f50, 4, arm_UHSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // UHSAX<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 | 10747 {0x0ff00ff0, 0x06700f50, 4, arm_UHSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // UHSAX<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 |
8270 {0x0ff000f0, 0x06700f50, 3, arm_UHSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // UHSAX<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 | 10748 {0x0ff000f0, 0x06700f50, 3, arm_UHSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // UHSAX<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 |
8271 {0x0ff00ff0, 0x06700f70, 4, arm_UHSUB16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // UHSUB16<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 | 10749 {0x0ff00ff0, 0x06700f70, 4, arm_UHSUB16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // UHSUB16<c> <Rd>,<R
n>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 |
8272 {0x0ff000f0, 0x06700f70, 3, arm_UHSUB16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // UHSUB16<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 | 10750 {0x0ff000f0, 0x06700f70, 3, arm_UHSUB16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // UHSUB16<c> <Rd>,<R
n>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 |
8273 {0x0ff00ff0, 0x06700ff0, 4, arm_UHSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // UHSUB8<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 | 10751 {0x0ff00ff0, 0x06700ff0, 4, arm_UHSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // UHSUB8<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 |
8274 {0x0ff000f0, 0x06700ff0, 3, arm_UHSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // UHSUB8<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 | 10752 {0x0ff000f0, 0x06700ff0, 3, arm_UHSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // UHSUB8<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 |
8275 {0x0ff000f0, 0x00400090, 4, arm_UMAAL_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // UMAAL<c> <RdLo>,<RdHi
>,<Rn>,<Rm> cond:4|0|0|0|0|0|1|0|0|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4 | 10753 {0x0ff000f0, 0x00400090, 4, arm_UMAAL_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // UMAAL<c> <RdLo>,<R
dHi>,<Rn>,<Rm> cond:4|0|0|0|0|0|1|0|0|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4 |
8276 {0x0fe000f0, 0x00a00090, 4, arm_UMLAL_EQ, 0x14011c04, arm_instArgs{arm_a
rg_R_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // UMLAL{S}<c> <RdLo>,<R
dHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|0|1|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4 | 10754 {0x0fe000f0, 0x00a00090, 4, arm_UMLAL_EQ, 0x14011c04, arm_instArgs{arm_a
rg_R_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // UMLAL{S}<c> <RdLo>
,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|0|1|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4 |
8277 {0x0fe000f0, 0x00800090, 4, arm_UMULL_EQ, 0x14011c04, arm_instArgs{arm_a
rg_R_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // UMULL{S}<c> <RdLo>,<R
dHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|0|0|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4 | 10755 {0x0fe000f0, 0x00800090, 4, arm_UMULL_EQ, 0x14011c04, arm_instArgs{arm_a
rg_R_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // UMULL{S}<c> <RdLo>
,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|0|0|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4 |
8278 {0x0ff00ff0, 0x06600f10, 4, arm_UQADD16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // UQADD16<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 | 10756 {0x0ff00ff0, 0x06600f10, 4, arm_UQADD16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // UQADD16<c> <Rd>,<R
n>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 |
8279 {0x0ff000f0, 0x06600f10, 3, arm_UQADD16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // UQADD16<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 | 10757 {0x0ff000f0, 0x06600f10, 3, arm_UQADD16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // UQADD16<c> <Rd>,<R
n>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 |
8280 {0x0ff00ff0, 0x06600f90, 4, arm_UQADD8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // UQADD8<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 | 10758 {0x0ff00ff0, 0x06600f90, 4, arm_UQADD8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // UQADD8<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 |
8281 {0x0ff000f0, 0x06600f90, 3, arm_UQADD8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // UQADD8<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 | 10759 {0x0ff000f0, 0x06600f90, 3, arm_UQADD8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // UQADD8<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 |
8282 {0x0ff00ff0, 0x06600f30, 4, arm_UQASX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // UQASX<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 | 10760 {0x0ff00ff0, 0x06600f30, 4, arm_UQASX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // UQASX<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 |
8283 {0x0ff000f0, 0x06600f30, 3, arm_UQASX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // UQASX<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 | 10761 {0x0ff000f0, 0x06600f30, 3, arm_UQASX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // UQASX<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 |
8284 {0x0ff00ff0, 0x06600f50, 4, arm_UQSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // UQSAX<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 | 10762 {0x0ff00ff0, 0x06600f50, 4, arm_UQSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // UQSAX<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 |
8285 {0x0ff000f0, 0x06600f50, 3, arm_UQSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // UQSAX<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 | 10763 {0x0ff000f0, 0x06600f50, 3, arm_UQSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // UQSAX<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 |
8286 {0x0ff00ff0, 0x06600f70, 4, arm_UQSUB16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // UQSUB16<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 | 10764 {0x0ff00ff0, 0x06600f70, 4, arm_UQSUB16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // UQSUB16<c> <Rd>,<R
n>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 |
8287 {0x0ff000f0, 0x06600f70, 3, arm_UQSUB16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // UQSUB16<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 | 10765 {0x0ff000f0, 0x06600f70, 3, arm_UQSUB16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_0}}, // UQSUB16<c> <Rd>,<R
n>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 |
8288 {0x0ff00ff0, 0x06600ff0, 4, arm_UQSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // UQSUB8<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 | 10766 {0x0ff00ff0, 0x06600ff0, 4, arm_UQSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // UQSUB8<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 |
8289 {0x0ff000f0, 0x06600ff0, 3, arm_UQSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // UQSUB8<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 | 10767 {0x0ff000f0, 0x06600ff0, 3, arm_UQSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // UQSUB8<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 |
8290 {0x0ff0f0f0, 0x0780f010, 4, arm_USAD8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_16, arm_arg_R_0, arm_arg_R_8}}, // USAD8<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|1|1|0|0|0|Rd:4|1|1|1|1|Rm:4|0|0|0|1|Rn:4 | 10768 {0x0ff0f0f0, 0x0780f010, 4, arm_USAD8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_16, arm_arg_R_0, arm_arg_R_8}}, // USAD8<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|1|1|0|0|0|Rd:4|1|1|1|1|Rm:4|0|0|0|1|Rn:4 |
8291 {0x0ff000f0, 0x07800010, 2, arm_USADA8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // USADA8<c> <Rd>,<Rn>,<
Rm>,<Ra> cond:4|0|1|1|1|1|0|0|0|Rd:4|Ra:4|Rm:4|0|0|0|1|Rn:4 | 10769 {0x0ff000f0, 0x07800010, 2, arm_USADA8_EQ, 0x1c04, arm_instArgs{arm_arg_
R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // USADA8<c> <Rd>,<Rn
>,<Rm>,<Ra> cond:4|0|1|1|1|1|0|0|0|Rd:4|Ra:4|Rm:4|0|0|0|1|Rn:4 |
8292 {0x0ff00ff0, 0x06e00f30, 4, arm_USAT16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_satimm4, arm_arg_R_0}}, // USAT16<c> <Rd>,#<sat_
imm4>,<Rn> cond:4|0|1|1|0|1|1|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4 | 10770 {0x0ff00ff0, 0x06e00f30, 4, arm_USAT16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_satimm4, arm_arg_R_0}}, // USAT16<c> <Rd>,#<s
at_imm4>,<Rn> cond:4|0|1|1|0|1|1|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4 |
8293 {0x0ff000f0, 0x06e00f30, 3, arm_USAT16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_satimm4, arm_arg_R_0}}, // USAT16<c> <Rd>,#<sat_
imm4>,<Rn> cond:4|0|1|1|0|1|1|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4 | 10771 {0x0ff000f0, 0x06e00f30, 3, arm_USAT16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_satimm4, arm_arg_R_0}}, // USAT16<c> <Rd>,#<s
at_imm4>,<Rn> cond:4|0|1|1|0|1|1|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4 |
8294 {0x0fe00030, 0x06e00010, 4, arm_USAT_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_satimm5, arm_arg_R_shift_imm}}, // USAT<c> <Rd>,#<sat_im
m5>,<Rn>{,<shift>} cond:4|0|1|1|0|1|1|1|sat_imm:5|Rd:4|imm5:5|sh|0|1|Rn:4 | 10772 {0x0fe00030, 0x06e00010, 4, arm_USAT_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_satimm5, arm_arg_R_shift_imm}}, // USAT<c> <Rd>,#<sat
_imm5>,<Rn>{,<shift>} cond:4|0|1|1|0|1|1|1|sat_imm:5|Rd:4|imm5:5|sh|0|1|Rn:4 |
8295 {0x0ff00ff0, 0x06500f50, 4, arm_USAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // USAX<c> <Rd>,<Rn>,<Rm
> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 | 10773 {0x0ff00ff0, 0x06500f50, 4, arm_USAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // USAX<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 |
8296 {0x0ff000f0, 0x06500f50, 3, arm_USAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // USAX<c> <Rd>,<Rn>,<Rm
> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 | 10774 {0x0ff000f0, 0x06500f50, 3, arm_USAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_16, arm_arg_R_0}}, // USAX<c> <Rd>,<Rn>,
<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 |
8297 {0x0ff00ff0, 0x06500f70, 4, arm_USUB16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // USUB16<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 | 10775 {0x0ff00ff0, 0x06500f70, 4, arm_USUB16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // USUB16<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 |
8298 {0x0ff000f0, 0x06500f70, 3, arm_USUB16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // USUB16<c> <Rd>,<Rn>,<
Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 | 10776 {0x0ff000f0, 0x06500f70, 3, arm_USUB16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_16, arm_arg_R_0}}, // USUB16<c> <Rd>,<Rn
>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 |
8299 {0x0ff00ff0, 0x06500ff0, 4, arm_USUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // USUB8<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 | 10777 {0x0ff00ff0, 0x06500ff0, 4, arm_USUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // USUB8<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 |
8300 {0x0ff000f0, 0x06500ff0, 3, arm_USUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // USUB8<c> <Rd>,<Rn>,<R
m> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 | 10778 {0x0ff000f0, 0x06500ff0, 3, arm_USUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_0}}, // USUB8<c> <Rd>,<Rn>
,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 |
8301 {0x0ff003f0, 0x06c00070, 2, arm_UXTAB16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_rotate}}, // UXTAB16<c> <Rd>,<Rn>,
<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|0|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 | 10779 {0x0ff003f0, 0x06c00070, 2, arm_UXTAB16_EQ, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_R_16, arm_arg_R_rotate}}, // UXTAB16<c> <Rd>,<R
n>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|0|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 |
8302 {0x0ff003f0, 0x06e00070, 2, arm_UXTAB_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_rotate}}, // UXTAB<c> <Rd>,<Rn>,<R
m>{,<rotation>} cond:4|0|1|1|0|1|1|1|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 | 10780 {0x0ff003f0, 0x06e00070, 2, arm_UXTAB_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_rotate}}, // UXTAB<c> <Rd>,<Rn>
,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|1|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 |
8303 {0x0ff003f0, 0x06f00070, 2, arm_UXTAH_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_rotate}}, // UXTAH<c> <Rd>,<Rn>,<R
m>{,<rotation>} cond:4|0|1|1|0|1|1|1|1|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 | 10781 {0x0ff003f0, 0x06f00070, 2, arm_UXTAH_EQ, 0x1c04, arm_instArgs{arm_arg_R
_12, arm_arg_R_16, arm_arg_R_rotate}}, // UXTAH<c> <Rd>,<Rn>
,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|1|1|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 |
8304 {0x0fff03f0, 0x06cf0070, 4, arm_UXTB16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_rotate}}, // UXTB16<c> <Rd>,<Rm>{,
<rotation>} cond:4|0|1|1|0|1|1|0|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 | 10782 {0x0fff03f0, 0x06cf0070, 4, arm_UXTB16_EQ, 0x1c04, arm_instArgs{arm_arg_
R_12, arm_arg_R_rotate}}, // UXTB16<c> <Rd>,<Rm
>{,<rotation>} cond:4|0|1|1|0|1|1|0|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 |
8305 {0x0fff03f0, 0x06ef0070, 4, arm_UXTB_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_rotate}}, // UXTB<c> <Rd>,<Rm>{,<r
otation>} cond:4|0|1|1|0|1|1|1|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 | 10783 {0x0fff03f0, 0x06ef0070, 4, arm_UXTB_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_rotate}}, // UXTB<c> <Rd>,<Rm>{
,<rotation>} cond:4|0|1|1|0|1|1|1|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 |
8306 {0x0fff03f0, 0x06ff0070, 4, arm_UXTH_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_rotate}}, // UXTH<c> <Rd>,<Rm>{,<r
otation>} cond:4|0|1|1|0|1|1|1|1|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 | 10784 {0x0fff03f0, 0x06ff0070, 4, arm_UXTH_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_R_rotate}}, // UXTH<c> <Rd>,<Rm>{
,<rotation>} cond:4|0|1|1|0|1|1|1|1|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 |
8307 {0x0fffffff, 0x0320f002, 4, arm_WFE_EQ, 0x1c04, arm_instArgs{}},
// WFE<c> cond:4|0|0|1|1
|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|0 | 10785 {0x0fb00e10, 0x0e000a00, 4, arm_VMLA_EQ_F32, 0x60108011c04, arm_instArgs
{arm_arg_Sd_Dd, arm_arg_Sn_Dn, arm_arg_Sm_Dm}}, // V<MLA,MLS><c>.F<32
,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|0|0|Vn:4|Vd:4|1|0|1|sz|N|op|M|
0|Vm:4 |
8308 {0x0fff00ff, 0x0320f002, 3, arm_WFE_EQ, 0x1c04, arm_instArgs{}},
// WFE<c> cond:4|0|0|1|1
|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|0 | 10786 {0x0fbf0ed0, 0x0eb00ac0, 4, arm_VABS_EQ_F32, 0x8011c04, arm_instArgs{arm
_arg_Sd_Dd, arm_arg_Sm_Dm}}, // VABS<c>.F<32,64> <
Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|0|0|0|Vd:4|1|0|1|sz|1|1|M|0|Vm:4 |
8309 {0x0fffffff, 0x0320f003, 4, arm_WFI_EQ, 0x1c04, arm_instArgs{}},
// WFI<c> cond:4|0|0|1|1
|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|1 | 10787 {0x0fb00e50, 0x0e300a00, 4, arm_VADD_EQ_F32, 0x8011c04, arm_instArgs{arm
_arg_Sd_Dd, arm_arg_Sn_Dn, arm_arg_Sm_Dm}}, // VADD<c>.F<32,64> <
Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|1|1|Vn:4|Vd:4|1|0|1|sz|N|0|M|0|Vm:4 |
8310 {0x0fff00ff, 0x0320f003, 3, arm_WFI_EQ, 0x1c04, arm_instArgs{}},
// WFI<c> cond:4|0|0|1|1
|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|1 | 10788 {0x0fbf0e7f, 0x0eb50a40, 4, arm_VCMP_EQ_F32, 0x70108011c04, arm_instArgs
{arm_arg_Sd_Dd, arm_arg_fp_0}}, // VCMP{E}<c>.F<32,64
> <Sd,Dd>, #0.0 cond:4|1|1|1|0|1|D|1|1|0|1|0|1|Vd:4|1|0|1|sz|E|1|0|0|(0)|(0)|(0)
|(0) |
8311 {0x0fffffff, 0x0320f001, 4, arm_YIELD_EQ, 0x1c04, arm_instArgs{}},
// YIELD<c> cond:4|0|0|1
|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|1 | 10789 {0x0fbf0e70, 0x0eb50a40, 3, arm_VCMP_EQ_F32, 0x70108011c04, arm_instArgs
{arm_arg_Sd_Dd, arm_arg_fp_0}}, // VCMP{E}<c>.F<32,64
> <Sd,Dd>, #0.0 cond:4|1|1|1|0|1|D|1|1|0|1|0|1|Vd:4|1|0|1|sz|E|1|0|0|(0)|(0)|(0)
|(0) |
8312 {0x0fff00ff, 0x0320f001, 3, arm_YIELD_EQ, 0x1c04, arm_instArgs{}},
// YIELD<c> cond:4|0|0|1
|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|1 | 10790 {0x0fbf0e50, 0x0eb40a40, 4, arm_VCMP_EQ_F32, 0x70108011c04, arm_instArgs
{arm_arg_Sd_Dd, arm_arg_Sm_Dm}}, // VCMP{E}<c>.F<32,64
> <Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|1|0|0|Vd:4|1|0|1|sz|E|1|M|0|Vm:4 |
| 10791 {0x0fbe0e50, 0x0eba0a40, 4, arm_VCVT_EQ_F32_FXS16, 0x801100107011c04, ar
m_instArgs{arm_arg_Sd_Dd, arm_arg_Sd_Dd, arm_arg_fbits}}, // VCVT<c>.F<32,64>.F
X<S,U><16,32> <Sd,Dd>, <Sd,Dd>, #<fbits> cond:4|1|1|1|0|1|D|1|1|1|0|1|U|Vd:4|1|0
|1|sz|sx|1|i|0|imm4:4 |
| 10792 {0x0fbe0e50, 0x0ebe0a40, 4, arm_VCVT_EQ_FXS16_F32, 0x1001070108011c04, a
rm_instArgs{arm_arg_Sd_Dd, arm_arg_Sd_Dd, arm_arg_fbits}}, // VCVT<c>.FX<S,U><16
,32>.F<32,64> <Sd,Dd>, <Sd,Dd>, #<fbits> cond:4|1|1|1|0|1|D|1|1|1|1|1|U|Vd:4|1|0
|1|sz|sx|1|i|0|imm4:4 |
| 10793 {0x0fbf0ed0, 0x0eb70ac0, 4, arm_VCVT_EQ_F64_F32, 0x8011c04, arm_instArgs
{arm_arg_Dd_Sd, arm_arg_Sm_Dm}}, // VCVT<c>.<F64.F32,F
32.F64> <Dd,Sd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|1|1|1|Vd:4|1|0|1|sz|1|1|M|0|Vm
:4 |
| 10794 {0x0fbe0f50, 0x0eb20a40, 4, arm_VCVTB_EQ_F32_F16, 0x70110011c04, arm_ins
tArgs{arm_arg_Sd, arm_arg_Sm}}, // VCVT<B,T><c>.<F32.
F16,F16.F32> <Sd>, <Sm> cond:4|1|1|1|0|1|D|1|1|0|0|1|op|Vd:4|1|0|1|0|T|1|M|0|Vm:
4 |
| 10795 {0x0fbf0e50, 0x0eb80a40, 4, arm_VCVT_EQ_F32_U32, 0x80107011c04, arm_inst
Args{arm_arg_Sd_Dd, arm_arg_Sm}}, // VCVT<c>.F<32,64>.<
U,S>32 <Sd,Dd>, <Sm> cond:4|1|1|1|0|1|D|1|1|1|0|0|0|Vd:4|1|0|1|sz|op|1|M|0|Vm:4 |
| 10796 {0x0fbe0e50, 0x0ebc0a40, 4, arm_VCVTR_EQ_U32_F32, 0x701100108011c04, arm
_instArgs{arm_arg_Sd, arm_arg_Sm_Dm}}, // VCVT<R,><c>.<U,S>3
2.F<32,64> <Sd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|1|1|0|signed|Vd:4|1|0|1|sz|op|1|
M|0|Vm:4 |
| 10797 {0x0fb00e50, 0x0e800a00, 4, arm_VDIV_EQ_F32, 0x8011c04, arm_instArgs{arm
_arg_Sd_Dd, arm_arg_Sn_Dn, arm_arg_Sm_Dm}}, // VDIV<c>.F<32,64> <
Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|1|D|0|0|Vn:4|Vd:4|1|0|1|sz|N|0|M|0|Vm:4 |
| 10798 {0x0f300e00, 0x0d100a00, 4, arm_VLDR_EQ, 0x1c04, arm_instArgs{arm_arg_Sd
_Dd, arm_arg_mem_R_pm_imm8at0_offset}}, // VLDR<c> <Sd,Dd>, [
<Rn>{,#+/-<imm8>}] cond:4|1|1|0|1|U|D|0|1|Rn:4|Vd:4|1|0|1|sz|imm8:8 |
| 10799 {0x0ff00f7f, 0x0e000a10, 4, arm_VMOV_EQ, 0x1c04, arm_instArgs{arm_arg_Sn
, arm_arg_R_12}}, // VMOV<c> <Sn>, <Rt>
cond:4|1|1|1|0|0|0|0|0|Vn:4|Rt:4|1|0|1|0|N|0|0|1|0|0|0|0 |
| 10800 {0x0ff00f7f, 0x0e100a10, 4, arm_VMOV_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12, arm_arg_Sn}}, // VMOV<c> <Rt>, <Sn>
cond:4|1|1|1|0|0|0|0|1|Vn:4|Rt:4|1|0|1|0|N|0|0|1|0|0|0|0 |
| 10801 {0x0fd00f7f, 0x0e100b10, 4, arm_VMOV_EQ_32, 0x1c04, arm_instArgs{arm_arg
_R_12, arm_arg_Dn_half}}, // VMOV<c>.32 <Rt>, <
Dn[x]> cond:4|1|1|1|0|0|0|opc1|1|Vn:4|Rt:4|1|0|1|1|N|0|0|1|0|0|0|0 |
| 10802 {0x0fd00f7f, 0x0e000b10, 4, arm_VMOV_EQ_32, 0x1c04, arm_instArgs{arm_arg
_Dn_half, arm_arg_R_12}}, // VMOV<c>.32 <Dd[x]>
, <Rt> cond:4|1|1|1|0|0|0|opc1|0|Vd:4|Rt:4|1|0|1|1|D|0|0|1|0|0|0|0 |
| 10803 {0x0fb00ef0, 0x0eb00a00, 4, arm_VMOV_EQ_F32, 0x8011c04, arm_instArgs{arm
_arg_Sd_Dd, arm_arg_imm_vfp}}, // VMOV<c>.F<32,64> <
Sd,Dd>, #<imm_vfp> cond:4|1|1|1|0|1|D|1|1|imm4H:4|Vd:4|1|0|1|sz|0|0|0|0|imm4L:4 |
| 10804 {0x0fbf0ed0, 0x0eb00a40, 4, arm_VMOV_EQ_F32, 0x8011c04, arm_instArgs{arm
_arg_Sd_Dd, arm_arg_Sm_Dm}}, // VMOV<c>.F<32,64> <
Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|0|0|0|Vd:4|1|0|1|sz|0|1|M|0|Vm:4 |
| 10805 {0x0fff0fff, 0x0ef10a10, 4, arm_VMRS_EQ, 0x1c04, arm_instArgs{arm_arg_R_
12_nzcv, arm_arg_FPSCR}}, // VMRS<c> <Rt_nzcv>,
FPSCR cond:4|1|1|1|0|1|1|1|1|0|0|0|1|Rt:4|1|0|1|0|0|0|0|1|0|0|0|0 |
| 10806 {0x0fff0fff, 0x0ee10a10, 4, arm_VMSR_EQ, 0x1c04, arm_instArgs{arm_arg_FP
SCR, arm_arg_R_12}}, // VMSR<c> FPSCR, <Rt
> cond:4|1|1|1|0|1|1|1|0|0|0|0|1|Rt:4|1|0|1|0|0|0|0|1|0|0|0|0 |
| 10807 {0x0fb00e50, 0x0e200a00, 4, arm_VMUL_EQ_F32, 0x8011c04, arm_instArgs{arm
_arg_Sd_Dd, arm_arg_Sn_Dn, arm_arg_Sm_Dm}}, // VMUL<c>.F<32,64> <
Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|1|0|Vn:4|Vd:4|1|0|1|sz|N|0|M|0|Vm:4 |
| 10808 {0x0fbf0ed0, 0x0eb10a40, 4, arm_VNEG_EQ_F32, 0x8011c04, arm_instArgs{arm
_arg_Sd_Dd, arm_arg_Sm_Dm}}, // VNEG<c>.F<32,64> <
Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|0|0|1|Vd:4|1|0|1|sz|0|1|M|0|Vm:4 |
| 10809 {0x0fb00e10, 0x0e100a00, 4, arm_VNMLS_EQ_F32, 0x60108011c04, arm_instArg
s{arm_arg_Sd_Dd, arm_arg_Sn_Dn, arm_arg_Sm_Dm}}, // VN<MLS,MLA><c>.F<3
2,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|0|1|Vn:4|Vd:4|1|0|1|sz|N|op|M
|0|Vm:4 |
| 10810 {0x0fb00e50, 0x0e200a40, 4, arm_VNMUL_EQ_F32, 0x8011c04, arm_instArgs{ar
m_arg_Sd_Dd, arm_arg_Sn_Dn, arm_arg_Sm_Dm}}, // VNMUL<c>.F<32,64>
<Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|1|0|Vn:4|Vd:4|1|0|1|sz|N|1|M|0|Vm:4 |
| 10811 {0x0fbf0ed0, 0x0eb10ac0, 4, arm_VSQRT_EQ_F32, 0x8011c04, arm_instArgs{ar
m_arg_Sd_Dd, arm_arg_Sm_Dm}}, // VSQRT<c>.F<32,64>
<Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|0|0|1|Vd:4|1|0|1|sz|1|1|M|0|Vm:4 |
| 10812 {0x0f300e00, 0x0d000a00, 4, arm_VSTR_EQ, 0x1c04, arm_instArgs{arm_arg_Sd
_Dd, arm_arg_mem_R_pm_imm8at0_offset}}, // VSTR<c> <Sd,Dd>, [
<Rn>{,#+/-<imm8>}] cond:4|1|1|0|1|U|D|0|0|Rn:4|Vd:4|1|0|1|sz|imm8:8 |
| 10813 {0x0fb00e50, 0x0e300a40, 4, arm_VSUB_EQ_F32, 0x8011c04, arm_instArgs{arm
_arg_Sd_Dd, arm_arg_Sn_Dn, arm_arg_Sm_Dm}}, // VSUB<c>.F<32,64> <
Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|1|1|Vn:4|Vd:4|1|0|1|sz|N|1|M|0|Vm:4 |
| 10814 {0x0fffffff, 0x0320f002, 4, arm_WFE_EQ, 0x1c04, arm_instArgs{}},
// WFE<c> cond:4|0|0|
1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|0 |
| 10815 {0x0fff00ff, 0x0320f002, 3, arm_WFE_EQ, 0x1c04, arm_instArgs{}},
// WFE<c> cond:4|0|0|
1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|0 |
| 10816 {0x0fffffff, 0x0320f003, 4, arm_WFI_EQ, 0x1c04, arm_instArgs{}},
// WFI<c> cond:4|0|0|
1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|1 |
| 10817 {0x0fff00ff, 0x0320f003, 3, arm_WFI_EQ, 0x1c04, arm_instArgs{}},
// WFI<c> cond:4|0|0|
1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|1 |
| 10818 {0x0fffffff, 0x0320f001, 4, arm_YIELD_EQ, 0x1c04, arm_instArgs{}},
// YIELD<c> cond:4|0|
0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|1 |
| 10819 {0x0fff00ff, 0x0320f001, 3, arm_YIELD_EQ, 0x1c04, arm_instArgs{}},
// YIELD<c> cond:4|0|
0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|1 |
| 10820 {0xffffffff, 0xf7fabcfd, 4, arm_UNDEF, 0x0, arm_instArgs{}},
// UNDEF 1|1|1|1|0|1|
1|1|1|1|1|1|1|0|1|0|1|0|1|1|1|1|0|0|1|1|1|1|1|1|0|1 |
8313 } | 10821 } |
LEFT | RIGHT |