non inline jumptables for arm

lib/Target/ARM/ARMInstrInfo.td

 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file describes the ARM instructions in TableGen format.
@@ skipping 568 matching lines @@
 //  Control Flow Instructions.
 //
 
 let isReturn = 1, isTerminator = 1 in
   def BX_RET : AI<(outs), (ins), BrMiscFrm, "bx", " lr", [(ARMretflag)]> {
   let Inst{7-4}   = 0b0001;
   let Inst{19-8}  = 0b111111111111;
   let Inst{27-20} = 0b00010010;
 }
 
+// Indirect branches
+let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {

[muth02446, 2009/07/17 21:02:30]

probably only works for amv5 and higher (c.f. code using "blx" below)

+  def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, "bx $dst",
+                  [(brind GPR:$dst)]> {
+    let Inst{7-4}   = 0b0001;
+    let Inst{19-8}  = 0b111111111111;
+    let Inst{27-20} = 0b00010010;
+  }
+}
+
 // FIXME: remove when we have a way to marking a MI with these properties.
 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
 // operand list.
 // FIXME: Should pc be an implicit operand like PICADD, etc?
 let isReturn = 1, isTerminator = 1, mayLoad = 1 in
   def LDM_RET : AXI4ld<(outs),
                     (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
                     LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
                     []>;
 
@@ skipping 908 matching lines @@
 // Floating Point Support
 //
 
 include "ARMInstrVFP.td"
 
 //===----------------------------------------------------------------------===//
 // Advanced SIMD (NEON) Support
 //
 
 include "ARMInstrNEON.td"