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Issue 946042: [PATCH] Trap values persist through memory and cause undefined switch behavior (Closed)

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Created:
14 years, 9 months ago by Jeffrey Yasskin
Modified:
14 years, 9 months ago
Reviewers:
llvm-commits, gohman
CC:
chandlerc1, resistor
Base URL:
https://llvm.org/svn/llvm-project/llvm/trunk/
Visibility:
Public.

Description

Clarify that a trap value stored to memory stays a trap value after it's loaded back into a register, even though the side effect (for example, from a volatile store) is still undef. Also extend trap values to cause undefined behavior when they control a conditional branch or switch. This is important for switches because it can allow the optimizer to change the default branch to unreachable. If a trap switch argument merely acted like undef, the optimizers couldn't introduce a branch to unreachable. I'm less sure that br(trap) needs to be unreachable, but it seems nicely symmetric.

Patch Set 1 #

Total comments: 2

Patch Set 2 : Tweak store trap wording #

Patch Set 3 : Rearrange examples #

Patch Set 4 : Reorder examples #

Patch Set 5 : s/causes/results in/ #

Unified diffs Side-by-side diffs Delta from patch set Stats (+21 lines, -10 lines) Patch
M docs/LangRef.html View 1 2 3 4 1 chunk +21 lines, -10 lines 0 comments Download

Messages

Total messages: 2
chandlerc
http://codereview.appspot.com/946042/diff/1/2 File docs/LangRef.html (right): http://codereview.appspot.com/946042/diff/1/2#newcode2331 docs/LangRef.html:2331: <p>A <a href="#i_br">br</a> or <a href="#i_switch">switch</a> instruction whose This ...
14 years, 9 months ago (2010-04-25 07:32:25 UTC) #1
Jeffrey Yasskin
14 years, 9 months ago (2010-04-25 07:49:07 UTC) #2
We noticed this when designing the concurrency memory model, but I think it's a
needed refinement regardless.
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